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Experiment#11 Clocked Sequential Circuits and Counters

This document describes an experiment involving the design and testing of synchronous and asynchronous counters. It provides state tables and logic equations for building a synchronous sequential circuit and synchronous counter using JK flip-flops. An asynchronous up/down counter is also presented that counts from 0 to 15 and back using D flip-flops. In conclusion, the key differences between synchronous and asynchronous counters are discussed, with synchronous counters avoiding propagation delays through clocking and asynchronous counters not requiring a clock signal.

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113 views8 pages

Experiment#11 Clocked Sequential Circuits and Counters

This document describes an experiment involving the design and testing of synchronous and asynchronous counters. It provides state tables and logic equations for building a synchronous sequential circuit and synchronous counter using JK flip-flops. An asynchronous up/down counter is also presented that counts from 0 to 15 and back using D flip-flops. In conclusion, the key differences between synchronous and asynchronous counters are discussed, with synchronous counters avoiding propagation delays through clocking and asynchronous counters not requiring a clock signal.

Uploaded by

fahad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EXPERIMENT#11

Clocked sequential circuits and counters


Objective

-to design, build and test synchronous sequential circuits.

-to design, build and test synchronous counters.

-to design, build and test asynchronous counters.

Apparatus

-IC type 7476 dual JK master-slave flip-flop.

-IC type 7400 quad 2-input NAND gates.


Part 1: synchronous sequential circuit

Part a
Present state input Next state output Flip-flop input functions
0 0 0 0 1 0 0 X 1 X
0 0 1 1 0 1 1 X 0 X
0 1 0 0 1 0 0 X X 0
0 1 1 1 0 1 1 X X 1
1 0 0 1 0 0 X 0 0 X
1 0 1 0 0 0 X 1 0 X
1 1 0 X X X X X X X
1 1 1 X X X X X X X

JA= X NOT self correcting


KA =X
JB=A'X'
KB=X
Present state input Next state output Flip-flop input functions
0 0 0 0 1 0 0 X 1 X
0 0 1 1 0 1 1 X 0 X
0 1 0 0 1 0 0 X X 0
0 1 1 1 0 1 1 X X 1
1 0 0 1 0 0 X 0 0 X
1 0 1 0 0 0 X 1 0 X
1 1 0 0 0 0 X 1 X 1
1 1 1 0 0 0 X 1 X 1

JA= X Self correcting


KA =B+X
JB=A'X'
KB=X+AB
Part 2: Synchronous counter

Present state Next state Flip-flop input functions


A B A B JA KA JB KB
0 0 0 1 0 X 1 X
0 1 1 1 1 X X 0
1 1 1 0 X 0 X 1
1 0 0 0 X 1 0 X

JA= B
KA =B'
JB=A'
KB=A
Part 3: asynchronous counters

Up count 0-15

A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
down count 15-0

A B C D
15 1 1 1 1
14 1 1 1 0
13 1 1 0 1
12 1 1 0 0
11 1 0 1 1
10 1 0 1 0
9 1 0 0 1
8 1 0 0 0
7 0 1 1 1
6 0 1 1 0
5 0 1 0 1
4 0 1 0 0
3 0 0 1 1
2 0 0 1 0
1 0 0 0 1
0 0 0 0 0
Conclusion

-synchronous counter is also known as parallel counter.

- synchronous counter eliminates the propagation delay problem that


can be overcome by lookahead logic.

- synchronous counter starts with state diagram, state table, K-maps


and the circuit.

-asynchronous counters can easily be made from toggle or D flip-flop.

- asynchronous counters do not require clock signal to change the


output.

- asynchronous counters are sometimes called ripple counters because


the data appears to " ripple " from the output of one flip-flop to the
input of the next.

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