Topic 5

Arithmetic & Logic instructions

ISMAIL ARIFFIN
ECE,FKE,UTM, SKUDAI, JOHOR
2018
Data Processing
 Data Processing

• Arithmetic operations:
– ADD, ADC, ADIW, SUB, SBC, MUL, MULS, EXT, NEG.

• Logical
– AND, OR, EOR, NOT

• Shift
– ASL, ASR, LSL, LSR, ROL, ROR, ROXL, ROXR.

• Bit operations:
– BCLR, BSET, BCHG, BTST
Data Processing: Arithmetic
Operations
AVR Arithmetic Instruction
 Arithmetic Result and Indicator
Register = result
SREG = indicator of arithmetic condition
SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Half carry N+V

Result indicator or flag or condition

C = 1, the result was too big for unsigned number
Z = 1, the result was exactly zero
N = 1, the result is negative for signed number, msb result= 1
V = 1, the result was too big for signed number
S= 1 = N xor V
H= 1, a carry bit from bit 3 to bit 4
T = 1, a temporary storage for one bit
I = 1, to enable interrupt to happen
 SREG:
Status Register (SREG)
I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Data Address
Half carry N+V Space
Example:Show
Example:
Example:
Example: Showthe
Show
Show thestatus
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the statusof
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status ofthe
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the C,H,
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H,
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and
and
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flags afterthe
after
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the
the addition
$0001 General
subtraction
subtraction
of
of 0x9C of
of 0x9C
0x23
0x73 from
from
from 0x9C
0xA5
0x52 in
in the
the following
following
0x64 in the following instructions:
0x38 and 0x2F instructions:
instructions:
Purpose

...
LDI LDILDI 0x38
LDI
R16, R20, 0x9C
R20,
R20, 0x9C
0xA5
0x52;R16 = 0x38 Registers
R0 $001F IO Address
ALU LDI LDI 0x2F
LDI
LDI
R17, R21, 0x64
R21,
R1
R21, 0x9C
0x23
0x73
;R17 = $0020
0x2F TWBR $00
TWSR $01
R2
SUB R17R20,
R20, R21
R21;add R17;addStandard IO R21 from R20
;subtract
ADD SUB
ADD
R16, R20, R21 ;subtract
R21 toR21
to Registers
R16 R20from R20

...
...
…

SPH $3E
SREG: I T H S V N Z C
Solution:
Solution:
Solution: R15 11
$005F SREG $3F

CPU
Solution:
$52
$9C
$A5
$38
$9C
- $23
$73
0101
R16 0010
1001
1010
0011
1001
0111
$0060
1100
0101
1000
1100
R17 0011
General
purpose
...
+-- +$64
$9C
$2F 10010100
0010
0110 1100
0011
1111 RAM
PC $DF 1101 1111 R20 = $DF
…

$00
$82
$67
$100 1 0000
1000
0110
0000 0000
0010
0111
0000 R20
R20
R16
R20 ==
= $00
$82
0x67
00
(SRAM)
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CC===100because
C becausethere
because R21 is
R21 is not
isnot
R30 bigger
bigger
a carry than R20
than
beyond R20 andbit.
and
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there is no
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bit.
Z
C == 00 decoder
because
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Instruction
ZZ =
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01 because
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other
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D4 bit.
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the toto
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the D4 bit.
ZH
H == 00 because
because there
there is
is no
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borrow from
from D4
D4 to
to D3.
D3.
Z = 0 because the R16 (the result) has a value 0other
= 1 because
Instruction Register the R20 (the
registers
result) has a value in it after
than 0 the addition.
after the addition.
$FFFF
 ADD: Add Without Carry
o ADD instruction is used to adds two registers without the C Flag
and place the result in the destination register, Rd.

o Example:

o Result in Rd and result condition indicated in flags (SREG)

Flag affected : H, S, V, N, Z, C
CPU cycle: 1
 ADD: Example
Show the status of the C, H and Z flags after the addition
of 0x38 and 0x2F in the following instruction:
LDI R16, 0x38
LDI R17, 0x2F
ADD R16, R17
Solution:
$38 0011 1000
+ $2F 0010 1111 R16 = 0x67
R16 $67 0110 0111

C = 0 because there is no carry beyond the bit7

H = 1 because there is a carry from the bit 3 to bit 4
Z = 0 because the R16 (the result) has a value other than 0 after the
addition.
 ADD: Example
Show the status of the C, H and Z flags after the addition of 0x9C and
0x64 in the following instruction:
LDI R20, 0x9C
LDI R21, 0x64
ADD R20, R21 ;add R21 to R20
Solution:
$9C 1001 1100
+ $64 0110 0100 R20 = 0x00
R20 $100 0000 0000

C = 1 because there is a carry beyond the bit7

H = 1 because there is a carry from the bit 3 to bit 4
Z = 1 because the R20 (the result) has a value of 0 after the addition.
 ADC: Add With Carry
o ADC instruction is used to adds two registers and the contents of
the C Flag and place the result in the destination register, Rd.

o Example:

Flag affected : H, S, V, N, Z, C
CPU cycle: 1
ADC: Example
 ADIW: Add Immediate to Word
o ADIW instruction is used to adds and immediate value (0-63) to a
register pair and place the result in the register pair.

o Example:

Flag affected : S, V, N, Z, C
CPU cycle: 2
 ADIW: Example

LDI ZL, 13 • 13 is added to ZL

• If the result is > 255 the carry bit is set, and ZH
LDI ZH, 53
incremented by 1

ADIW R30, 26 • If ZH is > 255, the carry bit in the SREG is set

Solution

• ZL = 13 = 0b 0000 1101
• ZH = 53 = 0b 0011 0101
After adding 26 = 0b 0001 1010
• ZL = 13 + 26 = 39 = 0b 0010 0111 is < 255, the carry bit will not set
• ZH = 53 = 0b 0011 0101 unchanged and the carry bit in SREG is not
set
 SUB: Subtract without Carry
o SUB instruction is used to subtracts two registers and places the
result in the destination register, Rd

o Example:

Flag affected : H,S, V, N, Z, C

CPU cycle: 1
SUB: Example
 SUBI: Subtract Immediate
o SUBI instruction is used to subtracts a register with a constant
value and d places the result in the destination register, Rd

o Example:

Flag affected : H,S, V, N, Z, C

CPU cycle: 1
SUBI: Example
 SBIW: Subtract Immediate from Word
o SBIW instruction is used to subtracts an immediate value (0-63)
from a register pair and place the result in the register pair.

o Example:

Flag affected : S, V, N, Z, C
CPU cycle: 2
SBIW: Example
 SBC: Subtract with Carry
o SBC instruction is used to subtracts two registers and subtracts
with the C Flag and places the results in the destination registers,
Rd.

o Example:

Flag affected : H,S, V, N, Z, C

CPU cycle: 1
SBC: Example
 SBCI: Subtract Immediate with Carry
o SBCI instruction is used to subtracts a constant from a register and
subtract with the C Flag and place the result in the destination
register, Rd.

o Example:

Flag affected : H, S, V, N, Z, C
CPU cycle: 1
 MUL: Multiply Unsigned
o MUL instruction perform 8-bit x 8-bit  16-bit unsigned
multiplication.

o Example:

Flag affected : Z, C
CPU cycle: 2
 MULS: Multiply Signed
o MULS instruction perform 8-bit x 8-bit  16-bit signed
multiplication.

o Example:

Flag affected : Z, C
CPU cycle: 2
 What is Signed and Unsigned numbers?
o In signed 8-bit operands, D7 (MSSB) is the sign, and D0 to D6 are
magnitude.
o If D7 = 0, operand is positive.
o The range of positive numbers are 0 to +127.
o If positive number larger than +127, a 16-bit operand must be used.

o If D7 = 1, operand is negative.
o The magnitude is represented in 2’s compliment.
What is Signed and Unsigned numbers?
What is Signed and Unsigned numbers?
 MULSU: Multiply Signed with Unsigned
o MULSU instruction perform 8-bit x 8-bit  16-bit multiplication of
a signed and unsigned number.

Flag affected : Z, C
CPU cycle: 2
 INC: Increment
o INC instruction used to adds one (1) to the contents of register Rd
and place the result in the destination register Rd.

o Example:

Flag affected : S,V, Z, C

CPU cycle: 1
 DEC: Decrement
o DEC instruction used to subtract one (1) to the contents of register
Rd and place the result in the destination register Rd.

o Example:

Flag affected : S,V, Z, C

CPU cycle: 1
Data Processing: Logic Operations
 AND: Logical AND
o AND instruction performs the logical AND between the contents of
Rd and Rr and place the result in destination register, Rd.

o Example:

Flag affected : S,V, N, Z,

CPU cycle: 1
 ANDI: Logical AND with Immediate
o ANDI instruction performs the logical AND between the contents
of register Rd and a constant and place the result in destination
register, Rd.

o Example:

Flag affected : S,V, N, Z,

CPU cycle: 1
 OR: Logical OR
o OR instruction performs the logical OR between the contents of
register Rd and register Rr and place the result in destination
register, Rd.

o Example:

Flag affected : S,V, N, Z,

CPU cycle: 1
 ORI: Logical OR with Immediate
o ORI instruction performs the logical OR between the contents of
register Rd and a constant and place the result in destination
register, Rd.

o Example:

Flag affected : S,V, N, Z,

CPU cycle: 1
 EOR: Exclusive OR
o EOR instruction performs the logical Exclusive OR between the
contents of register Rd and register Rr and place the result in
destination register, Rd.

o Example:

Flag affected : S,V, N, Z,

CPU cycle: 1
 COM: One’s Complement
o COM instruction performs a One’s complement of register, Rd.

o Example:

Flag affected : S,V, N, Z, C

CPU cycle: 1
 NEG: Two’s Complement
o NEG instruction replace the contents of register Rd with its two’s
complement.

o Example:

Flag affected : H, S,V, N, Z, C

CPU cycle: 1
 SBR: Set Bits in Register
o SBR instruction sets specified bits in register Rd. Perform the
logical ORI between contents of register Rd and constant value and
places the result in destination register, Rd.

o Example:

Flag affected : S,V, N, Z

CPU cycle: 1
 CBR: Clear Bits in Register
o CBR instruction clear specified bits in register Rd. Perform the
logical AND between contents of register Rd and constant value
and places the result in destination register, Rd.

o Example:

Flag affected : S,V, N, Z

CPU cycle: 1
 TST: Test for Zero or Minus
o TST instruction tests if a register is zero or negative. Perform a
logical AND between a register itself.

o Example:

Flag affected : S, V, N, Z
CPU cycle: 1
 SWAP: Swap Nibbles
o SWAP instruction swaps high and low nibbles in a register.

o Example:

Flag affected : None

CPU cycle: 1
 NOP: No Operation
o NOP instruction performs a single cycle No Operation.

o Example:

Flag affected : None

CPU cycle: 1
Exercise Problems
 Exercise Problem
o Write a program to add two 16-bit numbers: 2762H + 1296H. Place
the results in R26 and R27; R26 should have the lower byte.

o Solution:
LDI R16, 0x62 ;low byte R16 = 62H
LDI R17, 0x27 ;high byte R17 = 27H
LDI R26, 0x96 ;low byte R26 = 96H
LDI R27, 0x12 ;high byte R27 = 12H
ADD R26, R16 ;R26 = R26 + R16 = 96H + 62H = F8H, C=0, H=O,
Z=0
ADC R27, R17 ;R27 = R27 + R17 + C = 12H + 27H + 0 = 39H
 Exercise Problem
o Write a program to add 18H and 2917H. Place the results in R25
and R24; R24 should have the lower byte.

o Solution:
LDI R24, 0x17 ;low byte R24 = 17H
LDI R25, 0x29 ;high byte R29 = 29H
ADIW R24, 0x18 ;R25:R24 = R25:R24 + 18H = 2917H + 18H = 292FH
 Exercise Problem
o Write a program to multiplies 25H by 65H, and give the answer.

o Solution:
LDI R23, 0x25 ;load R23 = 25H
LDI R24, 0x65 ;load R24 = 65H
MUL R23, R24 ; R1:R0 = R23 x R24 = 25H x 65H = E99H
 Exercise Problem
o Write a program to multiply 25H by 65H, and give the answer.

o Solution:
LDI R23, 0x25 ;load R23 = 25H
LDI R24, 0x65 ;load R24 = 65H
MUL R23, R24 ; R1:R0 = R23 x R24 = 25H x 65H = E99H
 Exercise Problem
o Write a program to multiply two numbers as below and give the
answer.
a) F7H and 02H (both unsigned number)
b) F7H and 02H (both signed number)
c) F7H (signed) and 02H (unsigned)

o Solution (a):
LDI R23, 0xF7 ;load R23 = F7H (unsigned number)
LDI R24, 0x02 ;load R24 = 02H (unsigned number)
MUL R23, R24 ; R1:R0 = R23 x R24 = F7H x 02H = IEEH
 Exercise Problem
o Solution (b):
LDI R23, 0xF7 ;load R23 = F7H (signed number)
LDI R24, 0x02 ;load R24 = 02H (signed number)
MULS R23, R24 ; R1:R0 = R23 x R24 = F7H x 02H = -9x2 = -18
= FFEEH

o Solution (c):
LDI R22, 0xF7 ;load R22 = F7H (signed number)
LDI R23, 0x02 ;load R23 = 02H (unsigned number)
MULSU R22, R23 ; R1:R0 = R22 x R23 = F7H x 02H = -9x2 = -18
;=FFEEH
 Exercise Problem
o Show the result of following instructions:
LDI R20, 0x04 ;load R20 = 04H
ORI R20, 0x30 ;R20 = R20 OR 30H

o Solution:
 Exercise Problem
o Show the result of following instructions:
LDI R20, 0x35 ;load R20 = 35H
ANDI R20, 0x0F ;R20 = R20 AND 0FH

o Solution:
 Exercise Problem
o Show the result of following instructions:
LDI R20, 0x54 ;load R20 = 54H
LDI R21, 0x78 ;load R21 = 78H
EOR R20, R21 ;R20 = R20 EOR R21

o Solution: