4.empat (Encoder Decoder)
4.empat (Encoder Decoder)
CCE61206
Pemrograman FPGA
Agenda
• Introduction
• Review Sistem Digital
• FPGA design dengan Xilinx
• Rangkaian kombinasional
• Rangkaian Decoder, Encoder, Multiplekser, Demux
• Rangkaian sekuensial (counter)
• -----------------------------------UTS-------------------------------------
• Desain project dan presentasi
• -----------------------------------UAS-------------------------------------
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Review tugas sebelumnya
- Kasus > tabel kebenaran > K-maps > persamaan logika > koding
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DECODER
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Decoder
A decoder has
▪ N inputs
▪ 2N outputs
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Decoder
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Decoder 3 to 8 in VHDL
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Simplified into …
MSB MSB
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ENCODER
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Encoder
An encoder has
− 2N inputs
− N outputs
⚫ An encoder outputs the binary value of the selected (or active) input.
⚫ An encoder performs the inverse operation of a decoder.
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⚫ Issues
− What if more than one input is active?
− What if no inputs are active?
Priority Encoders
⚫ If more than one input is active, the higher-order input has priority over the lower-order input.
− The higher value is encoded on the output
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− Output is valid when at least one input is active
d=1
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Priority Encoder 4 to 2 in VHDL
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4 cara conditional programming
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CONCURRENT ASSIGNMENT STATEMENTS
1. Conditional signal assignment
2. Selected signal assignment
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1. Conditional signal assignment statement
Contoh:
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1. Conditional signal assignment statement
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2. Selected signal assignment statement
Contoh:
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2. Selected signal assignment statement
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ROUTING CIRCUIT WITH IF AND CASE STATEMENTS (sequential method)
3. IF statements
4. Case statements
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3. If statement
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Concurrent method Sequential method
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4. Case statement
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Concurrent method Sequential method
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4. Case statement
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4 cara conditional programming
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Tugas Kelompok minggu 4
Buat program VHDL untuk kasus minggu lalu (komparator) dg kriteria:
1. Memilih salah satu dari 4 cara conditional programming
2. Jadikan input switch menjadi vektor (bus) yakni bilangan_A (2 bit)
dan bilangan_B (2 bit)
3. Atur plan Ahead dg site bebas, silakan pilih sesuai alamat site gambar
di bawah ini
4. Lakukan simulasi dan bandingkan dengan gambar timing diagram
hasil simulasi dengan tugas kelompok minggu lalu
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