Lab 04

Adder and Subtractor

(加減法器)
Adder
Half-Adder
Adding two single-bit binary values, X, Y produces a sum
S bit and a carry out C-out bit.
This operation is called half addition and the circuit to
realize it is called a half adder.

C-out S
 Half Adder Truth Table
X Half S Inputs Outputs
Y Adder C-OUT
X Y S C-out
(a) Block Diagram 0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

74LS86
X
Sum S
Y
S (X, Y) = X’Y + XY’=X Y
C-out (X, Y) = XY
C-out

74LS08
 Full Adder
Adding two single-bit binary values, X, Y with a carry input
bit C-in produces a sum bit S and a carry out C-out bit.

Full Adder Truth Table S(X,Y, C-in) = S (1,2,4,7)

Inputs Outputs
C-out(x, y, C-in) = S (3,5,6,7)
X Y C-in S C-out Sum S X
XY
0 0 0 0 0 C-in 00 01 11 10
0 0 1 1 0 0 2 6 4
0 1 1
0 1 0 1 0
1 3 7 5
0 1 1 0 1 1 1 1 C-in

1 0 0 1 0
1 0 1 0 1 Carry C-out
Y
X
1 1 0 0 1 XY
1 1 1 1 1 C-in 00 01 11 10
0 2 6 4
0 1
S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in)
1 3 7 5
S = X  Y  (C-in) 1 1 1 1 C-in

C-out = XY + X(C-in) + Y(C-in)

Y
 S = X  Y  (C-in)
C-out = XY + X(C-in) + Y(C-in)

X Y Y Sum S
C-in

Full
C-out C-in
Adder X
XY

Y
S
X
XC-in C-out
C-in

C-in YC-in
Subtractor
Half Subtractor
Half-Subtractor
 Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces a
difference bit D and a borrow out bit B-out.
 This operation is called half subtraction and the circuit to realize it is called a
half subtractor.
B-out

D
 Half Subtractor Truth Table
X Inputs Outputs
Half D
Y Subtractor B-OUT X Y D B-out
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

D(X,Y) = S (1,2)
D = X’Y + XY’ = X  Y 74LS86
X Difference D
Y
B-out(x, y, C-in) = S (1)
B-out = X’Y
B-out

74LS08
 Full Subtractor
Subtracting two single-bit binary values, Y, B-in from a
single-bit value X produces a difference bit D and a borrow
out B-out bit. D(X,Y, B-in) = S (1,2,4,7)
B-out(x, y, B-in) = S (1,2,3,7)
Full Subtractor Truth Table
Inputs Outputs Difference D X
XY
X Y B-in D B-out B-in 00 01 11 10
0 6
0 0 0 0 0 0
2
1
4
1
0 0 1 1 1 1 3 7 5
0 1 0 1 1 1 1 1 B-in

0 1 1 0 1
Y
1 0 0 1 0 Borrow B-out X
1 0 1 0 0 XY

1 1 0 0 0 B-in 00 01 11 10
0 2 6 4
1 1 1 1 1 0 1
1 3 7 5
D = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in) 1 1 1 1 B-in
D = X  Y  (B-in)
B-out = X’Y + X’(B-in) + Y(B-in) Y
Four-Bit Adder / Subtractor
4-bit Adder

If mode M=0, Bn 0 = Bn , C0=0, S0 = A+B

4-bit Subtractor

If mode M=1, Bn 1 = Bn’, C0=1, A+(-B) = A-B where Bn’=-Bn if

2’s complement is considered.
Carry out (進位輸出)
 In adder mode, carry out C4 will be 1 when sum > 15
(在加法時，總和超過15時，進位輸出為1)
 In sub. mode, if A ≥ B, C4 will be 1; if A<B, C4 will be 0
(answer of subtract is 2’s complement of A-B).
(減法時，若A >= B，進位輸出為1，若A < B，減法得到
A – B之後2的補數，進位輸出為0)
Example 1.7
Given the two binary numbers X = 1010100 and Y = 1000011, perform the
subtraction (a) X – Y and (b) Y  X by using 2's complement.

There is no end carry.

Therefore, the answer is Y
– X =  (2's complement
of 1101111) =  0010001.
 Lab (實驗說明)
I. Implement 1 bit half adder/subtractor by XOR
(IC7486) and AND (7408) gates. Half Adder Truth Table
Inputs Outputs
74LS86
Sum S
X Y S C-out
X
0 0 0 0
Y
C-out
0 1 1 0
1 0 1 0
1 1 0 1
74LS08
Half Subtractor Truth Table
74LS86 Inputs Outputs
X
Difference D
Y X Y D B-out
B-out 0 0 0 0
0 1 1 1
74LS08 1 0 1 0
1 1 0 0
A. Follow the cable requirements in Lab 03 Part II. (
接線方式與顏色使用， 請依照Lab03 Part II的要
求)
B. 使用零件 (請勿自行增加零件)
7486 (XOR) x 1
7408 (AND) x 1
LED x2
C. 利用 XOR 與另一個訊號源 (0 or 1, mode) 整合
single-bit 加法器的X與減法器的NOT gate (X’)，
成為單一電路。
a) 手動調整mode的0 或 1
b) 當mode=0時，電路執行加法功能
c) 當mode=1時，電路執行減法功能
D. No Quartus II simulation for Part I.
II. Implement 4 bits full adder using IC 74283 or
7483 and XOR(7486)

⚫If mode=0, the circuit will into adder mode 當輸入0為加法

⚫If mode=1, the circuit will into sub. mode 當輸入1為減法
A. Components
7486 (XOR) x 1
7483 or 74283 (4-bit adder/subtractor) x 1
LED x 5
B. Circuit Requirements
Follow the cable requirements in Lab 03 Part II. (接線方式
與顏色使用， 請依照Lab03 Part II的要求)
One select mode (模式選擇mode 一個輸入)
Tow sets of inputs: A1~A4, B1~B4
Connect four sum outputs, S1~S4, to LEDs
Connect the carry output, C4, to one LED.
Arrange LEDs in order (LED請依序排列)
C. Perform the decimal calculations: 9+5、8+8, 9-5
and 9-11.
D. Quartus II Simulation
Use the IC 7486 and IC 7483 in your simulation.
模擬波形時間長度為50ns， 高低電壓波形請依照9+5、
8+8, 9-5 and 9-11設定 (高電壓為 1)
成功下載到DE1，並且可展示9+5、8+8, 9-5 and 9-11的
正確結果。
 實驗繳交項目
 請先使用IC檢查麵包板，檢查所領到的7486與7408
是否完全正常。
 完成上述Part I and II後，舉手請助教檢查並登記。
 實驗報告
 請參考課程網站的實驗報告範本
 報告需包含實作麵包板電路結果照片、開發板展示照片
、計算結果與範本中的要求項目
 需繳交紙本報告
 繳交日期：
 2021/04/09 14:10 (B班)
 2020/04/12 15:10 (A班)