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    VLSI Testing Advanced VLSI Design Lab IIT Kharagpur: System Specs/BM Models/Schematic

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    Rarun Arun
    This document summarizes research being conducted on efficient testing of system-on-a-chip integrated circuits. The research team is exploring techniques like genetic algorithm-based scan chain design and test scheduling to reduce power consumption and test time. They are also investigating test data compression methods like Huffman coding to reduce the memory requirements of test equipment. The overall goal is to address the testing challenges of advanced SOC designs with hundreds of embedded cores in a single chip.

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    VLSI Testing Advanced VLSI Design Lab IIT Kharagpur: System Specs/BM Models/Schematic

    Uploaded by

    Rarun Arun
    84 views4 pages
    This document summarizes research being conducted on efficient testing of system-on-a-chip integrated circuits. The research team is exploring techniques like genetic algorithm-based scan chain design and test scheduling to reduce power consumption and test time. They are also investigating test data compression methods like Huffman coding to reduce the memory requirements of test equipment. The overall goal is to address the testing challenges of advanced SOC designs with hundreds of embedded cores in a single chip.

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    This document summarizes research being conducted on efficient testing of system-on-a-chip integrated circuits. The research team is exploring techniques like genetic algorithm-based scan chain design and test scheduling to reduce power consumption and test time. They are also investigating test data compression methods like Huffman coding to reduce the memory requirements of test equipment. The overall goal is to address the testing challenges of advanced SOC designs with hundreds of embedded cores in a single chip.

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    84 views4 pages

    VLSI Testing Advanced VLSI Design Lab IIT Kharagpur: System Specs/BM Models/Schematic

    Uploaded by

    Rarun Arun
    This document summarizes research being conducted on efficient testing of system-on-a-chip integrated circuits. The research team is exploring techniques like genetic algorithm-based scan chain design and test scheduling to reduce power consumption and test time. They are also investigating test data compression methods like Huffman coding to reduce the memory requirements of test equipment. The overall goal is to address the testing challenges of advanced SOC designs with hundreds of embedded cores in a single chip.

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    of 4

    VLSI Testing

    Advanced VLSI design Lab


    IIT Kharagpur
    Activity: On-Line Testing of Digital and Mixed Signal VLSI Circuits
    Team Members: Rahul Bhattacharya, Santosh Biswas, Prof. A Patra, Prof. S Mukhopadhyay,
    Contact Email: [email protected]

    Brief Summary: Issues related to on-line testing (OLT) are increasingly becoming important in modern
    electronic systems. These needs have increased dramatically in recent times because with the widespread
    usage of deep submicron technology, there is a rise in the probability of development of transient and
    pattern sensitive faults. Classical techniques of performing burn-in tests after production and deploying the
    circuit in the system with the assumption of fault free behavior henceforth are no longer valid. Timely and
    efficient detection of such faults requires departure from traditional test methodologies. OLT can be
    defined as the procedure to enable integrated circuits to verify the correctness of their functionality during
    normal operation by checking whether the response of the circuit conforms to its normal dynamic model.
    Extensive research is carried out by the test team of the laboratory, in this area for Digital and Mixed
    Signal Circuits. “OLM_MAX”: A cad tool for OLT has been developed and is validated by design,
    fabrication and testing of chips in 0.18 micron technology.

    System Specs/BM Models/Schematic


    Hybrid Automata
    For Individual Subsystems

    HA for the Normal Fault Models at


    Composition Operation And Faulty dynamic Model of Subsystems
    The System Level
    Active Testing

    Stimulants (TPs) Tester/BIST/On-board DFT Tap Points of the


    Signals applied by LA System Circuitry Circuit
    or AWG and Scope by Tester

    Silicon Silicon Tested


    Mismatch

    No
    Yes

    Diagnose faults/Switch to normal module


    Based on Diagnoser Reports

    Flow for OLT of Mixed Signal Circuits


    OLT of a DC-DC Buck Converter

    Achievements:
    1. About 40 publications in last 4 years in International Journals and Conferences
    2. Pre-conf tutorials at International and National conferences
    3. Infineon India best thesis award 2005 ( masters degree)
    4. Talks at VLSI Industries and International Universities

    Activity: Concurrent Test Program Development and Validation for Mixed Signal circuits using
    Behavioral Models
    Team Members: Rahul Bhattacharya, Santosh Biswas, Prof. A Patra, Prof. S Mukhopadhyay,
    Email Contact: [email protected]
    Mentoring Organizations: National Semiconductor Corp. USA, Tessolve India

    Brief Summary: Test plan starts only during final phases of the design, after the designer provides the
    specs to be met, the design schematic, pinmap etc. Test engineers being on the latter phase of the “design
    & test” flow, they have a higher pressure to meet the deadlines compared to designers. This project
    attempts to use Behavioral Models (BM) to facilitate the test engineer to plan the test before the schematic
    design has started and handshaking with the design engineer at intermediate stages in the flow. As BMs are
    faster in simulation they may be used to model the chip, ATE, Load board, probes, board components etc.
    that would enable the test engineer to validate the test environment by simulation. Research in this area has
    been initiated with collaboration from VLSI Test industries.
    Traditional Test Flow

    Concurrent Design and Test Programming cum Validation


    Activity: Efficient Testing of System-On-a-Chip – A new VLSI Manufacturing Paradigm
    Team Members: Chandan Giri, Prof. S. Chattopadhyay, B. Mallikarjuna Rao, B. Naveen Kumar and
    Dilip Kumar Reddy Tipparthi
    Contact Email: {chandan,santanu}@ece.iitkgp.ernet.in, [email protected],
    [email protected] and [email protected]

    Brief Summary: In order to fully exploit the capabilities of the advanced process technology and at the
    same time to meet the product development schedules semiconductor manufacturing industry is capable of
    integrating pre-designed and pre-verified IP cores to build an entire system on chip. This design paradigm
    has led to an unprecedented increase in test costs like test access to embedded cores, long test
    development, long test application time and high test data volume and also power consumption during test.
    For low cost testing scan chain design strategy using Genetic algorithm (GA) is consider for both single
    and multiple scan chain design. This method considers both reduction of power consumption and delay
    simultaneously, where previous works for scan chain design considered power and delay separately. Upto
    70% improvement in power reduction and 17.6% delay reduction can be achieved with the proposed
    method for single scan chain design and for multi scan chain design upto 78% improvement in power
    reduction and 98% delay reduction can be achieved. To reduce test application time we proposed a GA
    based test scheduling approach for hierarchical cores instead of flat core, which makes more sense in
    current day scenario. Same approach is used for both non-interactive and interactive design transfer model.
    Method shows test time improvement upto 52% for non-interactive case and 43% for interactive case over
    recently proposed method. To consider power constrained scheduling of the cores a pre-processing
    algorithm has been proposed. It is noted that all the previous works for power constrained scheduling was
    considered for flat cores only. For reduction of tester data memory, which contribute significantly the test
    cost two test data compression method namely Huffman Coded Dictionary (HCD) and Split-VIHC
    (SVIHC) has been proposed. In HCD variable length dictionary index is used instead of fixed length
    dictionary, which shows significant improvement in compression ratio with lower decompression hardware
    cost than fixed length dictionary base method. Method SVIHC is proposed to improve the compression
    ratio and test application time over VIHC (Variable length Input Huffman Coding). Upto 6% improvement
    in compression ratio 29% improvement in test application time can be achieved with this SVIHC method
    over VIHC.

    Achievements:
    1. About 8 publications in last 1 year in International Conferences
    2. Pre-conf tutorials at National conferences

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