Unit Iii - Interfacing Memory & Io and Applications of 8086 Microprocessor Static Memory Interfacing
Unit Iii - Interfacing Memory & Io and Applications of 8086 Microprocessor Static Memory Interfacing
Unit Iii - Interfacing Memory & Io and Applications of 8086 Microprocessor Static Memory Interfacing
Introduction : Memory is simply a device that can be used to store the information . • The semiconductor
memories are extensively used because of their small size, low cost, high speed, high reliability & ease of
expansion of the memory size. • It consist of mainly flip-flop & some additional circuitry such as buffers, one flip
flop can hold one bit of data.
Memory fundamentals : Memory capacity . The no. of bits that a semiconductor memory chip can store is called
its chip capacity. • Memory Organization: . Each memory chip contains 2N locations, where N is the no. of
address pins on the chip.
chip will contain 2N x M bits. E.g. for 4K x 4, 212 =4096 locations, each location holding 4 bits, so N=12 & M=4.
1. Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit bank is called ‘odd
address memory bank’ and the lower 8-bit bank is called ‘even address memory bank’.
2. Connect available memory address lines of memory chips with those of the microprocessor and also connect the
memory RD and WR inputs to the corresponding processor control signals. Connect the 16-bit data bus of the
memory bank with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE and Ao are used for decoding the required chip select
signals for the odd and even memory banks. The CS of memory is derived from the output of the decoding circuit.
4. As a good and efficient interfacing practice, the address map of the system should be continuous as far as
possible
Fig shows the interfacing diagram for the memory system
The memory system in this example contains in total four 4Kx8 memory chip. The two 4Kx8 chips of
RAM and ROM are arranged in parallel to obtain 16-bit data bus width. Ao is 0, i.e. the address is even and is in
RAM, then the lower RAM chip is selected indicating 8-bit transfer at an even address. If Ao is 1, i.e. the address
is odd and is in RAM, the BHE goes low, the upper RAM chip is selected, further indicating that the 8-bit transfer
is at an odd address. The selection of chips here takes place as shown in table 2.
PROGRAMMABLE PERIPHERAL INTERFACE 8255
PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its outside world such
as ADC, DAC, keyboard etc. We can program it according to the given condition. It can be used with almost any
microprocessor.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can assign different ports
as input or output functions.
Internal architecture –
It consists of 40 pins and operates in +5V regulated power supply. Port C is further divided into two 4-bit ports i.e.
port C lower and port C upper and port C can work in either BSR (bit set rest) mode or in mode 0 of input-output
mode of 8255. Port B can work in either mode or in mode 1 of
input-output mode. Port A can work either in mode 0, mode 1 or
mode 2 of input-output mode.
It has two control groups, control group A and control group B.
Control group A consist of port A and port C upper. Control
group B consists of port C lower and port B.
Depending upon the value if CS’, A1 and A0 we can select
different ports in different modes as input-output function or
BSR. This is done by writing a suitable word in control register
(control word D0-D7).
Pin diagram –
PA0 – PA7 – Port A contains one 8-bit output latch/buffer
and one 8-bit input buffer.
Data bus buffer(D0 – D7): It is used to connect the internal bus of 8255 with the system bus so as to
establish proper interfacing between the two. The data bus buffer allows the read/write operation to be
performed from/to the CPU.
The buffer allows the passing of data from ports or control register to CPU in case of write operation and
from CPU to ports or status register in case of read operation.
Read/ Write control logic: This unit manages the internal operations of the system. This unit holds the
ability to control the transfer of data and control or status words both internally and externally.
Whenever there exists a need for data fetch then it accepts the address provided by the processor through
the bus and immediately generates command to the 2 control groups for the particular operation.
Group A and Group B control: These two groups are handled by the CPU and functions according to the
command generated by the CPU. The CPU sends control words to the group A and group B control and
they in turn sends the appropriate command to their respective port.
As we have discussed that group A has the access of the port A and higher order bits of port C. While
group B controls port B with the lower order bits of port C.
CS: It stands for chip select. A low signal at this pin shows the enabling of communication between the
8255 and the processor. More specifically we can say that the data transfer operation gets enabled by an
active low signal at this pin.
RD – It is the signal used for read operation. A low signal at this pin shows that CPU is performing read
operation at the ports or status word. Or we can say that 8255 is providing data or information to the CPU
through data buffer.
WR – It shows write operation. A low signal at this pin allows the CPU to perform write operation over the
ports or control register of 8255 using the data bus buffer.
A0 and A1: These are basically used to select the desired port among all the ports of the 8255 and it do so
by forming conjunction with RD and WR. It forms connection with the LSB of the address bus.
MODES OF OPERATION
These are two basic modes of operation of 8255. I/O mode and Bit Set Reset mode (BSR).
• In I/O mode, the 8255 ports work as programmable I/O ports, while in BSR mode only port C (PC0-PC7) can be
used to set or reset its individual port bits.
• Under the I/O mode of operation, further there are three modes of operation of 8255, so as to support different
types of applications, mode 0, mode 1 and mode 2.
• BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 of the control word. The
bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR as given in table.
1. Bit set reset (BSR) mode –
If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits are used for set or
reset.
2. Input-Outpt mode –
If MSB of control word (D7) is 1, PPI works in input-output mode. This is further divided into three modes:
Mode 0 – This mode is also called as basic input/output mode. This mode provides simple input and
output capabilities using each of the three ports. Data can be simply read from and written to the input
and output ports respectively, after appropriate initialisation.
The salient features of this mode are as listed below:
1. Two 8-bit ports (port A and port B)and two 4-bit ports (port C upper and lower) are available. The two 4-bit
ports can be combinedly used as a third 8-bit port.
2. Any port can be used as an input or output port.
3. Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configurations are possible.
• All these modes can be selected by programming a register internal to 8255 known as CWR.
• The control word register has two formats. The first format is valid for I/O modes of operation, i.e. modes 0,
mode 1 and mode 2 while the second format is valid for bit set/reset (BSR) mode of operation. These formats are
shown in following fig.
b) Mode 1: (Strobed input/output mode) In this mode the handshaking control the input and output action of the
specified port. Port C lines PC0-PC2, provide strobe or handshake lines for port B. This group which includes port
B and PC0-PC2 is called as group B for Strobed data input/output. Port C lines PC3-PC5 provide strobe lines for
port A. This group including port A and PC3-PC5 from group A. Thus port C is utilized for generating handshake
signals. The salient features of mode 1 are listed as follows:
• Two groups – group A and group B are available for strobed data transfer.
• Each group contains one 8-bit data I/O port and one 4-bit control/data port.
• The 8-bit data port can be either used as input and output port. The inputs and outputs both are latched.
• Out of 8-bit port C, PC0-PC2 are used to generate control signals for port B and PC3-PC5 are used to generate
control signals for port A. the lines PC6, PC7 may be used as independent data lines.
Example: When CPU wants to send data to slow peripheral device like printer, it will send handshaking signal to
printer to tell whether it is ready or not to transfer the data. When printer will be ready it will send one
acknowledgement to CPU then there will be transfer of data through data bus.
• The control signals for both the groups in input and output modes are explained as follows:
Input control signal definitions (mode 1):
• STB’ (Strobe input) – If this lines falls to logic low level, the data available at 8-bit input port is loaded into input
latches.
• IBF (Input buffer full) – If this signal rises to logic 1, it indicates that data has been loaded into latches, i.e. it
works as an acknowledgement. IBF is set by a low on STB and is reset by the rising edge of RD input.
• INTR (Interrupt request) – This active high output signal can be used to interrupt the CPU whenever an input
device requests the service. INTR is set by a high STB pin and a high at IBF pin. INTE is an internal flag that can
be controlled by the bit set/reset mode of either PC4(INTEA) or PC2(INTEB) as shown in fig.
• INTR is reset by a falling edge of RD input. Thus an external input device can be request the service of the
processor by putting the data on the bus and sending the strobe signal.
Output control signal definitions (mode 1) :
• OBF (Output buffer full) – This status signal, whenever falls to low, indicates that CPU has written data to the
specified output port. The OBF flip-flop will be set by a rising edge of WR signal and reset by a low going edge at
the ACK input.
• ACK (Acknowledge input) – ACK signal acts as an acknowledgement to be given by an output device. ACK
signal, whenever low, informs the CPU that the data transferred by the CPU to the output device through the port
is received by the output device.
• INTR (Interrupt request) – Thus an output signal that can be used to interrupt the CPU when an output device
acknowledges the data received from the CPU. INTR is set when ACK, OBF and INTE are 1. It is reset by a
falling edge on WR input. The INTEA and INTEB flags are controlled by the bit set-reset mode of PC6 and PC2
respectively.
DMA CONTROLLER
The term DMA stands for direct memory access. The hardware device used for direct memory access is called the
DMA controller. DMA controller is a control unit, part of I/O device’s interface circuit, which can transfer blocks
of data between I/O devices and main memory with minimal intervention from the processor.
ARCHITECTURE OF 8257:
Register organization of 8257
• The 8257 performs the DMA operation over four independent DMA channels. Each of the four channels
of 8257 has a pair of two 16 bit registers viz. DMA address register and terminal count registers.
• There are two common registers for all channels namely, mode set registers and status registers .thus there
are a total of ten registers the CPU selects one of these ten registers using address lines A0-A3
DMA address register :It specifies the address of the first memory location to be accessed. It is necessary to load
valid memory address in the DMA address register before channel is enabled.
Terminal Count Register : shows the format of Terminal Count register.
The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0, 1, 2 and 3 respectively. A one in
these bit position will enable a particular channel and a zero will disable it • If the bit B4 is set to one, then the channels will
have rotating priority and if it zero then the channels wilt have fixed priority. In rotating priority after servicing a channel its
priority is made as lowest. In fixed priority the channel-0 has highest priority and channel-2 has lowest priority. • If the bit
B5 is set to one, then the timing of low write signals (MEMW and IOW) will be extended. • If the bit B6 is set to one then
the DMA operation is stopped at the terminal count. • The bit B7 is used to select the auto load feature for DMA channel-2. •
When bit B7 is set to one, then the content of channel-3 count and address registers are loaded in channel-2 count and
address registers respectively whenever the channel-2 reaches terminal count. When this mode is activated the number of
channels available for DMA reduces from four to three.
STATUS REGISTER:
Fig. 14.66 shows the status register format. As said earlier, it indicates which channels have reached a terminal count
condition and includes the update flag described previously.
The TC status bit, if one, indicates terminal count has been reached for that channel. TC bit remains set until the
status register is read or the 8257 is reset. The update flag, however, is not affected by a status read operation.
The update flag bit, if one, indicates CPU that 8257 is executing update cycle. In update cycle 8257 loads
parameters in channel 3 to channel 2.
The bit B0, B1, B2, and B3 of status register indicates the terminal count status of channel-0, 1,2 and 3
respectively. A one in these bit positions indicates that the particular channel has reached terminal count. • These
status bits are cleared after a read operation by microprocessor. • The bit B4 of status register is called update flag
and a one in this bit position indicates that the channel-2 register has been reloaded from channel-3 registers in the
auto load mode of operation.
Address Bus (A0-A3 and A4-A7) : The four least significant lines A0-A3 are bi – directional tri – state signals. In
the idle cycle they are inputs and used by the CPU to address the register to be loaded or read. In the Active cycle
they output the lower 4 bits of the address for DMA operation. A4-A7 are unidirectional lines, provide 4-bits of
address during DMA service.
Address Strobe (ADSTB) : This signal is used to demultiplex higher byte address and data using external latch.
Address Enable (AEN) : This active high signal enables the 8-bit latch containing the upper 8-address bits onto the
system address bus. AEN can also be used to disable other system bus drivers during DMA transfers.
Memory Read and Memory Write ( MEMR, MEMW) : These are active low tri-state signals. The MEMR signal
used to access data from the addressed memory location during a DMA read or memory-to-memory transfer and
MEMW signal is used to write data to the addressed memory location during DMA write or memory to memory
transfer.
I/O Read and I/O Write ( IOR and IOW ) : These are active low bi-directional signals. In idle cycle, these are an
input control signals used by CPU to read/write the control registers. In the active cycle IOR signal is used to
access data from a peripheral and IOW signal is used to send data to the peripheral.
Chip Select (CS) : This is an active low input, used to select the 8257 as an I/O device during the idle cycle. This
allows CPU to communicate with Pin Diagram of 8257.
Reset : This active high signal clears, the command, status, request and temporary registers. It also clears the
first/last flip-flop and sets the Master Register. After reset the device is in the idle cycle.
Ready : This input is used to extend the memory read and write signals from the 8257 to interface slow memories
or I/O devices.
Hold request (HRQ) : Any valid DREQ causes 8257 to issue the HRQ. It is used for requesting CPU to get the
control of system bus.
Hold Ackmiwledge (HLDA) : The active high Hold Acknowledge from the CPU indicates that it has relinquished
control of the system bus.
DREQ0-DREQ3 : These are DMA request lines, which are activated to obtain DMA service, until the
corresponding DACK signal goes active.
DACK0-DACK3 : These are used to indicate peripheral devices that the DMA request is granted.
Terminal Count (TC) : This is active high signal concern with the completion of DMA service. The TC output
signal is activated at the end of DMA service, i.e. when present cycle is a last cycle for the current data block.
MARK : This output notifies the selected peripheral that the current DMA cycle is the 128th cycle since the
previous MARK output. MARK always occurs at 128 (all multiplies of 128) cycles from the end of the data block.
Direct Memory Access TRANSFER
DMA is a process of communication for data transfer between memory and input/output, controlled by an
external circuit called DMA controller, without involvement of CPU.
8086 MP has two pins HOLD and HLDA which are used for DMA operation.
First, DMA controller sends a request by making HRQ control line high. When MP receives high signal to
HOLD pin, it first completes the execution of current machine cycle, it takes few clocks and sends HLDA
signal to the DMA controller.
After receiving HLDA TO DMA controller, the DMA controller takes control over system bus and
transfers data directly between memory and I/O without involvement of CPU. During DMA operation, the
processor is free to perform next job which does not need system bus.
At the end of data transfer, the DMA controller terminates the request by sending low signal to HOLD pin
and MP regains control of system bus by making HLDA low.
Figure shows the block diagram of a typical DMA controller. The unit communicates with the MP via the
data bus and control lines.
The registers in the DMA are selected by the MP through the address bus by enabling the DS (DMA select)
and RS (Register Select) inputs. The RD (read) and WR (write) inputs are bidirectional.
When the bus grant (HRQ) input is 0, the MP can communicate with the DMA registers through the data
bus to read from or write to the DMA registers. When HRQ=1, the processor does not have control over
the system buses and the DMA can communicate directly with the memory by specifying an address in the
address bus and activating the RD or WR control.
The DMA controller has three registers: an address register, a word count register and a control register.
The address register contains an address to specify the desired location in memory. The address bits go
though bus buffers into the address bus. The address register is incremented after each word that is
transferred to memory.
The word count register holds the number of words to be transferred. The register is decremented by one
after each word transfer and internally tested for zero.
8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator between
microprocessor and peripheral to transmit serial data into parallel form and vice versa.
1. It takes data serially from peripheral (outside devices) and converts into parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into serial form.
4. After converting data into serial form, it transmits it to outside device (peripheral).
Simplex: Data travels in one direction (from A to B). An example of a simplex link would be scoreboards such as
those used in hockey, basketball, or other sports. The information is entered at a console by the score/timekeeper
and sent serially to large displays that everybody can see.
Half-duplex: Data travels in one direction (from A to B) and then the other direction (from B to A) but not at the
same time. The RS-485 is half-duplex.
Fig. 14.37 shows the block diagram of IC Block Diagram of 8251 Microcontroller. It includes : Data bus buffer,
Read/Write control logic, modem control, Transmit buffer, Transmit Control, Receiver Buffer and Receiver
control.
This tri-state, bi-directional, 8-bit buffer is used to interface Block Diagram of 8251 Microcontroller to the system
data bus. Along with the data, control word, command words and status information are also transferred through
the Data Bus Buffer.
This functional block accepts inputs from the system control bus and generates control signals for overall device
operation. It decodes control signals on the 8085 control bus into signals which controls the internal and external
I/O bus. It contains the control word register and command word register that stores the various control formats for
the device functional definition.
Transmit Buffer:
The transmit buffer accepts parallel data from the CPU, adds the appropriate framing information, serializes it, and
transmits it on the TxD pin on the falling edge of TxC.
It has two registers : A buffer register to hold eight bits and an output register to convert eight bits into a stream of
serial bits. The CPU writes a byte in the buffer register, Which is transferred to the output register when it is
empty. The output register then transmits serial data on the TxD pin.
In the asynchronous mode the transmitter always adds START bit; depending on how the unit is programmed, it
also adds an optional even or odd parity bit, and either 1, 1 1/2, or 2 STOP bits. In synchronous mode no extra bits
(other than parity, if enable) are generated by the transmitter.
Transmit Control :
It manages all activities associated with the transmission of serial data. It accepts and issues signals both externally
and internally to accomplish this function.
TxRDY (Transmit Ready ) : This output signal indicates CPU that buffer register is empty and the USART is
ready to accept a data character. It can be used as an interrupt to the system or, for polled operation, the CPU can
‘check TxRDY using the status read operation. This signal is reset when a data byte is loaded into the bliffer
register.
TxE (Transmitter Empty) : This is an output signal. A high on this line indicates that the output buffer is empty. In
the synchronous mode, if the CPU has failed to load a new character in time, TxE will go high momentarily as
SYN characters are loaded into the transmitter to fill the gap in transmission.
TxC (Transmitter Clock) : This clock controls the rate at which characters are transmitted by USART. In the
synchronous mode TxC is equivalent to the ‘baud rate, and is supplied by the modem. In asynchronous mode TxC
is 1, 16, or 64 times the baud rate. The clock division is programmable. It can be programmed by writing proper
mode word in the mode set register.
Receiver Buffer:
The receiver accepts serial data on the RxD line, converts this serial data to parallel format, checks for bits or
characters that are unique to the communication technique and sends an “assembled” character to the CPU.
When Block Diagram of 8251 Microcontroller is in the asynchronous mode an4 it is ready to accept a character, it
looks for a low level on the RxD line. When it receives the low level, it assumes that it is a START bit and enables
an internal counter, At a count equivalent to one-half of a hit time, the RxD line is sampled again. If the line is still
low, a valid START bit is detected and the 8251A proceeds to assemble the character. After successful reception
of a START bit the 8251A receives data, parity and STOP bits, and then transfers the data on the receiver input
register. The data is then transferred into the receiver buffer register.
In the synchronous mode the receiver simply receives the specified number of data bits and transfers them to the
receiver input register and then to the receiver buffer register.
Receiver Control:
It manages all receiver-related activities. Along with data reception, it does false start bit detection, parity error
detection, framing error detection, sync detection and break detection.
RxRDY (Receiver Ready) : This is an output signal. It goes high (active), when the USART has a character in the
buffer register and is ready to transfer it to the CPU. This line can be used either to indicate the status in the status
register or to interrupt the CPU. This signal is reset when a data byte from receiver buffer is read by the CPU.
RxC (Receiver Clock) : This clock controls the rate at which the character is to be received by USART in the
synchronous mode. RxC is equivalent to the baud rate, and is supplied by the modem. In asynchronous mode RxC
is 1, 16, or 64 times the baud rate. The clock division is programmable. It can be programmed by writing proper
mode word in the mode set register.
Modem Control:
The Block Diagram of 8251 Microcontroller has a set of control inputs and output’s that can be used to simplify
the interface to almost any modem. It provides control circuitry for the generation of RTS and DTR and the
reception of CTS and DSR. In addition, a general purpose inverted output and a general purpose input are
provided. The output is labeled DTR and the input is labeled DSR. DTR can be asserted by setting bit 2 of the
command instruction; DSR can be sensed as bit 7 of the status register. When used as a modem control signal
DTR indicates that the terminal is ready to communicate and DSR indicates that it is ready for communication.
The control words defines the complete functional definition of Block Diagram of 8251 Microcontroller and they
must be loaded before any transmission or reception. The control words of Block Diagram of 8251
Microcontroller are split into two formats
Mode instruction
Command instruction
Command Instruction:
In the data communication systems it is often necessary to examine the “status” of the transmitter and receiver. It
is also necessary for CPU to know if any error has occurred during communication. The Block Diagram of 8251
Microcontroller allow the programmer to read above mentioned information from the status register any time
during the functional operation. Fig. 14.40 shows the format of status register.
Error Definitions:
Parity Error : At the time of transmission of data an even or odd parity bit is inserted in the data stream. At the
receiver end, if parity of the character does not match with the pre-defined parity, parity error occurs.
Overrun Error : In the receiver section received character is stored in the receiver buffer. The CPU is supposed to
read this character before reception of the next character. But if CPU fails in reading the character loaded in the
receiver buffer, the next the received character replaces the previous one and the OVERRRUN Error occurs.
Framing Error : If valid stop bit is not detected at the end each character framing error occurs.
All these errors, when occur, set the corrosponding bits in the status register. These error bits are reset by setting
ER bit in the command instruction.
converters with
microprocessor.
EOC signal is
called as the conversion delay of the ADC.
hundred
milliseconds in case of slow ADCs.
utput.
conversion till
the end of the conversion to get correct results. This may be ensured by as ample and hold circuit which
samples the analog signal and holds it constant for specific time duration. The microprocessor may issue a
hold signal to the sample and hold circuit.
ADC 0808/0809:
The digital to analog converters convert binary numbers into their analog equivalent voltages. The DAC
find applications in areas like digitally controlled gains, motor speed controls, programmable gain amplifiers,
etc.
resistor acts to
control the gain. One may not connect any external feedback resistor, if no gain control is required.
STEPPER MOTOR INTERFACING:
shafts. It employs
rotation of its shaft in terms of steps, rather than continuous rotation as in case of AC or DC motors.
To rotate the shaft of the stepper motor, a sequence of pulses is needed to be applied to the windings of
the stepper motor, in a proper sequence.
motor is equal to
its number of internal teeth on its rotor. The stator teeth and the rotor teeth lock with each other to fix a
position of the shaft.
Another popular
scheme for rotation of a stepper motor shaft applies pulses to two successive windings at a time but
these are shifted only by one position at a time. This scheme for rotation of stepper motor shaft is shown in
table2.
EXAMPLE : Design a stepper motor controller and write an ALP to rotate shaft of a 4 phase stepper motor in
clockwise 5 rotation and in anticlockwise 5 rotation