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ACA Assignment 3 QUIZ Assignment: Answer 1 - B. Physical Addresses

This document contains a quiz assignment with 14 multiple choice questions about computer architecture topics like virtual memory, cache memory, RISC vs CISC architectures, and memory. The questions assess understanding of concepts like physical vs virtual addresses, write-back caching, zero address instruction formats, flow dependence, RISC characteristics, fetch cycles, programmable logic arrays, content addressable memory, integrated circuits, and immediate addressing. The answers to each question are also provided.

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shresth choudhary
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44 views3 pages

ACA Assignment 3 QUIZ Assignment: Answer 1 - B. Physical Addresses

This document contains a quiz assignment with 14 multiple choice questions about computer architecture topics like virtual memory, cache memory, RISC vs CISC architectures, and memory. The questions assess understanding of concepts like physical vs virtual addresses, write-back caching, zero address instruction formats, flow dependence, RISC characteristics, fetch cycles, programmable logic arrays, content addressable memory, integrated circuits, and immediate addressing. The answers to each question are also provided.

Uploaded by

shresth choudhary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ACA Assignment 3

QUIZ Assignment
Q1. In a virtual memory system, the addresses used by the programmer belongs to

A. memory space.

B. physical addresses.

C. address space.

D. main memory address

Answer 1 – B. physical addresses

Q2. The method for updating the main memory as soon as a word is removed from the Cache is
called

A. Write-through

B. write-back

C. protected write

D. cache-write

Answer 2 – B. write-back

Q3. Zero address instruction format is used for:

A. RISC architecture.

B. CISC architecture.

C. Von-Neuman architecture.

D. Stack-organized architecture.

Answer 3 - D. Stack-organized architecture.

Q4. A statement S2 is flow dependent on statement S1, if an execution path is exist from S1 to S2
and if at least one output of S1 is used as input to S2.

A. True

B. False

Answer 4 – A. True

Q5. Which is true for a typical RISC architecture?

A. Micro programmed control unit.


B. Instruction takes multiple clock cycles.

C. Have few registers in CPU.

D. Emphasis on optimizing instruction pipelines.

Answer 5 - A. Micro programmed control unit


Q6. When an instruction is read from the memory, it is called?

A. Memory Read cycle

B. Fetch cycle

C. Instruction cycle

D. Memory write cycle

Answer 6 - B. Fetch cycle

Q7. A circuit in which connections to both AND and OR arrays can be programmed is called?
A. RAM
B. ROM
C. PAL
D. PLA

Answer 7 - A. RAM

Q8. Associative memory is sometimes called as


A. Virtual memory
B. Cache memory
C. Main memory
D. Content addressable memory

Answer 8 - D. Content addressable memory

Q9. The advantage of RISC processor over CISC processor is that


A. The hardware architecture is simpler
B. An instruction can be executed in one cycle
C. Less number of registers accommodate in chip
D. Parallel execution capabilities

Answer 9 – B. An instruction can be executed in one cycle

Q10. Intel Pentium CPU is a


A. RISC based
B. CISC based
C. Both of the above
D. None of the above

Answer 10 – B. CISC based

Q11. Which of the following require large computer memory?


A. Imaging
B. Graphics
C. Voice
D. All of the above

Answer 11 – D. All of the above

Q12. Which major development led to the production of microcomputers?


A. Magnetic disks
B. floppy disks
C. Logic gates
D. Integrated Circuits

Answer 12 – D. Integrated Circuits

Q13. In immediate addressing the operand is placed


A. in the CPU register
B. after opcode in the instruction
C. in the memory
D. in the stack

Answer 13 – B. after opcode in the instruction

Q14. Micro instructions are stored in


A. computer memory
B. primary storage
C. secondary storage
D. control memory

Answer 14 – D. control memory

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