Section 1

Sno 1

Name SECTION-1

Time 120

Mark 1

Negative 0

Questions – S1

Qno 1

Question An embedded system is a

Sno 1

Type Mcq

A Operating system

B Software

C Hardware

D Combination of Software & Hardware

Answer D

Topic Chapter-1

Mark 1

Level 1

Qno 2

Which of the following are examples of an embedded systems

Question
a) ATM b) Washing Machine c)Table d) Camera
Sno 2

Type Mcq

A a,b,c

B b,c,d

C a,b,d

D a,b,c,d

Answer C

Topic Chapter-1

Mark 1

Level 1

Qno 3

Question Expand SoC

Sno 3

Type Mcq

A System of components

B Silicon on chip

C Silicon on circuit

D System on chip

Answer D

Topic Chapter-1

Mark 1

Level 1
Qno 4

Question PIC stands for

Sno 1

Type Mcq

A Peripheral interface controller

B Peripheral interrupt controller

C Peripheral internet controller

D Peripheral controller

Answer A

Topic Chapter-1

Mark 1

Level 1

Qno 5

Question ASIC stands for

Sno 1

Type Mcq

A Application specific interrupt controller

B Application specific integrated circuit

C Application specific integrated controller

D Application specific interrupt circuit

Answer B

Topic Chapter-1

Mark 1
Level 1

Qno 6

In an embedded system architecture, the incoming information/signals

Question
are collected by

Sno 1

Type Mcq

A Sensors

B Actuators

C CPU

D ADC

Answer A

Topic Chapter-1

Mark 1

Level 1

Qno 7

Question Which of the following is/are features of an embedded systems

Sno 1

Type Mcq

A Sophisticated functionality

B Restricted memory

C Real time operation

D All of these

Answer D

Topic Chapter-1

Mark 1

Level 1

Qno 8

Question ASSP stands for

Sno 1

Type Mcq

A Application Specific System Programme

B Application Specific Instruction programme

C Application Specific System Processor

D Application Specific Instruction Processors

Answer C

Topic Chapter-1

Mark 1

Level 1

Qno 9

How many level hardware stack is present in midrange type PIC

Question
controller?

Sno 1
Type Mcq

A 6

B 7

C 8

D 11

Answer C

Topic Chapter-1

Mark 1

Level 1

Qno 10

Question PIC18 family comes under which type ?

Sno 1

Type Mcq

A Baseline

B Midrange

C Enhanced midrange

D High end

Answer D

Topic Chapter-1

Mark 1

Level 1
Qno 11

Question How many instructions are there in midrange PIC?

Sno 1

Type Mcq

A 33

B 35

C 49

D 83

Answer B

Topic Chapter-1

Mark 1

Level 2

Qno 12

Question How many instructions are there in Highend PIC?

Sno 1

Type Mcq

A 33

B 35

C 49

D 83

Answer D

Topic Chapter-1

Mark 1

Level 2
Qno 13

Question UART stands for

Sno 1

Type Mcq

A Universal Syncronous Asynchronous Receiver/Transmitter

B Universal synchronous Receiver/Transmitter

C Universal Asynchronous Receiver/Transmitter

D Universal Asynchronous Receiver

Answer C

Topic Chapter-1

Mark 1

Level 2

Qno 14

Question Speed of Midrange PIC is

Sno 1

Type Mcq

A 2MIPS

B 5MIPS

C 8MIPS

D 10MIPS

Answer B
Topic Chapter-1

Mark 1

Level 2

Qno 15

Question 16-level hardware stack id present in which type of PIC?

Sno 1

Type Mcq

A Baseline

B Midrange

C Enhanced Midrange

D High end

Answer C

Topic Chapter-1

Mark 1

Level 2

Qno 16

The operating frequency of a microprocessor(8086) for fetch-and-execute

Question
cycle is

Sno 1

Type Mcq

A 1MHz

B 2MHz
C 1GHz

D 2GHz

Answer D

Topic Chapter-1

Mark 1

Level 2

Qno 17

Question ISA stands for

Sno 1

Type Mcq

A Instruction set Architecture

B Instruction set Application

C Interrupt set Architecture

D Interrupt set Application

Answer A

Topic Chapter-1

Mark 1

Level 2

Qno 18

The additional block requirement for ATM cash deposition machine

Question
based embedded system

Sno 1
Type Mcq

A Aux system

B User interface

C Money

D Sensor

Answer B

Topic Chapter-1

Mark 1

Level 2

Qno 19

data and code lie in different memory blocks, then the architecture is
Question
referred as

Sno 1

Type Mcq

A CISC architecture

B RISC architecture

C Von neumann architecture

D Harvard architecture

Answer D

Topic Chapter-1

Mark 1

Level 2
Qno 20

Question The number of pins that 16c5x(12-bit)

Sno 1

Type Mcq

A 8

B 14

C 28

D 40

Answer B

Topic Chapter-1

Mark 1

Level 2

Qno 21

Question Expand RISC

Sno 1

Type Mcq

A Reused Instruction Set Computer

B Reused Interrupt Set Computer

C Reduced Instruction Set Computer

D Reduced Interrupt Set Computer

Answer C

Topic Chapter-1

Mark 1

Level 3
Qno 22

Question SPI stands for

Sno 1

Type Mcq

A Serial Peripheral Interface

B Serial Programmable Interface

C Serial Peripheral Instruction

D Serial Programmable Innstruction

Answer A

Topic Chapter-1

Mark 1

Level 3

Qno 23

Question I2C stands for

Sno 1

Type Mcq

A Inter Instruction Circuit

B Inter Instruction port

C Inter Integrated Circuit

D Inter Integrated port

Answer C
Topic Chapter-1

Mark 1

Level 3

Qno 24

Question PIC 18 architecture having a program memory of upto

Sno 1

Type Mcq

A 16

B 32

C 64

D 128

Answer D

Topic Chapter-1

Mark 1

Level 3

Qno 25

Question Base line PIC processor instruction length

Sno 1

Type Mcq

A 10

B 12

C 16
D 18

Answer B

Topic Chapter-1

Mark 1

Level 3

Qno 26

Question Data memory of Midrange PIC is

Sno 1

Type Mcq

A 368 Bytes

B 138 Bytes

C 1 KB

D 4 KB

Answer A

Topic Chapter-1

Mark 1

Level 3

Qno 27

Question Enhanced mid range PIC has a spped of

Sno 1

Type Mcq

A 5MIPS
B 8MIPS

C 10MIPS

D 12MIPS

Answer B

Topic Chapter-1

Mark 1

Level 3

Qno 28

Question PWM mode of operation is available in which type of PIC?

Sno 1

Type Mcq

A Baseline

B Midrange

C Enhanced midrange

D High end

Answer B

Topic Chapter-1

Mark 1

Level 3

Qno 29

Which of the following is a fetch unit for fetching instructions from the
Question
memory
Sno 1

Type Mcq

A Control unit

B Execution unit

C Arithmetic and logical unit

D None

Answer A

Topic Chapter-1

Mark 1

Level 3

Qno 30

Question FPGA stands for

Sno 1

Type Mcq

A Fixed programmable gate array

B Field processor gate array

C Field programmable gate array

D Fixed processor gate array

Answer C

Topic Chapter-1

Mark 1

Level 3
Qno 31

Question If destination bit is 0 contents stores in which register ?

Sno 1

Type Mcq

A Working register

B FSR register

C Shift register

D Destination register

Answer A

Topic Chapter-2

Mark 1

Level 1

Qno 32

Question How many memory banks are available in Direct addressing mode?

Sno 1

Type Mcq

A 2

B 4

C 8

D 16

Answer B

Topic Chapter-2

Mark 1

Level 1
Qno 33

Question If destination bit is 1 contents stores in which register ?

Sno 1

Type Mcq

A Working register

B FSR register

C Shift register

D Destination register

Answer B

Topic Chapter-2

Mark 1

Level 1

Qno 34

The contents are stored in which register addwf 0x20,0 ?

Question

Sno 1

Type Mcq

A W register

B F register

C Accumulator

D B register

Answer A

Topic Chapter-2
Mark 1

Level 1

Qno 35

Which flag is affected for clrf f ?

Question

Sno 1

Type Mcq

A DC

B O

C C

D Z

Answer D

Topic Chapter-2

Mark 1

Level 1

Qno 36

Question DECFSZ f,d instruction requires how many clock cycles if result is Zero?

Sno 1

Type Mcq

A 0

B 1

C 2
D 4

Answer C

Topic Chapter-2

Mark 1

Level 1

Qno 37

Question ―Bit Test f, Skip if Clear ― the corresponding instruction is

Sno 1

Type Mcq

A BTFSC

B BTFSS

C BFTSS

D BFTSC

Answer A

Topic Chapter-2

Mark 1

Level 1

Qno 38

Question BTFSS f,d requires how many clock cycles if result is non zero ?

Sno 1

Type Mcq

A 0
B 1

C 2

D 4

Answer B

Topic Chapter-2

Mark 1

Level 1

Qno 39

Question Call subroutine requires how many number of clock cycles ?

Sno 1

Type Mcq

A 0

B 1

C 2

D 3

Answer C

Topic Chapter-2

Mark 1

Level 1

Qno 40

Question After GOTO K instruction execution which flag will be affected ?

Sno 1
Type Mcq

A Z

B C

C DC

D None

Answer D

Topic Chapter-2

Mark 1

Level 1

Qno 41

Question The instruction has to give to the processor to enter into standby mode?

Sno 1

Type Mcq

A Wdt

B Sleep

C Shtdwn

D Clear

Answer B

Topic Chapter-2

Mark 1

Level 2
Qno 42

In PIC assembly programming target files must be saved with which type
Question
?

Sno 1

Type Mcq

A .INC

B .JPG

C .PIC

D .PNG

Answer A

Topic Chapter-2

Mark 1

Level 2

Qno 43

Question Which one of the following is optional in programming in PIC?

Sno 1

Type Mcq

A Label

B Mnemonics

C Operand

D Comment

Answer D

Topic Chapter-2

Mark 1
Level 2

Qno 44

Question In PIC assembly programming label can be represented in which format ?

Sno 1

Type Mcq

A Bit

B Wait

C Loop

D _again

Answer D

Topic Chapter-2

Mark 1

Level 2

Qno 45

Question How many maximum characters that a label contains

Sno 1

Type Mcq

A 16

B 32

C 128

D 64

Answer B
Topic Chapter-2

Mark 1

Level 2

Qno 46

Question Which of the following is not a PIC Peripheral ?

Sno 1

Type Mcq

A UART

B Pulse Width Modulator

C Watch Dog Timer

D File Shift Register

Answer D

Topic Chapter-2

Mark 1

Level 2

Qno 47

Question GIE stands for

Sno 1

Type Mcq

A Global instruction entry

B Global interrupt entity

C Global interrupt enable

D Global instruction enable

Answer C

Topic Chapter-2

Mark 1

Level 2

Qno 48

Which registers contain bits for enabling interrupts from individual

Question
peripherals ?

Sno 1

Type Mcq

A PIE

B PIR

C PWM

D PPP

Answer A

Topic Chapter-2

Mark 1

Level 2

Qno 49

Which registers contain flag bits for individual peripheral interrupts?

Question

Sno 1
Type Mcq

A PIE

B PIR

C PWM

D PPP

Answer B

Topic Chapter-2

Mark 1

Level 2

Qno 50

When interrupt is responded by processor then the PC is pushed into

Question

Sno 1

Type Mcq

A Data Memory

B Register

C Stack

D Program memory

Answer C

Topic Chapter-2

Mark 1

Level 2
Qno 51

Question ISP stands for

Sno 1

Type Mcq

A Interrupt service routine

B Instruction Service router

C Interrupt Service router

D Instruction service routine

Answer A

Topic Chapter-2

Mark 1

Level 3

Qno 52

____________is a sequence of instructions that must be protected from

Question
an intervening interrupt or produce erroneous output.

Sno 1

Type Mcq

A Critical point

B Critical path

C Critical region

D Critical area

Answer C

Topic Chapter-2

Mark 1
Level 3

Qno 53

Question All PIC’s have digital I/O pins called

Sno 1

Type Mcq

A Out pins

B Ports

C Routers

D Connectors

Answer B

Topic Chapter-2

Mark 1

Level 3

Qno 54

Question Each port of PIC is having how many control registers ?

Sno 1

Type Mcq

A 1

B 2

C 3

D 4

Answer B
Topic Chapter-2

Mark 1

Level 3

Qno 55

Question The 8pin 12C508 has ___ ports with ___ digital I/O pins respectively ?

Sno 1

Type Mcq

A 1,4

B 2,4

C 2,8

D 4,16

Answer A

Topic Chapter-2

Mark 1

Level 3

Qno 56

the 68pin 17C766 has ____ ports with ___ digital I/O pins
Question

Sno 1

Type Mcq

A 9,69

B 10,69
C 9,66

D 10,66

Answer C

Topic Chapter-2

Mark 1

Level 3

Qno 57

To directly drive the LED’s the source/sink pins must have a current of (in
Question
mA)

Sno 1

Type Mcq

A 10

B 20

C 25

D 15

Answer C

Topic Chapter-2

Mark 1

Level 3

Qno 58

Question TIMER 0 acts as

Sno 1
Type Mcq

A 8 bit timer/counter with pre scaler

B 16 bit timer/counter with pre scaler

C 8 bit timer/counter with post scaler

D 16 bit timer/counter with post scaler

Answer A

Topic Chapter-2

Mark 1

Level 3

Qno 59

Question TIMER 0 is

Sno 1

Type Mcq

A Readable

B Writable

C Both

D None

Answer C

Topic Chapter-2

Mark 1

Level 3

Qno 60
Question TIMER 1 is

Sno 1

Type Mcq

A 8 bit timer/counter pre scaler

B 16 bit timer/counter

C 8 bit timer/counter post scaler

D 16 bit timer/counter post scaler

Answer B

Topic Chapter-2

Mark 1

Level 3

Qno 61

Question TIMER 1 is

Sno 1

Type Mcq

A Readable

B Writable

C Both

D None

Answer C

Topic Chapter-3

Mark 1

Level 1
Qno 62

Question In how many modes the TIMER 1 can be operated ?

Sno 1

Type Mcq

A 1

B 2

C 3

D 4

Answer C

Topic Chapter-3

Mark 1

Level 1

Qno 63

In which operating mode TIMER 1 increments on rising edge of external

Question
clock?

Sno 1

Type Mcq

A Synchronised timer

B Synchronised counter

C Asynchronised timer

D Asynchronised counter

Answer B

Topic Chapter-3

Mark 1
Level 1

Qno 64

Question In which operating mode TIMER Increments every instruction cycle?

Sno 1

Type Mcq

A Synchronised timer

B Synchronised counter

C Asynchronised timer

D Asynchronised counter

Answer A

Topic Chapter-3

Mark 1

Level 1

Qno 65

In which operating mode ,Timer increments independent of internal

Question
phase clock ?

Sno 1

Type Mcq

A Synchronised timer

B Synchronised counter

C Asynchronised timer

D Asynchronised counter

Answer D
Topic Chapter-3

Mark 1

Level 1

Qno 66

Question TIMER 2 is a

Sno 1

Type Mcq

A 8-bit timer/counter with pre scaler and post scaler

B 16-bit timer/counter with pre scaler

C 8-bit timer/counter with pre scaler

D 16-bit timer/counter with pre scaler and post scaler

Answer A

Topic Chapter-3

Mark 1

Level 1

Qno 67

Question CCP Stands for

Sno 1

Type Mcq

A Capture/Compare/PMW

B Compare/Capture/PWM

C Compare/Capture/PMW

D Capture/Compare/PWM
Answer D

Topic Chapter-3

Mark 1

Level 1

Qno 68

The CCP module bit operations are generally having a bit lengths
Question
of_,__,__ respectively

Sno 1

Type Mcq

A 10,16,16

B 16,10,16

C 16,16,10

D 16,16,16

Answer C

Topic Chapter-3

Mark 1

Level 1

Qno 69

________will interrupt when the timer equals the value in a compare

Question
register

Sno 1

Type Mcq

A Capture

B Compare
C PWM

D Program counter

Answer B

Topic Chapter-3

Mark 1

Level 1

Qno 70

Question Which of the following counts external pin changes

Sno 1

Type Mcq

A Capture

B Compare

C PWM

D Program counter

Answer A

Topic Chapter-3

Mark 1

Level 1

Qno 71

Question Uses of PWM mode of operation is

Sno 1

Type Mcq
 Intensity control
A

B Motor control

C Temperature control

D All of these

Answer D

Topic Chapter-3

Mark 1

Level 2

Qno 72

In pulse width modulation mode, CCPx pin produces up to a ___bit

Question
resolution PWM output

Sno 1

Type Mcq

A 8

B 16

C 10

D 20

Answer C

Topic Chapter-3

Mark 1

Level 2
Qno 73

Question To control the speed of DC motor which mode of operation required ?

Sno 1

Type Mcq

A Capture

B Compare

C PWM

D Watch dog timer

Answer C

Topic Chapter-3

Mark 1

Level 2

Qno 74

Question Clock frequency of 12C508 PIC is

Sno 1

Type Mcq

A 1 MHz

B 2 MHz

C 3 MHz

D 4 MHz

Answer D

Topic Chapter-3

Mark 1

Level 2
Qno 75

Question How many bit program memory own by 12C508 PIC

Sno 1

Type Mcq

A 10

B 12

C 14

D 16

Answer B

Topic Chapter-3

Mark 1

Level 2

Qno 76

Question PIC 16F876 has instruction time of

Sno 1

Type Mcq

A 200 ns

B 100 ns

C 400 ns

D 300 ns

Answer A

Topic Chapter-3
Mark 1

Level 2

Qno 77

Question PIC 16F876 has ____bit EEPROM(non-volatile) data registers

Sno 1

Type Mcq

A 2

B 4

C 8

D 16

Answer C

Topic Chapter-3

Mark 1

Level 2

Qno 78

Question ICD stands for

Sno 1

Type Mcq

A In circuit Debugger

B Inter circuit Debugger

C Intra circuit Debugger

D In chip Debugger
Answer A

Topic Chapter-3

Mark 1

Level 2

Qno 79

Question Original name of ARM processor is

Sno 1

Type Mcq

A Acron RISC Machine

B Advanced RISC Machine

C Arm RISC Machine

D Apple RISC machine

Answer A

Topic Chapter-3

Mark 1

Level 2

Qno 80

Question ARM processors instruction bit length is

Sno 1

Type Mcq

A 8

B 16
C 32

D 64

Answer C

Topic Chapter-3

Mark 1

Level 2

Qno 81

Question Version 1 ARM processor addressing bit length

Sno 1

Type Mcq

A 16

B 26

C 32

D 64

Answer B

Topic Chapter-3

Mark 1

Level 3

Qno 82

Question Version 2 ARM processor addressing bit length

Sno 1

Type Mcq
A 16

B 26

C 32

D 64

Answer C

Topic Chapter-3

Mark 1

Level 3

Qno 83

Question Bit operations consist of following micro operations ?

Sno 1

Type Mcq

A CPU reads the complete byte

B CPU changes one bit in it

C CPU writes the entire byte back

D All of these

Answer D

Topic Chapter-3

Mark 1

Level 3

Qno 84
Question Signal processing extensions are added in which version ?

Sno 1

Type Mcq

A Version 4

B Version 4T

C Version 5T

D Version 5TE

Answer D

Topic Chapter-3

Mark 1

Level 3

Qno 85

Question In ARM processors, R13 is

Sno 1

Type Mcq

A Link register

B Stack pointer

C Program counter

D ALU

Answer B

Topic Chapter-3

Mark 1

Level 3
Qno 86

Question whenever a subroutine is called return address is kept in

Sno 1

Type Mcq

A Link register

B Stack pointer

C Program counter

D ALU

Answer A

Topic Chapter-3

Mark 1

Level 3

Qno 87

Question CPSR stands for

Sno 1

Type Mcq

A control program status register

B current program shift register

C control program shift register

D current program status register

Answer D
Topic Chapter-3

Mark 1

Level 3

Qno 88

Question SPSR stands for

Sno 1

Type Mcq

A saved program status register

B saved program shift register

C saved priority status register

D saved priority shift register

Answer A

Topic Chapter-3

Mark 1

Level 3

Qno 89

Question When ALU operation is overflowed which status flag effects ?

Sno 1

Type Mcq

A C

B O
C OF

D V

Answer D

Topic Chapter-3

Mark 1

Level 3

Qno 90

Question If ‘I’ Flag is 1 then which of the following is disabled ?

Sno 1

Type Mcq

A IRQ

B FIQ

C T bit

D J bit

Answer A

Topic Chapter-3

Mark 1

Level 3

Qno 91

Question If ‘F’ Flag is 1 then which of the following is disabled ?

Sno 1
Type Mcq

A IRQ

B FIQ

C T bit

D J bit

Answer B

Topic Chapter-4

Mark 1

Level 1

Qno 92

Question When T bit = 0 then processor is in

Sno 1

Type Mcq

A THUMB state

B Jazelle state

C Over flow state

D ARM state

Answer D

Topic Chapter-4

Mark 1

Level 1

Qno 93
Question When T bit = 1 then processor is in

Sno 1

Type Mcq

A THUMB state

B Jazelle state

C Over flow state

D ARM state

Answer A

Topic Chapter-4

Mark 1

Level 1

Qno 94

When there is a failed attempt to access the memory then processor

Question
enters into which mode ?

Sno 1

Type Mcq

A Abort mode

B Supervisor mode

C System mode

D Undefined

Answer A

Topic Chapter-4

Mark 1

Level 1
Qno 95

Question state after reset and generally the mode is in which OS kernel executes

Sno 1

Type Mcq

A Abort mode

B Supervisor mode

C System mode

D Undefined

Answer B

Topic Chapter-4

Mark 1

Level 1

Qno 96

Question special version of user mode that allows full read-write access of CPSR

Sno 1

Type Mcq

A Abort mode

B Supervisor mode

C System mode

D Undefined

Answer C

Topic Chapter-4

Mark 1

Level 1
Qno 97

Question How many number of registers are available in Register file?

Sno 1

Type Mcq

A 16

B 20

C 37

D 40

Answer C

Topic Chapter-4

Mark 1

Level 1

Qno 98

Question How many hidden registers are there banked registers?

Sno 1

Type Mcq

A 16

B 20

C 37

D 40

Answer B

Topic Chapter-4

Mark 1
Level 1

Qno 99

Question Expands FIQ

Sno 1

Type Mcq

A Fast Interrupt Query

B Fast instruction request

C Fast instruction Query

D Fast interrupt request

Answer D

Topic Chapter-4

Mark 1

Level 1

Qno 100

Question Expand SP

Sno 1

Type Mcq

A Status pointer

B Status register pointer

C Stack Pointer

D Status programme

Answer C

Topic Chapter-4
Mark 1

Level 1

Qno 101

Question LR stands

Sno 1

Type Mcq

A Link router

B Listed register

C Link register

D Listed router

Answer C

Topic Chapter-4

Mark 1

Level 2

Qno 102

Question ARM Memory organization is in which style?

Sno 1

Type Mcq

A Big endian style

B Little endian style

C Big array style

D Little array style

Answer B
Topic Chapter-4

Mark 1

Level 2

Qno 103

Question 16 bits length is called

Sno 1

Type Mcq

A Byte

B Word

C Half word

D Half Byte

Answer C

Topic Chapter-4

Mark 1

Level 2

Qno 104

Question 8 bits length is called as

Sno 1

Type Mcq

A Byte

B Kilo Byte

C Half word
D Word

Answer A

Topic Chapter-4

Mark 1

Level 2

Qno 105

Question 32 bit length is called as

Sno 1

Type Mcq

A Byte

B Half Byte

C Half word

D Word

Answer D

Topic Chapter-4

Mark 1

Level 2

Qno 106

Which of the following instruction Swap a word between memory and

Question
register

Sno 1

Type Mcq

A SWAP
B SWP

C SWPA

D SWPB

Answer B

Topic Chapter-4

Mark 1

Level 2

Qno 107

The Additional bits to increase accuracy of results is

Question

Sno 1

Type Mcq

A Shifting bits

B Guard bits

C Saturation bits

D Aliasing bits

Answer B

Topic Chapter-4

Mark 1

Level 2

Qno 108

Question To Preventing wrap around on overflow or underflow

Sno 1
Type Mcq

A Shifting bits

B Guard bits

C Saturation bits

D Aliasing bits

Answer C

Topic Chapter-4

Mark 1

Level 2

Qno 109

Question Which are helps in Adjustment of mantissas of floating point numbers?

Sno 1

Type Mcq

A Delay

B Guard bands

C Multipliers

D Shifters

Answer D

Topic Chapter-4

Mark 1

Level 2

Qno 110

Question SoC stands for

Sno 1

Type Mcq

A System on chip

B System on circuit

C Silicon on Chip

D Silicon on Circuit

Answer A

Topic Chapter-4

Mark 1

Level 2

Qno 111

Question MPEG stands for

Sno 1

Type Mcq

A Media picture Experts Group

B Moving Picture Experts Group

C Media picture experts gain

D Moving picture experts gain

Answer B

Topic Chapter-4

Mark 1

Level 3

Qno 112
 Which of the following is not a type of memory?
a)
Question b)
c)
d)

Sno 1

Type Mcq

A RAM

B FPROM

C EEPROM

D ROM

Answer C

Topic Chapter-4

Mark 1

Level 3

Qno 113

If a RAM chip has n address input lines then it can access memory
Question
locations upto __________

Sno 1

Type Mcq

A 2(n-1)

B 2(n+1)

C 2n

D 22n

Answer C

Topic Chapter-4

Mark 1
Level 3

Qno 114

Question Static RAM employs

Sno 1

Type Mcq

A BJT or MOSFET

B FET or JFET

C Capacitor or BJT

D BJT or MOS

Answer D

Topic Chapter-4

Mark 1

Level 3

Qno 115

Question Dynamic RAM employs

Sno 1

Type Mcq

A BJT or MOSFET

B FET or JFET

C Capacitor or BJT

D BJT or MOS

Answer A

Topic Chapter-4
Mark 1

Level 3

Qno 116

Question Which one of the following is volatile in nature?

Sno 1

Type Mcq

A ROM

B EROM

C PROM

D RAM

Answer D

Topic Chapter-4

Mark 1

Level 3

Qno 117

Question IrLAP stands for

Sno 1

Type Mcq

A IrDA instruction link Access protocol

B IrDA interrupt link Access protocol

C IrDA information link Access protocol

D IrDA Infrared link Access protocol

Answer D

Topic Chapter-4

Mark 1

Level 3

Qno 118

Question IrLMP stands for

Sno 1

Type Mcq

A IrDA Infrared link management protocol

B IrDA interrupt link management protocol

C IrDA information link Access protocol

D IrDA Infrared link memory protocol

Answer A

Topic Chapter-4

Mark 1

Level 3

Qno 119

Question IrOBEX stands for

Sno 1

Type Mcq

A IrDA oriented expert protocols

B IrDA object expert protocols

C IrDA object exchange protocols

D IrDA oriented exchange protocols

Answer C

Topic Chapter-4

Mark 1

Level 3

Qno 120

Question The structure of Fire wire type is

Sno 1

Type Mcq

A Layer based

B Packet based

C Layer & packet based

D Spiral based

Answer C

Topic Chapter-4

Mark 1

Level 3

Qno 121

Question Which of the following are applications of film wire

Sno 1

Type Mcq

A Disk drivers and

B Printers &scanners
C cameras

D All of these

Answer D

Topic Chapter-5

Mark 1

Level 1

Qno 122

Question Fire wire type is also known as

Sno 1

Type Mcq

A IEEE1394

B IEEE1346

C IEEE1394b

D IEEE1346b

Answer A

Topic Chapter-5

Mark 1

Level 1

Qno 123

Question IEEE1394b speed is about

Sno 1

Type Mcq
A 3200Kbps

B 400Kbps

C 400Mbps

D 3200Mbps

Answer D

Topic Chapter-5

Mark 1

Level 1

Qno 124

Question Which of the following is/are not a data transfer type ?

Sno 1

Type Mcq

A Control

B Isochronous

C Bulk

D Instruction

Answer D

Topic Chapter-5

Mark 1

Level 1

Qno 125

Question Which of the following are valid for Hubs?

Sno 1

Type Mcq

A Hub is a bridge

B Hub is a single upstream connection

C Hub is a USB device

D All of these

Answer D

Topic Chapter-5

Mark 1

Level 1

Qno 126

Question Host controller initiates data transfer by generating

Sno 1

Type Mcq

A Data request

B Token packet

C Data packet

D Token request

Answer C

Topic Chapter-5

Mark 1

Level 1
Qno 127

Question Which of the following is/are serial interfaces?

Sno 1

Type Mcq

A IEEE1394,IrDA

B Bus protocol

C PIPE

D All of these

Answer D

Topic Chapter-5

Mark 1

Level 1

Qno 128

Question Expand ISA protocol

Sno 1

Type Mcq

A Internet standard architecture protocol

B Industry standard application protocol

C Industry standard architecture protocol

D Internet standard application protocol

Answer C

Topic Chapter-5

Mark 1

Level 1
Qno 129

Question ISA protocol address bit length is

Sno 1

Type Mcq

A 16

B 20

C 32

D 36

Answer B

Topic Chapter-5

Mark 1

Level 1

Qno 130

The master controls all the slave units at the same time operation is done
Question
in

Sno 1

Type Mcq

A Centralized parallel protocol

B Daisy chain protocol

C Distributed protocol

D Distributed parallel protocol

Answer A
Topic Chapter-5

Mark 1

Level 1

Qno 131

The master controls all the slave units one after another in specific time
Question
this operation is done in

Sno 1

Type Mcq

A Centralized parallel protocol

B Daisy chain protocol

C Distributed protocol

D Distributed parallel protocol

Answer B

Topic Chapter-5

Mark 1

Level 2

Qno 132

A bus slave responds to a write or read operation within a given address-

Question
space range is called

Sno 1

Type Mcq

A AHB

B AHP

C BHP
D None

Answer A

Topic Chapter-5

Mark 1

Level 2

Qno 133

Question Expand AHB

Sno 1

Type Mcq

A Advanced High impedance Bus

B Advanced High performance Bus

C Advanced High driving Bus

D Advanced High run Bus

Answer B

Topic Chapter-5

Mark 1

Level 2

Qno 134

Question AMBA stands for

Sno 1

Type Mcq

A Application specific Microprocessor Bus Architecture

B Advanced Microprocessor Bus Architecture

C Advanced Microcontroller Bus Architecture

D Application specific Microcontroller Bus Architecture

Answer C

Topic Chapter-5

Mark 1

Level 2

Qno 135

Question ASB stands for

Sno 1

Type Mcq

A Application System Bus

B Application Serial Bus

C Advanced Serial Bus

D Advanced System Bus

Answer D

Topic Chapter-5

Mark 1

Level 2

Qno 136

Question APB stands for

Sno 1

Type Mcq

A Application Peripheral Bus

B Advanced Parallel Bus

C Advanced Peripheral Bus

D Application parallel Bus

Answer C

Topic Chapter-5

Mark 1

Level 2

Qno 137

Question In Cortex-M designs the used Bus is

Sno 1

Type Mcq

A ASP

B ASB

C AHB

D APB

Answer C

Topic Chapter-5

Mark 1

Level 2

Qno 138

Question The PCI follows a set of standards primarily used in _____ PC’s.

Sno 1

Type Mcq

A Intel

B Motorola

C IBM
D SUN

Answer C

Topic Chapter-5

Mark 1

Level 2

Qno 139

Question The key feature of the PCI BUS is

Sno 1

Type Mcq

A Low cost connectivity

B Expansion of Bandwidth

C None

D Plug and Play capability

Answer D

Topic Chapter-5

Mark 1

Level 2

Qno 140

Question PCI stands for

Sno 1

Type Mcq

A Peripheral Computer Internet

B Processor Computer Interconnect

C Peripheral Component Interconnect

D Processor Cable Interconnect

Answer C

Topic Chapter-5

Mark 1

Level 2

Qno 141

Question The PCI BUS supports _____ address space/s.

Sno 1

Type Mcq

A I/O

B Memory

C Configuration

D All of the mentioned

Answer D

Topic Chapter-5

Mark 1

Level 3

Qno 142

Question ____ provides a separate physical connection to the memory

Sno 1

Type Mcq

A PCI BUS
B PCI interface

C PCI bridge

D Switch circuit

Answer C

Topic Chapter-5

Mark 1

Level 3

Qno 143

Question instructions fetched by CPU according to the value of —— from memory?

Sno 1

Type Mcq

A program status word

B program counter

C status register

D instruction register

Answer B

Topic Chapter-5

Mark 1

Level 3

Qno 144

Question the address generated by CPU is:

 A.
B.
C.
D. mac address

Sno 1

Type Mcq

A physical address

B Offset address

C logical address

D absolute address

Answer C

Topic Chapter-5

Mark 1

Level 3

Qno 145

Which of the followingdo the operation for virtual to physical address run-
Question
time mapping?

Sno 1

Type Mcq

A Memory management unit

B CPU

C PCI

D Operating system

Answer A

Topic Chapter-5
Mark 1

Level 3

Qno 146

Question Which is used to point the address of a page table in memory?

Sno 1

Type Mcq

A page register

B program counter

C stack pointer

D page table base register

Answer C

Topic Chapter-5

Mark 1

Level 3

Qno 147

Question ——- is contained by the page table

Sno 1

Type Mcq

A page size

B base address of every page

C page offset
D Page

Answer B

Topic Chapter-5

Mark 1

Level 3

Qno 148

Question a process is copied into the main memory from the secondary memory

Sno 1

Type Mcq

A Swapping

B Paging

C Segmentation

D Demand paging

Answer D

Topic Chapter-5

Mark 1

Level 3

Qno 149

When a program tries to access a page that is mapped in address space

Question
but not loaded in physical memory, then what occurs

Sno 1
Type Mcq

A page fault occurs

B fatal error occurs

C segmentation fault occurs

D no error occurs

Answer A

Topic Chapter-5

Mark 1

Level 3

Qno 150

what memory is called separation of user logical memory and physical

Question
memory

Sno 1

Type Mcq

A Memory sharing

B Virtual memory

C Memory management

D Memory control

Answer B

Topic Chapter-5

Mark 1

Level 3
Qno 151

technique is implemented by magnetic disk for secondary memory is

Question called

Sno 1

Type Mcq

A Main memory

B Cache

C Buffer

D Virtual memory

Answer D

Topic Chapter-6

Mark 1

Level 1

Qno 152

The main importance of ARM micro-processors is providing operation

Question
with ______

Sno 1

Type Mcq

A Efficient memory management

B Lower error or glitches

C Higher degree of multi-tasking

D Low cost and low power consumption

Answer D

Topic Chapter-6
Mark 1

Level 1

Qno 153

Question ARM processors where basically designed for

Sno 1

Type Mcq

A Mobile systems

B Main frame systems

C Super computers

D Distributed systems

Answer A

Topic Chapter-6

Mark 1

Level 1

Qno 154

Question The address space in ARM is

Sno 1

Type Mcq

A 264

B 232

C 216

D 224
Answer B

Topic Chapter-6

Mark 1

Level 1

Qno 155

Memory can be accessed in ARM systems by __________ instructions.

i) Store
Question ii) MOVE
iii) Load
iv) arithmetic

Sno 1

Type Mcq

A i, ii, iii

B i, ii

C i, iv

D iii, iv

Answer B

Topic Chapter-6

Mark 1

Level 1

Qno 156

Question The additional duplicate register used in ARM machines are called as

Sno 1
Type Mcq

A Copied-registers

B Banked registers

C Extra registers

D Extential registers

Answer B

Topic Chapter-6

Mark 1

Level 1

Qno 157

Question Each instruction in ARM machines is encoded into __________ Word.

Sno 1

Type Mcq

A 2 byte

B 8 byte

C 3 byte

D 4 byte

Answer D

Topic Chapter-6

Mark 1

Level 1

Qno 158
 The effective address of the instruction written in Post-indexed mode,
Question
MOVE[Rn]+Rm is

Sno 1

Type Mcq

A EA = [Rn]

B EA = [Rn + Rm]

C EA = [Rn] + Rm

D EA = [Rm] + Rn

Answer A

Topic Chapter-6

Mark 1

Level 1

Qno 159

Which converts the programs written in assembly language into machine

Question
instructions.

Sno 1

Type Mcq

A Machine compiler

B Assembler

C Interpreter

D Converter

Answer B

Topic Chapter-6

Mark 1

Level 1
Qno 160

Question The instructions like MOV or ADD are called as

Sno 1

Type Mcq

A Operators

B OP-Code

C Commands

D Comments

Answer B

Topic Chapter-6

Mark 1

Level 1

Qno 161

Question The alternate way of writing the instruction, ADD #5,R1 is

Sno 1

Type Mcq

A ADD #5,[R1]

B ADDIME 5,[R1];

C ADDI 5,R1;

D ADD [5],[R1];

Answer C

Topic Chapter-6

Mark 1
Level 2

Qno 162

Question Instructions which won’t appear in the object program are called as

Sno 1

Type Mcq

A Redundant instructions

B Exceptions

C Handler

D Assembler Directives

Answer D

Topic Chapter-6

Mark 1

Level 2

Qno 163

Question Which directive specifies the end of execution of a program.

Sno 1

Type Mcq

A End

B Return

C Stop

D Terminate

Answer B

Topic Chapter-6
Mark 1

Level 2

Qno 164

Question Which BUS arbitration approach uses the involvement of the processor.

Sno 1

Type Mcq

A Centralised arbitration

B Distributed arbitration

C Random arbitration

D Daisy chain arbitration

Answer A

Topic Chapter-6

Mark 1

Level 2

Qno 165

Question Which of the following are the components of microcontroller?

Sno 1

Type Mcq

A RAM

B ROM

C Timers

D All the above

Answer D
Topic Chapter-6

Mark 1

Level 2

Qno 166

Which of the following component of basic ES architecture relates DAC

Question
result with expected result?

Sno 1

Type Mcq

A Sensor

B Processor

C Actuator

D Timer

Answer C

Topic Chapter-6

Mark 1

Level 2

Qno 167

Which of the following is an example of direct type addressing mode in

Question
ES?

Sno 1

Type Mcq

A MOV A, #6AH

B MOV A, 04H

C MOV A, R4
D All the above

Answer B

Topic Chapter-6

Mark 1

Level 2

Qno 168

Question Which directive is used to indicate the beginning of the address?

Sno 1

Type Mcq

A EQU

B ORG

C END

D START

Answer B

Topic Chapter-6

Mark 1

Level 2

Qno 169

Question JB bit, target Instructions used for?

Sno 1

Type Mcq

A jump to target if bit = 0 (jump if no bit)

B jump to target if bit = 1, clear bit (jump if bit, then clear)

C jump to target if bit = 1 (jump if bit)

D None of the above

Answer C

Topic Chapter-6

Mark 1

Level 2

Qno 170

Question ALE stands for?

Sno 1

Type Mcq

A Address Length Enable

B Active Latch Enable

C Address Latch Enable

D Active Length Enable

Answer C

Topic Chapter-6

Mark 1

Level 2

Qno 171

Question What is the first part of each instruction called?

Sno 1

Type Mcq

A Opcode
B Mnemonic

C Both

D None

Answer C

Topic Chapter-6

Mark 1

Level
3

Qno 172

Question Which instruction is used for timing delays to waste clock cycles?

Sno 1

Type Mcq

A NOP

B RETURN

C CLR

D RST

Answer A

Topic Chapter-6

Mark 1

Level
3

Qno 173

Which system software is used to convert a "C" language program in to

Question
language of another processor?

Sno 1
Type Mcq

A Compiler

B Cross compiler

C Linker

D Cross linker

Answer B

Topic Chapter-6

Mark 1

Level
3

Qno 174

Question Which of the following is/are features of embedded software?

Sno 1

Type Mcq

A Timeliness

B Concurrency

C Heterogeneity

D All of these

Answer D

Topic Chapter-6

Mark 1

Level
3

Qno 175
 To measure dynamic efficiency of a networked embedded system
Question
______is required.

Sno 1

Type Mcq

A Number of PC cycles

B Number of CPU cycles

C Number of Interrupts cycles

D Number of instruction cycles

Answer B

Topic Chapter-6

Mark 1

Level
3

Qno 176

Question Which Runs on host to produce code for target

Sno 1

Type Mcq

A Compiler

B Cross assemblers

C Linker

D Cross linker

Answer B

Topic Chapter-6

Mark 1

Level
3
Qno 177

Question COEF stands for

Sno 1

Type Mcq

A Control object file format

B Combined object file format

C Common object file format

D Compiler object file format

Answer C

Topic Chapter-6

Mark 1

Level
3

Qno 178

Question ELF stands for

Sno 1

Type Mcq

A Extended Linker format

B Extra Linker format

C Executional Linker format

D Exceptional Linker format

Answer A

Topic Chapter-6
Mark 1

Level
3

Qno 179

Question Which of the following is/are the features of high level programming ?

Sno 1

Type Mcq

A Recursion

B Dynamic allocation

C Typing

D All of these

Answer D

Topic Chapter-6

Mark 1

Level
3

Qno 180

In which type of allocation at run time in stack for variables defined in

Question every function

Sno 1

Type Mcq

A Static

B Dynamic

C Automatic
D Fixed

Answer C

Topic Chapter-6

Mark 1

Level
3

Section 2

Sno 2

Name SECTION-2

Time 60

Mark 2

Negative 0

Questions - S2

Qno 181

Define Embedded system with examples and List out the types of
Question
embedded systems?

Sno 2

Type Sq

Topic Chapter-1

Mark 2

Level 1
Qno 182

Question Distinguish between Von neumann and Harvard architectures?

Sno 2

Type Sq

Topic Chapter-1

Mark 2

Level 1

Qno 183

Question List out few differences between Base line PIC and Midrange PIC ?

Sno 2

Type Sq

Topic Chapter-2

Mark 2

Level 1

Qno 184

Question Write a short note on Watch dog timer operation ?

Sno 2

Type Sq

Topic Chapter-2
Mark 2

Level 1

Qno 185

Question Write a short note on addressing modes of midrange PIC?

Sno 2

Type Sq

Topic Chapter-3

Mark 2

Level 1

Qno 186

List out all processor modes of ARM and its corresponding status
Question
registers?

Sno 2

Type Sq

Topic Chapter-3

Mark 2

Level 1

Qno 187

Question Explain the pipeline operation in ARM processor?

Sno 2
Type Sq

Topic Chapter-4

Mark 2

Level 2

Qno 188

Question Write down the applications and algorithms of Digital Signal Processing ?

Sno 2

Type Sq

Topic Chapter-4

Mark 2

Level 2

Qno 189

Question Write a short note on virtual memory ?

Sno 2

Type Sq

Topic Chapter-5

Mark 2

Level 2

Qno 190
Question Write a short note on Embedded system operating system?

Sno 2

Type Sq

Topic Chapter-6

Mark 2

Level 2

Qno 191

Question What are the features of software of embedded system?

Sno 2

Type Sq

Topic Chapter-6

Mark 2

Level 2

Qno 192

Question Explain the basic structure of an embedded system ?

Sno 2

Type Sq

Topic Chapter-1

Mark 2

Level 3
Qno 193

What are the PIC assembly language programming tools/building blocks

Question
?

Sno 2

Type Sq

Topic Chapter-2

Mark 2

Level 3

Qno 194

Write the instruction format of byte oriented ,bit oriented ,literal and
Question
control instructions?

Sno 2

Type Sq

Topic Chapter-2

Mark 2

Level 3

Qno 195

Question Explain all versions of ARM processors?

Sno 2

Type Sq

Topic Chapter-3
Mark 2

Level 3

Qno 196

Question What are the features of Digital signal processors ?

Sno 2

Type Sq

Topic Chapter-4

Mark 2

Level 2

Qno 197

Question Write a short note on all bus protocols?

Sno 2

Type Sq

Topic Chapter-5

Mark 2

Level 2

Qno 198

Question Explain briefly about multi-processor networks?

Sno 2
Type Sq

Topic Chapter-6

Mark 2

Level 2