42pq30r Manual
42pq30r Manual
This Section of the Presentation will cover troubleshooting the Y-SUS Board for the Single
Scan Plasma. Upon completion of the Section the technician will have a better
understanding of the operation of the circuit and will be able to locate voltage and
resistance test points needed for troubleshooting and alignments.
• Adjustments
• DC Voltage and Waveform Checks
• Resistance Measurements
Operating Voltages
SMPS Supplied VA VA supplies the Panel Vertical Grid (Routed to the X-Boards)
VS VS Supplies the Panel Horizontal Grid (Also routed to the Z-SUS)
M5V 5V Supplies Bias to Y-Z SUS, (Routed to the Control Board)
Y-Z SUS Developed -VY VR502 -VY Sets the Negative excursion of the Y SUS Drive Waveform
VSC VR501 VSC Set the amplitude of the complex waveform.
V SET UP VR601 Ramp UP sets amplitude of the Top Ramp of the Drive Waveform
V SET DN VR602 V Set Down sets the Pitch of the Bottom Ramp of the Drive Waveform
15V To the Control Board then routed to the Z-SUS board
Floating Ground FG 5V Used on the Y-Drive boards (Measured from Floating Gnd)
Y-Drive board
P201
VS, VA and M5V Input
P203 from the SMPS
SET UP
VR 601
P203, P208 and P205
All Floating Ground
V SET DN
VSC TP VR 401
P208 R520/J263
-VY TP
R201 P206 Vs to Z-SUS
5V and 15V
Floating Gnd 5V P101 Logic Signals
Pins 4 and 5 P207 from the
Ribbon
Control Board
Pins 7, 8, 9, 10 and 11 P202
Logic (Drive) Signals to
VSC ADJ P202
-VY ADJ 15V TP
the Y Drive Boards VR501 Va to Left X Board
VR502 J269
Pins 1, 2 and 3
1. Scan Sig
2. Scan Sig
FL1 3. n/c
4. 5V FG 5V measured from
5. 5V FG Floating Gnd
Pins 4 or 5 P207
P205
6. SUS Dn
7. CLK
8. STB
9. OC1
10. DATA
11. n/c P207 Pins 7, 8, 9, 10 and 11
12. SUS_Dn Logic (Drive) Signals to the Y
Drive Boards
Bottom Connector P207
Lower
Left Side
Of Board
-Vy TP
VR502
VR501
Just below Heat Sinks
-
VSC TP R520 / J263
J263
Vsc TP
+
Set should run for 15 minutes, this is the “Heat Run” mode. R520
Set screen to “White Wash” mode or 100 IRE White input.
528V p/p
Fig 1:
As an example of how to lock in to the Y-Drive Waveform.
Fig 1 shows the signal locked in at 4ms per/div. Note the Outlined
2 blanking sections. The signal for SET-UP or SET-DN is Area Fig 1
outlined within the Waveform 4mS
Area to
be adjusted
Fig 2: Fig 2
At 2mSec per/division, the waveform area to use for 2mS
SET-UP or SET-DN is now becoming clear. Blanking
Area to
Fig 3: be adjusted
At 400us per/div. the signal for SET-UP or SET-DN is now Fig 3
easier to recognize. It is outlined within the Waveform 400uS
Fig 5: Area to
At 40uSec per/division, the adjustment for be adjusted
SET-DN can be made.
Fig 4 40uS Fig 5 40uS
Observe the Picture while making these adjustments. Normally, they do not have to be done.
SET-UP ADJUST:
1) Adjust VR601 and set the (A) portion of the
signal to match the waveform above.
SET-DN ADJUST:
2) Adjust VR401 and set the (B) time of the
signal to match the waveform above.
ADJUSTMENT LOCATION:
Just to the bottom right of the right hand heat sink.
Ramp (Vset UP) too low Very little alteration to the picture, the wave form indicates a
distorted Vset UP. The peek widens due to the Vset UP
peeking too quickly.
Vset DN too high All of the center washes out due to increased Vset_DN time.
Distributes 15V
Y Drive Board
Display Panel
Receives Scan Waveform
30N45T 30N45T
IRGP4086
Forward: 0.6V Forward: 0.6V Forward: 0.39V ~ 0.5V
Reverse: Shorted Reverse: Shorted Reverse: Open
K3667 K3667 K3667
Forward: 0.22V Forward: 0.5V Forward: 0.4V ~ 0.5V
Reverse: Open Reverse: Open Reverse: Open
1 Vs 0V *193V Open
2 Vs 0V *193V Open
3 NC NC NC NC
6 Va 0V *60V Open
7 Va 0V *60V Open
9 M5V 0V 5V 1.1V
10 M5V 0V 5V 1.1V
* Note: This voltage will vary in accordance with Panel Label
Diode Mode Readings taken with all Connectors Disconnected. DVM in Diode Mode.
Diode Mode Readings taken with all Connectors Disconnected. DVM in Diode Mode.
Diode Mode Readings taken with all Connectors Disconnected. DVM in Diode Mode.
FS201
5V to run the Control Board.
Also sent to the Z-SUS Board.
Routed through the Control Board.
Leaves the Control Board on P101 pins 10. P101
Pin Label STBY Run Diode Mode Pin Label STBY Run Diode Mode
1 Gnd Gnd 0V Gnd 2 n/a 0V 0.12V 0.65V
3 n/a 0V 0.1V 0.65V 4 n/a 0V 0.13V 0.65V
5 n/a 0V 1.28V 0.65V 6 n/a 0V 0.2V 0.65V
7 n/a 0V 0V 0.65V 8 n/a 0V 1.05V 0.65V
9 n/a 0V 0.6V 0.65V 10 n/a 0V 0.17V 0.65V
11 n/a 0V 2.96V 0.65V 12 n/a 0V 2.5V 0.65V
13 n/a 0V 1.4V 0.65V 14 n/a 0V 0V 0.65V
15 n/a 0V 0V 0.65V 16 n/a 0V 0V 0.65V
17 n/a 0V 1.89V 0.65V 18 n/a 0V 0V Open
19 n/a 0V 2.16V 0.65V 20 Gnd Gnd Gnd Gnd
21 Gnd Gnd Gnd Gnd 22 Gnd Gnd Gnd Gnd
23 Gnd Gnd Gnd Gnd 24 5V 0V 5V 0.44V
25 5V 0V 5V 0.44V 26 5V 0V 5V 0.44V
27 5V 0V 5V 0.44V 28 5V 0V 5V 0.44V
29 15V 0V 15V Open 30 15V 0V 15V Open
Diode Mode Readings taken with all Connectors Disconnected. DVM in Diode Mode.
P207
Pin Label Voltage
1) VSC 140V
2) VSC 140V
3) Nc
4) 5V VF 5V
5) 5V VF 5V
6) SUS_DN FGnd
7) CLK 0.96V
8) STB 2.3V
9) OC1 2.3V
10) DATA 0V
11) Nc
12) SUS_DN FGnd
FG 20V
IC507
FG 15V
FG
D508
FG20V
17V
T502 FG
D509 FG 9V
IC508
FG9V
D509
Read 17V from Chassis Ground Read FG voltages from Floating Ground