Scribd Logo
Upload

Welcome to Scribd!

  • 111 views

    Sample Midterm Exam Questions

    Uploaded by

    Ishan Jawa
    1. The document contains sample exam questions for a computer architecture course. 2. The questions cover topics like cache organization, cache hit/miss rates, page tables, and calculating CPI given clock speeds and cache characteristics. 3. Diagrams and calculations are used to demonstrate concepts like direct-mapped cache mapping and determining memory access times in clock cycles.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Sample Midterm Exam Questions

    Uploaded by

    Ishan Jawa
    111 views2 pages
    1. The document contains sample exam questions for a computer architecture course. 2. The questions cover topics like cache organization, cache hit/miss rates, page tables, and calculating CPI given clock speeds and cache characteristics. 3. Diagrams and calculations are used to demonstrate concepts like direct-mapped cache mapping and determining memory access times in clock cycles.

    Original Description:

    ques

    Original Title

    sample_questions_1_solutions

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    1. The document contains sample exam questions for a computer architecture course. 2. The questions cover topics like cache organization, cache hit/miss rates, page tables, and calculating CPI given clock speeds and cache characteristics. 3. Diagrams and calculations are used to demonstrate concepts like direct-mapped cache mapping and determining memory access times in clock cycles.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    111 views2 pages

    Sample Midterm Exam Questions

    Uploaded by

    Ishan Jawa
    1. The document contains sample exam questions for a computer architecture course. 2. The questions cover topics like cache organization, cache hit/miss rates, page tables, and calculating CPI given clock speeds and cache characteristics. 3. Diagrams and calculations are used to demonstrate concepts like direct-mapped cache mapping and determining memory access times in clock cycles.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    CSci 360 Computer Architecture 3 Prof.

    Stewart Weiss
    Sample Midterm Exam Questions

    Sample Midterm Exam Questions


    1. Suppose a computer has a 4-way set associative cache with one-word blocks. It has a capacity of 256
    bytes. Given the sequence of byte addresses 8, 64, 96, 128, 64, 96, 256, 192, 24 show the nal cache
    contents and state the number of hits and misses.
    The block addresses for this sequence are 2, 16, 24, 32, 16, 24, 64, 48, 6. There are 256/(4*4) = 16
    sets. Therefore, the mapping of block address to sets is block_addr % 16. The sequence generates the
    following table. Empty sets are not shown. The currently accessed cache block is in boldface. The
    notation m[i] means the word located at memory address i.
    byte # block # set # set0 set0 set0 set0 set2 set6 set8
    block0 block1 block2 block3 block0 block0 block0
    8 2 2 miss m[8]
    64 16 0 miss m[64] m[8]
    96 24 8 miss m[64] m[8] m[96]
    128 32 0 miss m[64] m[128] m[8] m[96]
    64 16 0 hit m[64] m[128] m[8] m[96]
    96 24 8 hit m[64] m[128] m[8] m[96]
    256 64 0 miss m[64] m[128] m[256] m[8] m[96]
    192 48 0 miss m[64] m[128] m[256] m[192] m[8] m[96]
    24 6 6 miss m[64] m[128] m[256] m[192] m[8] m[24] m[96]
    There were 7 misses and 2 hits.

    2. A machine has a base CPI of 2 clock cycles. Measurements obtained show that the instruction miss
    rate is 12% and the data miss rate is 6%, and that on average, 30% of all instructions contain one data
    reference. The miss penalty for the cache is 10 cycles. What is the total CPI?
    Effective CPI = 2.0 + instruction miss cycles + data miss cycles
    = 2.0 + 0.12*10 + 0.30*0.06*10 = 2.0 + 1.2 + 0.18
    = 3.38

    3. A machine has a 500MHz system clock. Memory takes 30 ns to access a word. How many clock cycles
    is this?
    Clock cycles to access a word
    = 30 ns/(1 clock cycle) * ( 500 * 10^6 clock cycles/sec) * ( 1 sec/10^9 ns)
    = 30 * 500 * 10^6 * 10^-9
    = 15000 * 10^-3 = 15 clock cycles

    4. A machine has a 32-bit virtual address space and a 16KB page size. It has 1GB of physical memory.
    How many pages does a process have? How many bytes are needed for a page table, assuming 4 control
    bits and that disk addresses are stored elsewhere?
    Pages per process = 2^32 bytes * (1 page / 16*2^10 bytes) = 2^32 / 2^14
    = 2^18 = 256K pages

    5. A machine with a two level cache has a base CPI of 1.5 when all references hit the primary cache.
    Given the following characteristics:
    • a clock rate of 250MHz
    • memory access time of 100ns

    1
    CSci 360 Computer Architecture 3 Prof. Stewart Weiss
    Sample Midterm Exam Questions

    • miss rate at the primary cache of 5%


    • secondary cache access time of 10ns
    • miss rate at secondary cache of 1%

    what is the total CPI?


    The clock rate of 250 MHz implies a clock cycle of length 4 ns (because 1/(250*10^6) = 4 * 10^-9.
    Therefore the memory access time is 25 cycles and the secondary cache access time is 2.5 cycles.
    The effective CPI = 1.5 + cycles missed by primary but caught by secondary
    + cycles missed by both caches
    = 1.5 + (0.05 - 0.01)*2.5 + 0.01*( 2.5 + 25 )
    = 1.5 + 0.1 + 0.275 = 1.875

    6. Draw a picture showing the organization of a direct-mapped cache with 16 words per block, with
    a capacity of 128KB. Show any multiplexors, gates, needed. Show how a 32-bit physical address is
    mapped to a cache block.
    Cache capacity is 128KB. Each block has 16*4 = 64 bytes. There are 128K/64 = 2K = 2048 blocks.
    The bytes oset is 2 bits, the word oset is 4 bits (16 = 2^4) and the index is 11 bits since 2K = 2^11.
    That leaves 15 bits for the tag.

    You might also like