Microprocessor and Assembly Language

Course Code: 343 ALL

CHAPTER 3
Hardware Scheme for Data Transfer and Interrupts
Lecture Notes
 memory

address thousands

CHAPTER 3
Memory

•Memory is the storage device which can be used to store monitor program, users program
or users data.
cells ‫ وﻛل ﻋﻧوان ﯾﺗﻘﺳم اﯾﺿﺎ‬thousands ‫ﻣﻛﺎن ﻣﻘﺳم‬
• The memory consists of the thousands of memory cells arranged to store data.

•Each memory cell is capable of storing 1 bit of the data. 0 or 1

‫ﻋﺷﺎن ﺗﺷﺗﻐل اﻟذاﻛره ﻻزم اوﺻﻠﮭﺎ ب اﻟﻣﺎﯾﻛرو ﺑروﺳﯾﺳر‬
•Hence, to use memory to store programs or data of user or system, memory must be
interfaced with microprocessor properly, so that it can be accessed while reading or writing
data or program from/to it .

• In the same way, input and output devices are also required to read or write data out from
the microprocessor using input device such as keyboard or output device.
‫ﻻزم اوﺻل اﺟﮭزه اﻻدﺧﺎل واﻻﺧراج ﺑﺎﻟﻣﺎﯾﻛرو ﺑروﺳﯾﺳر‬
So, these devices must be interfaced properly with the microprocessor so that user can read
data from input device and write data to the output device.
 ‫ﻋﻧده ﻧوﻋﯾن‬
Hardware Scheme for Data Transfer
The two methods of interfacing memory or I/O devices with the microprocessor are
as follows:
a) I/O mapped I/O ‫اﺟﮭزه اﻻدﺧﺎل واﻻﺧراج ﺗﺗﺣﻛم ﻓﻲ اﺟﮭزه اﻻدﺧﺎل واﻻﺧراج‬
b) Memory mapped I/O ‫اﻟذاﻛره ﺗﺗﺣﻛم ﻓﻲ اﺟﮭزه اﻻدﺧﺎل واﻻﺧراج‬
a) I/O mapped I/O
In this technique, I/O device is treated as a I/O device and memory as memory.
MEMORY
eight address lines
• Each I/O device uses eight address lines. eight address lines
8BIT ‫ طرﯾﻘﮫ‬256 ‫ﺗﺳﻣﺢ ﻟﻲ اﺗﻌﺎﻣل ﻣﻊ‬

• If eight address lines are used to interface to generate the address of the I/O port, then
256 input and 256 output devices can be interfaced with the microprocessor.

• The address bus of the 8085 microprocessor is 16 bit, so we can either use lower order
address lines i.e. A0 – A7 or higher order address lines i.e. A8 – A15 to address I/O devices
where the address available on A0 – A7 will be copied on the address lines A8 – A15 .

•In I/O mapped I/O, the complete 64 Kbytes of memory can be interfaced as all address
lines can be used to address memory locations as the address space is not shared among
I/O devices and memory and 256 input and /or output devices.

‫ ﺑت اﻟﻰ ﻗﺳﻣﯾن‬16 ‫ﻧﻘﺳم ال‬

A0-A7 AND A8 -A15
‫اﻗدر اﺗﻌﺎﻣل ﻣﻊ ﻛل ﺟزء ﻟﺣﺎل‬
 ‫اﻟﻌﯾوب‬

a) I/O mapped I/O

Contd…
‫ﻣﺎﺗﻘدر ﺗﻧﻘل اي داﺗﺎ اﻻ ﺑﯾن ﺷﯾﺋﯾن اﻻﻧﺑوت اوت ﺑوت واﻻﻛﻣﯾوﻟﯾﺗر‬
‫ اﻟﺗﻌﺎﻣل ﻓﻘط ﻣﻊ ال‬Accumulator register
• In this type, the data transfer is possible between accumulator A register and I/O
devices only.

• Address decoding is simple, as less hardware is required.

•The separate control signals are used to access I/O devices and memory such as IOR,
IOW for I/O port and MEMR, MEMW for memory hence memory location are protected
from the I/O access.

•But in this type, arithmetic and logical operation are not possible directly.

•Also we cannot use other register for data transfer between I/O device and
microprocessor accepts A register.
 I/O mapped I/O

The figure below shows interfacing I/O devices in I/O mapped I/O.
 b)Memory mapped I/O

In this technique, I/O devices are treated as memory and memory as memory, hence the address of the
I/O devices are as same as that of memory i.e. 16 bit for 8085 microprocessor.

• So, the address space of the memory i.e. 64 Kbytes will be shared by the I/O devices as well as by
memory.

• All 16 address lines i.e. A0-A15 is used to address memory locations as well as I/O devices.

• The control signals MEMR and MEMW are used to access memory devices as well as I/O devices.

• The data transfer is possible between any register of the microprocessor and I/O device or memory
device.

• Hence, all memory related instructions can be used to access devices as they are treated as memory
devices.

• Address decoding of the I/O devices and memory devices are complicated and expensive as more
hardware is required.

• The 8085 microprocessor can access either 64 K I/O ports or memory locations, hence the total
numbers of the I/O ports and memory locations should not be greater than 64 K.

• I/O devices and memory locations are distinguished by the addresses only.
 b) Memory mapped I/O
Contd…

• Arithmetic and logical operation can be performed directly on the I/O devices.

• Most of the memory instructions are long; hence it reduces the speed of I/O.

• Normally, the speed of the I/O devices are very slow, hence the common interface used in
memory mapped I/O will reduce the speed of memory access unnecessarily.
 Memory mapped I/O

The figure below shows interfacing I/O devices inMemory mapped

I/O.
Exercise

• Write 8 differences between IO mapped IO and memory mapped IO.

https://www.geeksforgeeks.org/difference-between-memory-mapped-io-and-io-
mapped-io-with-reference-to-8085-microprocessor/
 Interrupts

When the microprocessor executes a program, the instructions are executed one by one,
usually without any interruption. The normal sequence of operation can be interrupted in 8085 by
some external signal applied to one of its interrupt pins or by one of the ‘restart’ instructions.

• Interrupt requests are classified into following two categories.

• Maskable interrupt requests.
• Unmaskable interrupt requests.

Maskable interrupt requests:

• The microprocessor can ignore or delay a maskable interrupt request if it is
performing some critical task.

Unmaskable interrupt requests.

• The microprocessor has to respond to a non maskable interrupt request without
any delay.
 The 8085 microprocessor interrupts are,

• INTR
• RST 5.5
• RST 6.5
• RST 7.5
• TRAP

The interrupt process is enabled by writing the instruction EI in main

program.
The instruction EI sets the interrupt enable flip flop. The instruction
DI resets the flip flop and disables the interrupt process.
EI – Enable Interrupt
DI- Disable Interrupt
Generation of RST codes:

The 8085 instruction set includes eight RST(Restart) instructions. These are one byte
CALL instructions and transfer the program execution to a specific memory location.

The RST instructions, the opcodes and the branch addresses are given below.

Instruction Branch Address

RST 0 0000
RST 1 0008
RST 2 0010
RST 3 0018
RST 4 0020
RST 5 0028
RST 6 0030
RST 7 0038
Main Program
•
2500
2501 0028 H
.
. .
. .
2505 RST 5
2506
•
•
250A HLT
Vectored Interrupts
• Vectored interrupts are automatically vectored(transferred) to specific memory
location, without any external hardware.
• These interrupts do not require INTA signal at an input port.
• Interrupt and their call location are as follows.

TRAP 0024H

RST 7.5 003CH

RST 6.5 0034H

RST 5.5 002CH

TRAP has highest priority followed by RST 7.5, RST 6.5, RST 5.5
Non Vectored Interrupt

• INTR is a maskable interrupt having least priority. It is a non vectored interrupt.

• If INTR is high and interrupt enable flip flop is set, microprocessor completes the
execution of current instruction, disables the interrupt enable flip flop and sends a
signal called INTA (Interrupt Acknowledge).

• The microprocessor cannot accept any interrupt request until interrupt enable flip
flop is set again.

• The signal INTA is used to insert a RST (Restart) instruction or call instruction through
external hardware.

• RST instruction transfers the program execution control to corresponding memory

location.

• When microprocessor receives an RST instruction it saves the address of next

instruction in the main program in the stack for future reference.
SIM instruction

• SIM stands for set interrupt mask.

• This is a 1 byte instruction.
• SIM reads the content of the accumulator and enables or disables the interrupts
according to the contents of accumulator.
• Bit D3 is the control bit and should be equal to 1 for bits D0, D1, D2 to be effective.
• Logic 0 in D0, D1 and D2 will enable the corresponding interrupt and logic 1 will
disable the interrupts.
0 ‫ ﯾﻌﻧﻲ‬enable
• Bit D4 is for controlling RST 7.5. If D4= 1 RST 7.5 is reset. 1 ‫ ﯾﻌﻧﻲ‬disenalbe
TRAP interrupt:
• TRAP is a non maskable interrupt (NMI).

• It has highest priority among all interrupt signals.

• When this interrupt is triggered the program control is transferred to location 0024H
without any external hardware or the interrupt enable instruction EI.

• TRAP is generally used for such critical events as power failure and emergency shut off.

RST 5.5, RST 6.5, RST 7.5:

To activate one of these interrupts, three conditions must be satisfied.

•The voltage on the pin should rise from 0 to 1 state.

•The interrupt enable flip flop must be set using EI instruction.

•These interrupts must be available (i.e) not masked in SIM instruction.

Example 1:
Write a program to enable interrupts RST 7.5, RST 6.5 and RST 5.5.
EI ; Enable interrupt
MVI A,08 ; Load bit pattern to enable RST 7.5, 6.5 and 5.5
SIM ; Enable RST 7.5, 6.5 and 5.5

Bit D3 = 1 in the accumulator makes the instruction SIM functional. The bits D2, D1
and D0 are all equal to zero and this enables the interrupts 7.5, 6.5 and 5.5.

Example 2:
Write a program to enable interrupts RST 7.5, RST 6.5 and disable RST 5.5.
EI ; Enable interrupt
MVI A,09 ; Load bit pattern to enable RST 7.5, 6.5 and disable 5.5
SIM ; Enable RST 7.5, 6.5 and disable 5.5

Bit D3 = 1 in the accumulator makes the instruction SIM functional. The bits D2, D1 are
all equal to zero and this enables the interrupts 7.5, 6.5. Bit D0 =1 therefore 5.5 is
disabled.