MIDTERMS IN COMPUTER ARCHITECTURE

Addressing modes

A – contents of an address filed in the instruction

R - contents of an address filed in the instruction that refers to a register

EA – Actual (effective) address of the location containing the referenced operand

(X) – contents of memory location X or register X

Most Common Addressing Technique

1. Immediate Addressing
• The simplest form of addressing, in which the operand value is present in the
instruction.
• Operant = A
• The advantage is that no memory reference other than the instruction fetch is
required to obtain the operand.
• The disadvantage is that the size of the number is restricted to the size of the
address field.
2. Indirect Addressing
• The address filed refer to the address of a word in memory, which in turn
contains a full-length address of the operand.
• EA=(A)
• The obvious advantage of this approach is that for a word length of N, an
address space of 2n is now available.
• The disadvantage is that instruction execution requires two memory references
to fetch the operand: one to get its address and a second to get its value.
3. Register Addressing
• Similar to direct addressing, the only difference is that the address field refers to a
register rather than a main memory address.
• EA = R
• To clarify, if the contents of a register address field in an instruction is 5, then
register R5 is the intended address, and the operand value is contained in R5.
• The advantages are (1) only a small address field is needed in the instruction, and (2)
no time-consuming memory references are required because the memory access
time for a register internal to the processor is much less than that for a main
memory address.
• The disadvantage is that the address space is very limited.
4. Register Indirect Addressing
• This is analogous to indirect addressing, the only difference is whether the address
field to a memory location or a register.
• EA = (R)
• The advantages and limitations are basically the same as for indirect addressing.
• It uses one less memory reference than indirect addressing.
5. Displacement Addressing
• Combines the capabilities of direct addressing and register indirect addressing.
• EA = A + (R)
• The value contained in one address field ( value = A) is used directly. The other
address field, or an implicit reference based on opcode, refers to a register whose
contents are added to A to produce the effective address.
• Most Common uses of displacement addressing:
• Relative addressing
 • Also called PC-relative addressing, the implicitly referenced register
is the program counter (PC). The next instruction address is added
to the address field to produce the EA.
• The effective address is a displacement relative to the address of
the instruction.
• Base-Register Addressing
• The referenced register contains a main memory address, and the
address field contains a displacement from that address.
• The register reference may be explicit or implicit.
• Indexing
• The address field references a main memory address, and the
referenced register contains a positive displacement from that
address. This usage is just the opposite of the interpretation for
base-register.
• An important use of indexing is to provide an efficient mechanism
for performing iterative operations.
• For example, a list of numbers stored starting at location. A Suppose
that we would like to add 1 to each element on the list. We need to
fetch each value, and 1 to it, and store it back. The sequence of
effective addresses that we need is A,A+1,A+2…,up to the last
location on the list.
• The value A is stored in the instruction’s address field, and the
chosen register, called an index register, is initialized to 0. After
each operation, the index register is incremented by 1.
• Because index registers are commonly used for such iterative tasks,
it is typical that there is a need to increment or decrement the index
register after each reference to it. Because this is such a common
operation, some systems will automatically do this as part of the
same instruction cycle.
• If general-purpose registers are used, the autoindex operation may
need to be signaled by a bit in the instruction.
• Autoindexing using increment can be depicted as follows:
• EA=A+(R)
• (R);(R)+1
• In some machines, both indirect addressing and indexing are
provided, and it is possible to employ both in the same instruction.
• If indexing is performed after the indirection, it is termed
postindexing:
• EA=(A) +R
• First, the contents of the address field are used to access a memory
location containing a direct address. This address is then indexed by
the register value.
• With preindexing, the indexing is performed before the indirection:
 • EA=(A+(R))
• An address is calculated as with simple indexing. In this case,
however, the calculated address contains not the operand, but the
address of the operand.
• Stack Addressing
• It is sometimes referred to as a pushdown list or last-in-first-out queue. The
stack is reserved block of locations.
• Items are appended to the top of the stack so that, at any given time, the
block is partially filled.
• Associated with the stack is a pointer whose value is the address of the top
of the stack.
• Alternatively, the top two elements of the stack may be in processor
registers, in which case the stack pointer references the third elements of
the stack.
• The stack pointer is maintained in a register. Thus, references to stack
locations in memory are in fact register indirect addresses.
• The stack mode of addressing is a form of implied addressing. The machine
instructions need no include a memory reference but implicitly operate on
the top of the stack.

Mode Algorithm Principal Principal

Advantage Disadvantage
Immediate Operand=A No memory Limited operand
reference magnitude
Direct EA=A Simple Limited address
space
Indirect EA=(A) Large address Multiple memory
space references
Register EA=R No memory Limited address
references space
Register Indirect EA=(R) Large address Extra memory
space reference
Displacement EA=A+(R) Flexibility Complexity
Stack EA=top of stack No memory Limited
references applicability

X86 Addressing Modes

o Addressing Modes
▪ OPCODE – Operation Code
▪ It tells the microprocessor which instruction or operation to perform
▪ OPCODE DESTINATION, SOURCE
▪ MOV CX, BX
o Types of Addressing Mode

▪ Register Addressing
• Transfer a byte or word from the source register or memory location to
the destination register or memory location.
• MOV AX, BX
Type REGISTER
Instruction MOV AX, BX
Source Register BX
Address Generation NONE
Destination Register AX
▪ Immediate Addressing
• Transfers an immediate byte or word of data into the destination
register or memory location.
• MOV BL,3AH
Type IMMEDIATE
Instruction MOV BL,3AH
Source Data equal to 3AH
Address Generation NONE
Destination Register BL
▪ Direct Addressing
• Transfers a byte or word between a memory location and a register.
• MOV [1234H], AX
Type DIRECT
Instruction MOV [1234H], AX
Source Register AX
Address Generation Displacement +(DS*10H)
DS=1000H
1234H +1000H
Destination Memory location 11234H

▪ Register Indirect Addressing

• Transfers a byte or word between a register and a memory location and
addressed by an Index or Base Register.
• MOV [BX], AX
Type REGISTER INDIRECT
Instruction MOV [BX], AX
Source Register AX
Address Generation BX+(DS*10H)
DS=1000H BX=0300H
Destination Memory location 10300H

▪ Base-plus-index addressing
• Transfer a byte or word between a register and a memory location
addressed by Base Register plus an Index Register.
 • MOV[BX+SI], AX
Type BASEPLUS-INDEX
Instruction MOV[BX+SI], AX
Source Register AX
Address Generation BX+SI+(DS*10H)
DS=1000H BX=0300H SI=0200H
Destination Memory location 10500H

▪ Register Relative Addressing

• Transfers a byte or word between a register and a memory location
addressed by Base Register or an Index Register plus a displacement.
• MOV[BX+4H], AX
Type REGISTER RELATIVE
Instruction MOV[BX+4H],AX
Source Register AX
Address Generation BX+4H+(DS*10H)
DS=1000H BX=0300H
Destination Memory location 10304H

▪ Base Relative-Plus-index Addressing

• Transfers a byte or word between a register and a memory location
addressed by Base Register an Index Register and a displacement.
• MOV ARRAY[BX+SI], AX
Type BASE RELATIVE-PLUS-INDEX
Instruction MOV ARRAY[BX+SI], AX
Source Register AX
Address Generation BX+ARRAY+SI(DS*10H)
DS=1000H BX=0300H SI=0200H
ARRAY=1000H
Destination Memory location 11500H

▪ Scaled-index Addressing
• Available in 80386 and 80486. The 2nd register is multiplied by a scaling
actor to generate the operand memory address.
• MOV [EBX+4*ESI], AX
Type SCALED INDEX
Instruction MOV [EBX+4*ESI], AX
Source Register AX
Address Generation EBX+(4* SI)+(DS*10H)
DS=1000H BX=0300H SI=0200H
Destination Memory location 11100H
o X86 addressing
Mode Algorithm
Immediate Operand =A
 Register Operand LA=R
Displacement LA=(SR)+A
Base LA(SR)+(B)
Base with Displacement LA=(SR)+(B)+A
Scaled Index with Displacement LA=(SR)+(I)*S+A
Base with index and displacement LA=(SR)+(B)+(I)+A
Base with Scaled index and displacement LA=(SR)+(I)*S+(B)+A
Relative LA=(PC)+A

LA= Linear Address

(X)=Content of X
SR= Segment Register
PC= Program Counter
A = Content of an address field in the instruction
R = Register
B= Base Register
I=Index Register
S= Scaling Factor

ARM Addressing
o ARM – Advanced RISC(Reduced instruction Set Computing) Machines

o LOAD/STORE ADDRESSING

▪ Load and store instructions are the only instructions that reference memory.
This is always done indirectly through a base register plus offset.
▪ There are three alternatives with respect to indexing:
• Offset
• Preindex
• Postindex
o OFFSET
▪ An offset value is added to or subtracted from the value in the base register to
form the memory address.
▪ As an example from the previous figure, illustrates this method with the
assembly language.
▪ STRB r0,[r1,#12]
▪ This is the store byte instruction. In this case the base address is in register r1
and the displacement is an immediate value of decimal 12.
▪ The resulting address (base plus offset) is the location where the least
significant byte from r0 is to be stored.

o PREINDEX
▪ The memory address is also written back to the base register.
▪ The base register value is incremented or decremented by the offset value.
 ▪ From the previous figure, illustrates this method with the assembly language
instruction
▪ STRBr0,[r1,#12]!
▪ The exclamation point signifies preindexing
o POSTINDEX
▪ The memory address is the base register value. An offset is added to or
subtracted from the base register value and the result is written back to the
base register.
▪ Figure illustrates this method with the assembly language instruction.
▪ STRB r0, [r1],#12
▪ The value in the offset register is scaled by one of the shift operators: logical
Shift Left, Logical, Shift Right, Arithmetic Shift right, Rotate right, or Rotate right
extended (which includes the carry bit in the rotation).
▪ The amount of the shift is specified as an immediate value in the instruction.

o Data processing instruction addressing

▪ Data processing instructions use either register addressing of a mixture of
register and immediate addressing.
▪ For register addressing, the value in one of the register operands may be scaled
using one of the five shift operators defined.

o Branch Instructions
▪ The only form of addressing for branch instructions is immediate addressing
▪ The branch instruction contains a 24-bit value.
▪ For address calculation, this value is shifted left 2 bits, so hat the address is on a
word boundary.
▪ Thus the effective address rage is 32 MB from the program counter.

o Load/Store Multiple Addressing

▪ Load multiple instructions load a subset of the general-purpose registers from
memory.
▪ Stoer multiple instructions store a subset of the general-purpose registers from
memory.
▪ The list of registers for the load or store is specified in a 16-bit field in the
instruction with each but corresponding to one of the 16 registers.
▪ Load and Store multiple addressing modes produce a sequential range of
memory addresses.
▪ The lowest-numbered register is stored at the lowest memory address and the
highest-numbered register at the highest memory address.
▪ Four addressing modes are used: Increment after, increment before, decrement
after, and decrement before.
▪ A base register specifies a main memory address where register values are
stored in or loaded from in ascending or descending word locations.
 ▪ Incrementing or decrementing starts either before or after the first memory
access.

➢ Instruction Format
o Defines the layout of the bits of an instruction.
o It must include an opcode and, implicitly and explicitly, zero or more operands.
o Each explicit operand is referenced using one of the addressing modes.
➢ Instruction Format Length Design Issue
o Either the instruction length should be equal to the memory-transfer length or one
should be a multiple of the other.
o Memory transfer rate has not kept up with increase in processor speed.
o Memory can become a bottle neck if the processor can execute instructions faster than
it can fetch them. One solution to this problem is to use cache memory and another is
to use shorter instructions.
o Instruction length should be a multiple of the character length, which is usually 8 bits,
and of the length of fixed-point numbers.
➢ Allocation of Bits
o For a given instruction length, more opcodes obviously mean more bits in the opcode
field.
o For an instruction format of a given length, this reduces the number of bits available for
addressing.
o The use of variable-length opcodes is the answer for this. There is minimum opcode
length but additional operations may be specified by using additional bits in the
instruction.
 o For a fixed-length instruction, this leaves fewer bits for addressing. Thus is used for
those instructions that require fewer operands.
➢ Factors determining the use of the addressing bits
o Number of addressing modes
o Number of operands
o Register versus memory
o Number of register sets
o Address range
o Address granularity

X86 Instruction Format

o Instruction Prefix
▪ If present, consists of the LOCK prefix or one of the repeat prefixes.
▪ The LOCK prefix is used to ensure exclusive use of shared memory in
multiprocessor environments.
▪ The repeat prefixes specify repeated operation of a string, which enables the
x86 to process strings much faster than with a regular software loop.
o Repeat Prefix
▪ When the absolute REP prefix is present, the operation specified in the
instruction is executed repeatedly on successive elements of the string.
▪ The number of repetitions is specified in register CX.
o Segment Override
▪ Specifies which segment register an instruction should use, overriding the
default segment-register selection generated by the x86 for that instruction.
o Operand Size
▪ An instruction has a default operand size of 16 or 32 bits, and the operand prefix
switches between 32-bit and 16-bit operands.
o Address Size
▪ The processor can address memory using either 16- or 32-bit addresses.
 ▪ It determines displacement size in instructions and the size of address offsets
generated during effective address calculation.
o Opcode
▪ It is 1,2, or 3 bytes in length
▪ It may also include bits that specify if data is byte- or full-size,, direction of data
operation, and whether an immediate data field must be sign extended.
o Mod R/m
▪ It specifies whether an operand is in a register or in memory.
▪ If it is in memory, then fields within the byte specify the addressing mode to be
used:
▪ It consists of three fields:
• Mod field (2 bits) combines with the r/m filed to form 32 possible
values: 8 registers and 24 indexing modes.
• Reg/Opcode filed (3 bits) specify a register as the location of an
operand, or it can form part of the addressing-mode encoding in
combination with the Mod field.
o SIB
▪ It consists of three fields:
• Scale field (2 bits) specifies the scale factor for scaled indexing
• Index field (3 bits) specifies the index register
• Base field (3 bits) specifies the base register
o Displacement
▪ When the addressing-mode specifier indicates that a displacement is used, 8-,
16-, or 32-bit signed integer displacement field is added.
o Immediate
▪ Provides the value of an 8-, 16-, 32-bit operand.

Processor Organization
o Arithmetic/Logic Unit
o Where data are held temporarily and calculations takes place
o Control Unit
o Interprets and controls the execution of instructions.
o By following a sequence of actions that correspond to the fetch-execute cycle,
most of these actions are movements of data or addresses from one part of the
CPU to another.
o Determines the particular instruction to be executed by reading the contents of
the program counter (part of the CU)
o I/O Interface
o Corresponds in function roughly to the input and output baskets.
o Memory
o Stores data for further processing

o Concepts of Registers
o Register is a single, temporary storage location within the CPU used for a
particular purpose.
o It is used to hold a binary value manipulation, and/or for simple calculations.
o Register is different from memory in a way that they are not addressed as a
memory location would be, but instead are manipulated directly by the control
unit during the execution of instructions.
o Registers may be as small as a single bit or as wide as several bytes.

o Important Registers of the Simple Model Architecture

o Accumulator
▪ Are also known as a general-purpose register
▪ Holds the data that are used for arithmetic operations as well as the
results. It is also used to transfer data between different memory
locations, and between I/O and memory.

o PC (Program Counter)
▪ Holds the actual instruction being executed currently by the computer.

o MAR (Memory Address Register)

▪ Holds the address of a memory location

o MDR (Memory Data Register)

▪ Also known as memory buffer register
▪ Holds a data value that is beings tore to or retrieved from the memory
location currently addressed by the MAR.
▪ It is a two-way register

o Flag Register
 ▪ Are one-bit register that allows the computer to keep track of special
conditions such as arithmetic carry, overflow, sign, parity, zero, etc.
o Types of Operations of the Registers
o Registers can be loaded with values from other locations, in particular from
other registers or from memory locations. This operation destroys the previous
value stored in the register.
o Data from another location can be added to or subtracted from the value
previously stored in the register, leaving the sum or difference in the register.
o Data in the register can be shifted or rotated right or left by one or more bits.
o Registers can also be loaded with the value of zero, which is known as clearing.
o Taking the 1’s complement of the registers is known as inverting.
o Registers can also be incremented and decremented, that is to add or subtract a
value of 1 to the current value in the register.

o The Memory Unit

o A memory unit is consists of cells, each of which can hold a single value, and each of
which has a single address.
o The MAR and MDR acts as an interface between the CPU and the memory.
o Each group represents the data cells for a single memory address, as shown in the figure
000, 001, …. 2n-1.
o The MAR holds the address in the memory which is to be “opened” for data. It is also
connected to a decoder that interprets the address and activates a single address line
into the memory. There is separate address line for each group of cells in the memory;
thus of there are n bits of addressing, there will be 2n address lines.
o The MDR is designed such that it is effectively connected to every cell in the memory
unit. Each bit of the MDR is connected to the corresponding bit of every location in the
memory. However, the addressing method assures that only a single group of cells is
activated at any given time. Thus, only one memory location is addressed at one time.
o Address line
o There are three lines that control the memory cell: and address line, a read/write line,
and an activation line.
o The address line to a particular cell is turned on only if the computer is addressing the
data within that cell.
o R/W line
o The R/W line determines whether the data will be transferred from the cell to MDR
(read) or from the MDR to cell (write). This line works by turning on one of the two
switches in conjunction with the address line and activation line.
o The read switch, turns on when the address line and the activation in line are both on
the R/W line is set to read; the switch then connects the output of the cell to the MDR
line.
 o The write switch works similarly; the write switch, turn on when the address line and
the activation line are both on and the R/W line is set to write; the switch then connects
the MDR line to the input of the cell, which transfers the data bit on the MDR line to the
cell for storage.
o Activation Line
o The activation lien is turned on for the transfer to take place between memory and the
MDR.
o When the instruction being executed is to store data, the data will be transferred from
another register in the CPU to the MDR, and from there it will be transferred into
memory. The original data at that location will be destroyed, replaced by the new data
from the MDR.
o When the instruction is to load data from memory, the data is transferred from memory
to MDR, and it will subsequently be transferred to the appropriate register in the CPU.
In this case, the memory data are intact, but the previous data value in the MDR is
replaced by the new data from the memory.

o Interaction between the CPU and memory

1. To retrieve or store data at a particular memory location
2. The CPU copies can address from some register in the CPU to the MAR
3. The CPU sends a message to the memory unit indicating whether the memory transfer
is retrieval from memory or store to memory.

o Memory Capacity
o There are two factors that determine the capacity of the memory.
1. The number of bits in MAR determines how many different address locations
can be decoded. For MAR of width k bits, the number of possible memory
addresses is M=2k
2. The number of bits in the address field of the memory locations can be directly
addressed from the instructions.
o For example the CPU in the first PC supported memory capacity of 1 megabyte
(MB), but a typical MAR will be 32 bits wide allows a memory capacity of 4GB. Many
modern computers provide even more capacity.
o The size of the word to be retrieved or stored in a single operation is
determined by the size of the MDR.
o In most modern computers, data and instructions found in memory are
addressed in multiples of 8-bit bytes. This establishes the minimum
instruction size as 8 bits.
o Most instructions cannot fit practically into 8 bits. If one were to allow 3 bits
for the opcode (8 instruction types), only 5 bits remain for addressing that
makes 32 (25) different addresses, which is clearly insufficient address
space.
o As a result, longer instructions of 16, 24, 32 or even more bits will be stored
in successive memory locations.
 o It is generally desirable to retrieve an entire instruction with a single fetch
for faster processing.
o Data to be used in arithmetic calculations frequently requires the precision
of several bytes. Therefore, most modern computer memories are designed
to allow the retrieval or storage of four or more successive bytes in a single
operation.
o Thus, the MDR is usually designed to retrieve the data or instruction(s) from
a sequence of several successive all at once, and the MDR will be several
bytes wide.

o Memory implementations
o Through the history of computing there have been several different types of
memory used; the most popular and useful of theses have been magnetic
core memory, static RAM, dynamic RAM, and ROM.
o It is important to realize that the method used to access memory is basically
the same, regardless of its type, the only difference occurs with the ROM,
since the computer cannot write to ROM, the MDR will retrieve data from
ROM for the CPU.

o Magnetic Core Memory

o Uses a small core of magnetic material to hold a bit of data; electrical wires
woven through the core determine the magnetic polarity of the core to read
the data and change the polarity of the core to read the date and change
the polarity by passing electrical current through the wires.
o It is non-volatile (data remains even if the power is removed)
o Expensive and slow in operation
o Still used on few computers where both read and write capability are
required and where the loss of data or programs would be severely
damaging, particularly for military and space applications.

o Static Random Access Memory (Static RAM)

o Does not require refreshing
o Faster to access than DRAM and is therefore useful in very high-speed
memory.
o It is more expensive and required more chips.
o It is a volatile memory that its contents are lost when power is turned off.

o Dynamic Random Access Memory (Dynamic RAM)

o Also a volatile memory and is less expensive
o Requires less electrical power, and can be made smaller, with more bits of
storage in a single integrated circuit.
o It also requires extra electronic circuitry that refreshes memory periodically;
otherwise the data fades away after a while and is lost.
 o The amount of data that can be stored in a single chip has increased rapidly
that is why it is the most popular type of memory.

o Read-Only Memory
o Used for situations where the software is built permanently into the
computer, is required as part of the computer’s software and is not
expected to change over the life of the computer.
o Early ROM was made up of integrated circuits with fuses in them that could
be blown. A blown fuse might represent a “0” an intact fuse a “1”.
o Modern ROMs uses a different technology that is can be erased and
rewritten.
o It is non-volatile and unwritable, thus data does not change with power on
or off.

Memory Organization
o FETCH-EXECUTE INSTRUCTION CYCLE
▪ We will use the following notation to indicate the transfer of data from one
register to another:
• REG, REG →REG REG8

o FETCH-EXECUTE INSTRUCTION CYCLE

▪ The first step in the execution of every instruction is:
• PC →MAR

o FETCH-EXECUTE INSTRUCTION CYCLE

• The next step is to transfer that instruction to the instruction register:
▪ MDR→IR
▪ The instruction register will hold the instruction through the rest of the
instruction cycle. This step completes the fetch phase of the instruction cycle.
▪ The remaining steps are, of course, instruction dependent.

o FETCH-EXECUTE INSTRUCTION CYCLE (LOAD INSTRUCTION)

• The Little Girl will walk over to the mailbox specified by that address, read the data, and
copied it to the calculator. The real CPU will operate similarly, thus:
▪ IR [address] →MAR
▪ MDR - A
▪ The notation IR [address] is used to indicate that only the address part of the
contents of the instruction register is to be transferred

o FETCH-EXECUTE INSTRUCTION CYCLE

o The CPU increments the program counter, and the cycle is complete and ready to begin in the
next instruction:
o PC + 1 PC
 o FETCH-EXECUTE INSTRUCTION CYCLE (LOAD INSTRUCTION)

▪ The LOAD instruction requires five steps.

• Four of the steps simply involve the movement of data from one
register to another.
• The fifth step requires the addition of the value 1 to the contents of PC,
and the new value is returned to the same register.

o FETCH-EXECUTE INSTRUCTION CYCLE (STORE)

o PC → MAR
o MDR -IR
o IR [address] →→ MAR
o A → MDR
o PC + 1-PC

o BUSES
▪ Data moves between the various I/O modules, memory, and the CPU.
▪ The physical connection that makes it possible to transfer data from one
location in the computer system to another is called a bus.
▪ Bus may be defined as a group of electrical conductors suitable for carrying
computer signals from one location to another. Each conductor in a bus is
commonly known as a line.
▪ Each line carries a single electrical signal. The signal might represent bit of
memory address, or a sequence of data bits, or a timing control that turns a
device on and off at the proper time.
o Categories of Bus Lines
o Data Lines
▪ Carry the data that is being moved from one location to another.
o Address line
▪ Specify the recipient of data on the bus.
o Control Lines
▪ Provide control for the proper synchronization and operation of the bus and of
the modules that are connected to the bus.
o POINT-TO-POINT BUS
o A bus that carry a specific signal from the source to a specific destination.
o Addressing is not required, since the destination is already known.
o MULTIPOINT BUS
▪ sometimes called as multidrop bus or broadcast bus
▪ a bus that is used to connect several points together

o MULTIPOINT BUS
▪ Requires addressing signals on the bus to identify the desired destination that is
being addressed by the source at a particular time.
▪ But sometimes addressing is not required where the signal is actually intended
to reach all the other locations at once, this is sometimes the case for buses that
are internal to the CPU.

o BACKPLANE
▪ Also known as a system bus or external bus.
▪ A bus used to carry computer signals that connect the CPU with memory
and/or with a set of plug-in I/O module cards in the same physical package.
▪ One common method of connecting a CPU to memory and I/O modules is to
mount the CPU and its related components on a printed circuit board known as
a motherboard. The backplane in this case is part of the printed circuit wiring on
the motherboard.
 ▪ The bus interface units make it possible for the different buses to communicate with
each other.
▪ The buses connecting the various parts of the CPU are actually within the CPU chip.
▪ The CPU bus, Peripheral Component Interface (PCI) or Video Electronics Standards
Association (VESA) local bus, and Industry Standard Architecture (ISA) bus are all
part of the backplane.

o THE MOTHERBOARD
o The system bus on many motherboards is made up of three separate parts.
o The CPU bus (not visible in the picture) connects the CPU and memory.
 o The other two parts, are the PCI bus and the ISA bus, are used to connect various 1/0
peripheral components to the CPU.
o Plug-in connectors for these two buses can be seen in the picture.
o The actual PCI and ISA buses are printed on the bottom of the board and consist of
parallel wires connecting all the plug-in connectors together.

o BUSES CAN BE CHARACTERIZED BY:

▪ Throughput
▪ The data width in bits, of the data being carried
▪ The distance between the two end points
▪ The type of control required
▪ The type of bus (i.e. point-to-point or multipoint)
▪ The addressing capacity
▪ The bus must also be specified electrically and mechanically, by the number of
pins on the connector

o THROUGHPUT
o The data transfer rate measured in bits per second

o DEDICATED BUS
▪ Buses that are internal to the CPU are usually not characterized at all, since they
serve special purposes and do not interface to the outside world.
▪ The need to characterize buses comes from the necessity of interfacing the bus
to other devices that are part of the computer system.

o BUS PROTOCOL
o To use a bus, the circuits that are connected to the bus must agree on the bus protocol.
o In general, a protocol is an agreement between two or more entities that establishes a
clear, common path of communication and understanding between them.
o A specification that spells out the meaning of each line and each signal on each line for
this purpose.
o A particular control line on a bus might be defined as a line that determines if the bus is
to be used for memory read or memory write.
o Both the CPU and memory would have to agree, for example, that a "0" on the
particular line means "memory read" and a "1" means "memory write".
o The line might have a name like MREAD/MWRITE, where the bar over MWRITE means
that a "0" is the active state.

o THE ISA BUS

▪ ls a 16-bit backplane bus that interconnects the CPU and various plug-in 1/0
modules that control serial and parallel ports, sound cards, some disk drives,
 and the like. It provides 16 data lines, labelled DO through D15, 26 address lines,
labelled AO through A19 and LA17 through LA23, and various control and power
lines.
▪ The power lines provide required power for the plug-in 1/0 peripheral interface
cards.
▪ The control lines control timing, determine whether the CPU request is to
memory or 1/0, determine if a memory request is a read or a write, and perform
other similar functions.
▪ For 1/0 modules that require higher performance, particularly video modules,
the ISA bus is gradually being supplanted by the PCI and VESA buses.