AT8A53D v1.6 200320

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AT8A53D
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12 I/O 8-bit EPROM-Based MCU
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Version 1.6
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Mar. 20, 2020
ATW TECHNOLOGY CO. reserves the right to change this document without prior notice. Information provided by ATW is believed to be accurate and reliable. However, ATW
makes no warranty for any errors which may appear in this document. Contact ATW to obtain the latest version of device specifications before placing your orders. No
responsibility is assumed by ATW for any infringement of patent or other rights of third parties which may result from its use. In addition, ATW products are not authorized for
use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in
significant injury to the user, without the express written approval of ATW.
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Revision History
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Version Date Description Modified Page
1.0 2016/08/24 Formal release. -
1.1
1.2
2016/11/15
2017/05/23
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1. Add the description to Pin Description.
2. Modify Table 16 Configuration Words.
Modify “Input Voltage Level” options in Configuration Words.

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1.3 2017/11/15 Modify Table 14 Summary of /TO & /PD Value and its Associated Event. 50
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1. Modify the pin description of PB3. 11

1.4 2018/04/17
1.5 2018/07/20
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2. Update the DC Characteristics table.
1. Modify Figure 2 Program Memory Address Mapping.

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2. Update RLR instruction description.
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1.6 2020/03/20 Add OSC Characteristics. 71
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Table of Contents
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1. 概述 ······················································································································· 6
1.1 功能 ·························································································································· 6
1. General Description ································································································ 8

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1.1 Features ···················································································································· 8
1.2 Block Diagram··········································································································· 10
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1.3 Pin Assignment ········································································································· 10
1.4 Pin Description ·········································································································· 11
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2. Memory Organization ····························································································· 12

2.1 Program Memory ······································································································· 12
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2.2 Data Memory ············································································································ 13
3. Function Description ······························································································ 16

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3.1 R-page Special Function Register·················································································· 16
3.1.1 INDF (Indirect Addressing Register) ················································································· 16
3.1.2 TMR0 (Timer0 Register)································································································· 16
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3.1.3 PCL (Low Byte of PC[9:0]) ······························································································ 16

3.1.4 STATUS (Status Register) ······························································································ 17
3.1.5 FSR (Register File Selection Register) ·············································································· 17
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3.1.6 PortA (PortA Data Register) ···························································································· 18

3.1.7 PortB (PortB Data Register) ···························································································· 18
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3.1.8 PCON (Power Control Register) ······················································································ 18

3.1.9 BWUCON (PortB Wake-up Control Register) ······································································ 19
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3.1.10 PCHBUF (High Byte of PC) ···························································································· 19

3.1.11 ABPLCON (PortA/PortB Pull-Low Resistor Control Register)·················································· 19
3.1.12 BPHCON (PortB Pull-High Resistor Control Register) ··························································· 20
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3.1.13 INTE (Interrupt Enable Register) ······················································································ 20

3.1.14 INTF (Interrupt Flag Register)·························································································· 21
3.2 T0MD Register ·········································································································· 21
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3.3 F-page Special Function Register ·················································································· 22

3.3.1 IOSTA (PortA I/O Control Register) ·················································································· 22
3.3.2 IOSTB (PortB I/O Control Register) ·················································································· 23
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3.3.3 PS0CV (Prescaler0 Counter Value Register) ······································································ 23
3.3.4 BODCON (PortB Open-Drain Control Register) ··································································· 23
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3.3.5 PCON1 (Power Control Register1) ··················································································· 23
3.4 S-page Special Function Register ·················································································· 24
3.4.1 TMR1 (Timer1 Register)································································································· 24
3.4.2 T1CR1 (Timer1 Control Register1) ··················································································· 24
3.4.3
3.4.4
3.4.5
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T1CR2 (Timer1 Control Register2) ··················································································· 25
PWM1DUTY (PWM1 Duty Register) ················································································· 26
PS1CV (Prescaler1 Counter Value Register) ······································································ 26
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3.4.6 BZ1CR (Buzzer1 Control Register) ··················································································· 26
3.4.7 IRCR (IR Control Register) ····························································································· 27
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3.4.8 TBHP (Table Access High Byte Address Pointer Register) ···················································· 28
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TBHD (Table Access High Byte Data Register) ··································································· 28
3.4.10 OSCCR (Oscillation Control Register) ··············································································· 29
3.5 I/O Port···················································································································· 29
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3.5.1 Block Diagram of IO Pins ······························································································· 31
3.6 Timer0····················································································································· 38
3.7 Timer1/PWM1/Buzzer1 ······························································································· 39
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3.8 IR Carrier ················································································································· 41

3.9 Watch-Dog Timer (WDT) ····························································································· 42
3.10 Interrupt ··················································································································· 43
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3.10.1 Timer0 Overflow Interrupt ······························································································· 43

3.10.2 Timer1 Underflow Interrupt ····························································································· 43
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3.10.3 WDT Timeout Interrupt ·································································································· 44

3.10.4 PB Input Change Interrupt ······························································································ 44
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3.10.5 External Interrupt ·········································································································· 44

3.11 Oscillation Configuration ······························································································ 44
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3.12 Operating Mode········································································································· 46

3.12.1 Normal Mode ··············································································································· 48
3.12.2 Slow Mode ·················································································································· 48
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3.12.3 Standby Mode ············································································································· 48

3.12.4 Halt Mode ··················································································································· 49
3.12.5 Wake-up Stable Time ···································································································· 49
3.12.6 Summary of Operating Mode ·························································································· 50
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3.13 Reset Process··········································································································· 50
4. Instruction Set ······································································································· 52
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5. Configuration Words ······························································································ 68
6. Electrical Characteristics ························································································ 69

6.1 Absolute Maximum Rating ··························································································· 69
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6.2 DC Characteristics ····································································································· 69
6.3 OSC Characteristics ··································································································· 71
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6.4 Characteristic Graph ··································································································· 71
6.4.1 Frequency vs. VDD of I_HRC ··························································································· 71
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6.4.2 Frequency vs. Temperature of I_HRC ··············································································· 71
6.4.3 Frequency vs. VDD of I_LRC ···························································································· 72
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Frequency vs. Temperature of I_LRC················································································ 72
6.5 Recommended Operating Voltage ················································································· 72
6.6 LVR vs. Temperature ·································································································· 73
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7. Die Pad Diagram ···································································································· 73
8. Package Dimension································································································ 74
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8.1 8-Pin Plastic SOP (150 mil) ·························································································· 74

8.2 14-Pin Plastic SOP (150 mil) ························································································ 74
8.3 14-Pin Plastic DIP (300 mil)·························································································· 75
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9. Ordering Information ······························································································ 75

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1. 概述
AT8A53D是以EPROM作為記憶體的 8 位元微控制器，專為多IO產品的應用而設計，例如遙控器、風扇/燈光控制或
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是遊樂器周邊等等。採用CMOS製程並同時提供客戶低成本、高性能等顯著優勢。AT8A53D核心建立在RISC精簡指
令集架構可以很容易地做編輯和控制，共有 55 條指令。除了少數指令需要 2 個時序，大多數指令都是 1 個時序即能
完成，可以讓使用者輕鬆地以程式控制完成不同的應用。因此非常適合各種中低記憶容量但又複雜的應用。
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在I/O的資源方面，AT8A53D有 12 根彈性的雙向I/O腳，每個I/O腳都有單獨的暫存器控制為輸入或輸出腳。而且每一
個I/O腳位都有附加的程式控制功能如上拉或下拉電阻或開漏極(Open-Drain) 輸出。此外針對紅外線搖控的產品方
面，AT8A53D內建了可選擇頻率的紅外載波發射口。
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AT8A53D有兩組計時器，可用系統頻率當作一般的計時的應用或者從外部訊號觸發來計數。另外AT8A53D提供 1 組
8 位元解析度的PWM輸出或者蜂鳴器輸出，可用來驅動馬達、LED、或蜂鳴器等等。
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AT8A53D採用雙時鐘機制，高速振盪或者低速振盪都可以分別選擇內部RC振盪或外部Crystal輸入。在雙時鐘機制
下，AT8A53D可選擇多種工作模式如正常模式(Normal)、慢速模式(Slow mode)、待機模式(Standby mode) 與睡眠
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模式(Halt mode)可節省電力消耗延長電池壽命。並且微控制器在使用內部RC高速振盪時，低速振盪可以同時使用外
部精準的Crystal計時。可以維持高速處理同時又能精準計算真實時間。
在省電的模式下如待機模式(Standby mode)與睡眠模式(Halt mode)中，有多種事件可以觸發中斷喚醒AT8A53D進入

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正常操作模式(Normal) 或慢速模式(Slow mode) 來處理突發事件。
1.1 功能
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 寬廣的工作電壓：(指令週期為 4 個CPU clock，亦即 4T模式)

 2.0V ~ 5.5V @系統頻率≦8MHz。
 2.2V ~ 5.5V @系統頻率＞8MHz。
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 寬廣的工作温度：-40°C ~ 85°C。
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 1Kx14 bits EPROM。
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 64 bytes SRAM。
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 12 根可分別單獨控制輸入輸出方向的I/O腳(GPIO)、PA[3:0]、PB[7:0]。
 PA[3:0]及PB[3:0]可選擇輸入時使用內建下拉電阻。
PB[7:4]及PB[2:0]可選擇上拉電阻或開漏極輸出(Open-Drain)。
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 PB[3]可選擇當作輸入或開漏極輸出(Open-Drain)。
 8 層程式堆棧(Stack)。
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 存取資料有直接或間接定址模式。
 一組 8 位元上數計時器(Timer0)包含可程式化的頻率預除線路。
 一組 8 位元下數計時器(Timer1)可選重複載入或連續下數計時。
 一個 8 位元的脈衝寬度調變輸出(PWM1)。
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 一個蜂鳴器輸出(BZ1)。
 38/57KHz紅外線載波頻率可供選擇，同時載波之極性也可以根據數據作選擇。
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 紅外線載波發射口。
 內建上電復位電路(POR)。
 內建低壓復位功能(LVR)。

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內建看門狗計時(WDT)，可由程式韌體控制開關。
雙時鐘機制，系統可以隨時切換高速振盪或者低速振盪。
 高速振盪: E_HXT (超過 6MHz外部高速石英振盪)
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E_XT (455K~6MHz外部石英振盪)
I_HRC (1~20MHz內部高速RC振盪)
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 低速振盪: E_LXT (32KHz外部低速石英振盪)
I_LRC (內部 32KHz低速RC振盪)
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四種工作模式可隨系統需求調整電流消耗：正常模式(Normal)、慢速模式(Slow mode)、待機模式(Standby
mode) 與睡眠模式(Halt mode)。
五種硬體中斷：
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 Timer0 溢位中斷。
 Timer1 借位中斷。
 WDT 中斷。
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 PB 輸入狀態改變中斷。
 外部中斷輸入。
 AT8A53D在待機模式(Standby mode)下的五種喚醒中斷：
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 Timer0 溢位中斷。
 Timer1 借位中斷。
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 WDT 中斷。
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 AT8A53D在睡眠模式(Halt mode)下的三種喚醒中斷：
 WDT 中斷。
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1. General Description
AT8A53D is an EPROM based 8-bit MCU tailored for I/O based applications like remote controllers, fan/light
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controller, game controllers, toy and various controllers.AT8A53D adopts advanced CMOS technology to provide
customers remarkable solution with low cost and high performance. RISC architecture is applied to AT8A53D and it
provides 55 instructions. All instructions are executed in single instruction cycle except program branch and skip
instructions which will take two instruction cycles. Therefore, AT8A53D is very suitable for those applications that are
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sophisticated but compact program size is required.
As AT8A53D address I/O type applications, it can provide 12 I/O pins for applications which require abundant input
and output functionality. Moreover, each I/O pin may have additional features, like Pull-High/Pull-Low resistor and
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open-drain output type through programming. Moreover, AT8A53D has built-in infrared (IR) carrier generator with
selectable IR carrier frequency and polarity for applications which demand remote control feature.
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AT8A53D also provides 2 sets of timers which can be used as regular timer based on system oscillation or event
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counter with external trigger clock. Moreover, AT8A53D provides 1 set of 8-bit resolution Pulse Width Modulation
(PWM) output and buzzer output in order to drive motor/LED and buzzer.
AT8A53D employs dual-clock oscillation mechanism, either high oscillation or low oscillation can be derived from
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internal resistor/capacitor oscillator or external crystal oscillator. Moreover, based on dual-clock mechanism,
AT8A53D provides kinds of operation mode like Normal mode, Slow mode, Standby mode and Halt mode in order to
save power consumption and lengthen battery operation life. Moreover, it is possible to use internal high-frequency
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oscillator as CPU operating clock source and external 32KHz crystal oscillator as timer clock input, so as to accurate
count real time and maintain CPU working power.
While AT8A53D operates in Standby mode and Halt mode, kinds of event will issue interrupt requests and can
wake-up AT8A53D to enter Normal mode and Slow mode in order to process urgent events.
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1.1 Features
 Wide operating voltage range: (@ 4 CPU clock per instruction, i.e. 4T mode)
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 2.0V ~ 5.5V @system clock ≦8MHz.

 2.2V ~ 5.5V @system clock ＞8MHz.
 Wide operating temperature: -40°C ~ 85°C.

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 1K x 14 bits EPROM.
 64 bytes SRAM.
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 12 general purpose I/O pins (GPIO), PA[3:0], PB[7:0], with independent direction control.
 PA[3:0] and PB[3:0] have features of Pull-Low resistor for input pin.
 PB[7:4] and PB[2:0] have features of Pull-High resistor, and open-drain output.
 PB[3] have feature of input or open-drain output.
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 8-level hardware Stack.
 Direct and indirect addressing modes for data access.
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 One 8-bit up-count timer (Timer0) with programmable prescaler.
 One 8-bit reload or continuous down-count timers (Timer1).
 One 8-bit resolution PWM (PWM1) output.

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One buzzer (BZ1) output.
Selectable 38/57KHz IR carrier frequency and high/low polarity according to data value.
Built-in Power-On Reset (POR).

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 Built-in Low-Voltage Reset (LVR).
 Built-in Watch-Dog Timer (WDT) enabled/disabled by firmware control.
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 Dual-clock oscillation: System clock can switch between high oscillation and low oscillation.
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 High oscillation: E_HXT (External High Crystal Oscillator, above 6MHz)
E_XT (External Crystal Oscillator, 455K~6MHz)
I_HRC (Internal High Resistor/Capacitor Oscillator ranging from 1M~20MHz)
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 Low oscillation: E_LXT (External Low Crystal Oscillator, about 32KHz)
I_LRC (Internal 32KHz oscillator)
 Four kinds of operation mode to reduce system power consumption:

 Normal mode, Slow mode, Standby mode and Halt mode.
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 Five hardware interrupt events:

 Timer0 overflow interrupt.
 Timer1 underflow interrupt.
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 WDT timeout interrupt.

 PB input change interrupt.
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 External interrupt.
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 Five interrupt events to wake-up AT8A53D from Standby mode:

 Timer0 overflow interrupt.
 Timer1 underflow interrupt.
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 Three interrupt events to wake-up AT8A53D from Halt mode:

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1.2 Block Diagram
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1.3 Pin Assignment

AT8A53D provides three kinds of package type which are SOP14, DIP14 and SOP8.
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Figure 1 Package pin assignment
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1.4 Pin Description
Pin Name I/O Description
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PA0 ~ PA3 I/O Bidirectional I/O pins.
PB0 is a bidirectional I/O pin.

PB0/ INT/ SDI I/O PB0 is input pin of external interrupt when EIS=1 & INTIE=1.
PB0 can be programming pad SDI.
PB1/ IR/ SDO I/O

T WPB1 is a bidirectional I/O pin.
If IR mode is enabled, this pin is IR carrier output.
PB1 can be programming pad SDO.

It also can be timer clock source EX_CKI.
PB2/ EX_CKI/ PB2 can be programming pad SCK.
I/O
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PWM1/ BZ1/ SCK PB2 is output of PWM signal by configuration words.
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PB2 is output of Buzzer signal by configuration words.

PWM has higher priority over Buzzer functions.
PB3/ RSTb/ VPP

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I/O
PB3 is an input pin or open-drain output pin.
It can be reset pin RSTb. If RSTb pin is low, it will reset AT8A53D.
If this pin is more than 7.75V, it also can make AT8A53D enter EPROM
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programming mode.
PB4 is a bidirectional I/O pin if I_HRC and I_LRC are adopted. PB4 also can be
PB4/ Xout I/O output of instruction clock.
PB4 is output of external crystal if E_HXT, E_XT or E_LXT is adopted.
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PB5 is a bidirectional I/O pin if I_HRC and I_LRC are adopted.

PB5/ Xin I/O
PB5 is input of external crystal if E_HXT, E_XT or E_LXT is adopted.

PB6/ PWM1 I/O
PB6 is output of PWM signal by configuration words.
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PB7/ BZ1 I/O
PB7 is output of Buzzer signal by configuration words.
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VDD - Positive power supply.
VSS - Ground.
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2. Memory Organization
AT8A53D memory is divided into two categories: one is program memory and the other is data memory.
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2.1 Program Memory
The program memory space of AT8A53D is 1K words. Therefore, the Program Counter (PC) is 10-bit wide in
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order to address any location of program memory.
Some locations of program memory are reserved as interrupt entrance. Power-On Reset vector is located at
0x000. Software interrupt vector is located at 0x001. Internal and external hardware interrupt vector is located at
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0x008.
AT8A53D provides instruction CALL, GOTOA, CALLA to address 256 location of program space. AT8A53D
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provides instruction GOTO to address 512 location of program space. AT8A53D also provides instructions
LCALL and LGOTO to address any location of program space.
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When a call or interrupt is happening, next ROM address is written to top of the stack, when RET, RETIA or
RETIE instruction is executed, the top of stack data is read and load to PC.
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AT8A53D program ROM address 0x3FE~0x3FF are reserved space, if user tries to write code in these
addresses will get unexpected false functions.
AT8A53D program ROM address 0x00E~0x00F are preset rolling code can be released and used as normal
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program space.
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Figure 2 Program Memory Address Mapping
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2.2 Data Memory
According to instructions used to access data memory, the data memory can be divided into three kinds of
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categories: one is R-page Special-function Register (SFR) + General Purpose Register (GPR), another is
F-page SFR and the other is S-page SFR. GPR are made of SRAM and user can use them to store variables or
intermediate results.
R-page data memory is divided into 4 banks and can be accessed directly or indirectly through a SFR register
banks.
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which is File Select Register (FSR). FSR[7:6] are used as Bank register BK[1:0] to select one bank out of the 4
R-page register can be divided into addressing mode: direct addressing mode and indirect addressing mode.
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The indirect addressing mode of data memory access is described in the following graph. This indirect
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addressing mode is implied by accessing register INDF. The bank selection is determined by FSR[7:6] and the
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location selection is from FSR[5:0].
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Figure 3 Indirect Addressing Mode of Data Memory Access

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The direct addressing mode of data memory access is described below. The bank selection is determined by
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FSR[7:6] and the location selection is from instruction op-code[5:0] immediately.

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Figure 4 Direct Addressing Mode of Data Memory Access
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R-page SFR can be accessed by general instructions like arithmetic instructions and data movement
instructions. The R-page SFR occupies address from 0x0 to 0xF of Bank 0. However, the same address range
of Bank 1, Bank 2 and Bank 3 are mapped back to Bank 0. In other words, R-page SFR physically existed at
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Bank 0. The GPR physically occupy address from 0x10 to 0x3F of Bank 0 and 0x10 to 0x1F of Bank 1. Other
banks in address from 0x10 to 0x3F are mapped back as the Table 1 shows.
The AT8A53D register name and address mapping of R-page SFR are described in the following table.
Address
FSR[7:6]
0x0
T W 00
(Bank 0)
INDF
01
(Bank 1)
10
(Bank 2)
11
(Bank 3)
0x1 TMR0
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0x2 PCL
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0x3 STATUS
0x4
0x5
0x6
ec FSR
PORTA
PORTB
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0x7 -
The same mapping as Bank 0
0x8 PCON
0x9 BWUCON
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0xA PCHBUF
0xB ABPLCON
0xC BPHCON
0xD -
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0xE INTE
0xF INTF
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General Purpose General Purpose Mapped to Mapped to

0x10 ~ 0x1F
Register Register bank0 bank1
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General Purpose Mapped to

0x20 ~ 0x3F
Register bank0
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Table 1 R-page SFR Address Mapping
F-page SFR can be accessed only by instructions IOST and IOSTR. S-page SFR can be accessed only by
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instructions SFUN and SFUNR. FSR[7:6] bank select bits are ignored while F-page and S-page register is
accessed. The register name and address mapping of F-page and S-page are depicted in the following table.
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SFR Category
F-page SFR S-page SFR
Address
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0x0 - TMR1
0x1 - T1CR1
0x2 - T1CR2
0x3 - PWM1DUTY
0x4
0x5
0x6
T W -
IOSTA
IOSTB
PS1CV
BZ1CR
IRCR
0x7 - TBHP
0x8 - TBHD
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0x9 - -
0xA PS0CV -
0xB
0xC
0xD
ec -
BODCON
-
-
-
-
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0xE - -
0xF PCON1 OSCCR
Table 2 F-page and S-page SFR Address Mapping

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3. Function Description
This chapter will describe the detailed operations of AT8A53D.
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3.1 R-page Special Function Register
3.1.1 INDF (Indirect Addressing Register)
Name
INDF
SFR Type
R W
R/W Property
Initial Value
T Addr.
0x0
Bit7 Bit6 Bit5 Bit4
INDF[7:0]
R/W
xxxxxxxx
Bit3 Bit2 Bit1 Bit0
The register INDF is not physically existed and it is used as indirect addressing mode. Any instruction
accessing INDF actually accesses the register pointed by register FSR
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3.1.2
TMR0
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TMR0 (Timer0 Register)
Name SFR Type
R
Addr.
0x1
Bit7 Bit6 Bit5 Bit4
TMR0[7:0]
Bit3 Bit2 Bit1 Bit0
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R/W Property R/W
Initial Value xxxxxxxx
When read the register TMR0, it actually read the current running value of Timer0.
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Write the register TMR0 will change the current value of Timer0.
Timer0 clock source can be from instruction clock FINST, or from external pin EX_CKI, or from Low Oscillator
Frequency according to T0MD and configuration word setting.
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3.1.3 PCL (Low Byte of PC[9:0])

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Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PCL R 0x2 PCL[7:0]
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R/W Property R/W

Initial Value 0x00
The register PCL is the least significant byte (LSB) of 10-bit PC. PCL will be increased by one after one
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instruction is executed except some instructions which will change PC directly. The high byte of PC, i.e.
PC[9:8], is not directly accessible. Update of PC[9:8] must be done through register PCHBUF.
For GOTO instruction, PC[8:0] is from instruction word and PC[9] is loaded from PCHBUF[1]. For CALL
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instruction, PC[7:0] is from instruction word and PC[9:8] is loaded from PCHBUF[1:0]. Moreover the next PC
address, i.e. PC+1, will push onto top of Stack. For LGOTO instruction, PC[9:0] is from instruction word.
For LCALL instruction, PC[9:0] is from instruction word. Moreover the next PC address, i.e. PC+1, will push
onto top of Stack.
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3.1.4 STATUS (Status Register)
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STATUS R 0x3 GP7 GP6 GP5 /TO /PD Z DC C
R/W Property R/W R/W R/W R/W(*2) R/W(*1) R/W R/W R/W
Initial Value 0 0 0 1 1 X X X
The register STATUS contains result of arithmetic instructions and reasons to cause reset.
C: Carry/Borrow bit W
C=1, carry is occurred for addition instruction or borrow is not occurred for subtraction instruction.
C=0, carry is not occurred for addition instruction or borrow is occurred for subtraction instruction.
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DC: Half Carry/half Borrow bit
DC=1, carry from the 4th LSB is occurred for addition instruction or borrow from the 4th LSB is not
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occurred for subtraction instruction.

DC=0, carry from the 4th LSB is not occurred for addition instruction or borrow from the 4th LSB is
Z: Zero bit
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occurred for subtraction instruction.
Z=1, result of logical operation is zero.

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Z=0, result of logical operation is not zero.
/PD: Power down flag bit

/PD=1, after power-up or after instruction CLRWDT is executed.
W
/PD=0, after instruction SLEEP is executed.
/TO: Time overflow flag bit

/TO=1, after power-up or after instruction CLRWDT or SLEEP is executed.
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/TO=0, WDT timeout is occurred.
GP7, GP6, GP5: General purpose read/write register bit.

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(*1) can be cleared by sleep instruction.
(*2) can be set by clrwdt instruction.

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3.1.5 FSR (Register File Selection Register)

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FSR R 0x4 BK[1:0] FSR[5:0]

R/W Property R/W
Initial Value 0 0 X X X X X X
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FSR[5:0]: Select one register out of 64 registers of specific Bank.
BK[1:0]: Bank register used to select one specific bank of data memory. BK[1:0]=00b, Bank 0 is selected.
BK[1:0]=01b, Bank 1 is selected. BK[1:0]=10b, Bank 2 is selected. BK[1:0]=11b, Bank 3 is
selected.
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3.1.6 PortA (PortA Data Register)
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PortA R 0x5 GP7 GP6 GP5 GP4 PA3 PA2 PA1 PA0
R/W Property R/W
Initial Value Data latch value is xxxx, read value is xxxx port value(PA3~PA0)
While reading PortA, it will get the status of pins of PA regardless that pin is configured as input or output pin.
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While writing to PortA, data is written to PA’s data latch.
GP7 ~ GP4: general register.

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3.1.7 PortB (PortB Data Register)
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PortB R 0x6 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
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R/W Property
Initial Value
R/W
Data latch value is xxxxxxxx, read value is xxxxxxxx port value(PB7~PB0)
While reading PortB, it will get the status of pins of PB regardless that pin is configured as input or output pin.
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While writing to PortB, data is written to PB’s data latch.
3.1.8 PCON (Power Control Register)

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PCON R 0x8 WDTEN EIS GP5 GP4 LVREN GP2 GP1 GP0
R/W Property R/W
Initial Value 1 0 0 0 1 0 0 0
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GP4~0: General read/write register bits.

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LVREN: Enable/disable LVR.
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LVREN=1, enable LVR.

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LVREN=0, disable LVR.
EIS: External interrupt select bit

EIS=1, PB0 is external interrupt.
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EIS=0, PB0 is GPIO.
WDTEN: Enable/disable WDT.

WDTEN=1, enable WDT.
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WDTEN=0, disable WDT.
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3.1.9 BWUCON (PortB Wake-up Control Register)
SFR
Name Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Type
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BWUCON R 0x9 WUPB7 WUPB6 WUPB5 WUPB4 WUPB3 WUPB2 WUPB1 WUPB0
R/W Property R/W R/W R/W R/W R/W R/W R/W R/W
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WUPBx: Enable/disable PBx wake-up function, 0 ≤ x ≤ 7.
WUPBx=1, enable PBx wake-up function.
WUPBx=0, disable PBx wake-up function.
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3.1.10 PCHBUF (High Byte of PC)
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PCHBUF R 0xA - XSPD_STP - - - GP5 PCHBUF[1:0]
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R/W Property
Initial Value
-
X
PCHBUF[1:0]: Buffer of the 9th bit, 8th bit of PC.

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0
-
X
-
X
-
X
R/W
000
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GP5: General read/write register bit.
XSPD_STP: Write 1 to stop crystal 32.768K speed-up function, write-only.

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3.1.11 ABPLCON (PortA/PortB Pull-Low Resistor Control Register)

SFR Addr
Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Type .
/PLPB /PLPB /PLPB /PLPB /PLPA /PLPA /PLPA /PLPA
ABPLCON R 0xB
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3 2 1 0 3 2 1 0
R/W Property R/W
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/PLPAx: Disable/enable PAx Pull-Low resistor, 0 ≤ x ≤ 3.

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/PLPAx=1, disable PAx Pull-Low resistor.

/PLPAx=0, enable PAx Pull-Low resistor.
/PLPBx: Disable/enable PBx Pull-Low resistor, 0 ≤ x ≤ 3.

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/PLPBx=1, disable PBx Pull-Low resistor.

/PLPBx=0, enable PBx Pull-Low resistor.
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3.1.12 BPHCON (PortB Pull-High Resistor Control Register)
SFR
Type
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/PHPB5 /PHPB4
BPHCON R 0xC /PHPB7 /PHPB6 GP3 /PHPB2 /PHPB1 /PHPB0
(*1) (*1)
R/W Property R/W
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/PHPBx: Disable/enable PBx Pull-High resistor, 0 ≤ x ≤ 7.
/PHPBx=1, disable PBx Pull-High resistor.
/PHPBx=0, enable PBx Pull-High resistor.
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GP3: General read/write register bit.
Note: When PB4 and PB5 are used as crystal oscillator pads, the Pull-High resistor should not be
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enabled, or the oscillation may fail.
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3.1.13 INTE (Interrupt Enable Register)
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INTE R 0xE - WDTIE - - T1IE INTIE PBIE T0IE
R/W Property - R/W - - R/W R/W R/W R/W
Initial Value X 0 X X 0 0 0 0
T0IE: Timer0 overflow interrupt enable bit.

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T0IE=1, enable Timer0 overflow interrupt.

T0IE=0, disable Timer0 overflow interrupt.
PBIE: PortB input change interrupt enable bit.

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PBIE=1, enable PortB input change interrupt.

PBIE=0, disable PortB input change interrupt.
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INTIE: External interrupt enable bit.

INTIE=1, enable external interrupt.
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INTIE=0, disable external interrupt.
T1IE: Timer1 underflow interrupt enable bit.

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T1IE=1, enable Timer1 underflow interrupt.

T1IE=0, disable Timer1 underflow interrupt.
WDTIE: WDT timeout interrupt enable bit.

WDTIE=1, enable WDT timeout interrupt.
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WDTIE=0, disable WDT timeout interrupt.
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3.1.14 INTF (Interrupt Flag Register)
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INTF R 0xF - WDTIF - - T1IF INTIF PBIF T0IF
R/W Property - R/W - - R/W R/W R/W R/W
Initial Value(note*) 0 0 0 0 0 0 0 0
T0IF: Timer0 overflow interrupt flag bit.
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T0IF=1, Timer0 overflow interrupt is occurred.
T0IF must be clear by firmware.
PBIF: PortB input change interrupt flag bit.
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PBIF=1, PortB input change interrupt is occurred.
PBIF must be clear by firmware.
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INTIF: External interrupt flag bit.

INTIF=1, external interrupt is occurred.
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INTIF must be clear by firmware.
T1IF: Timer1 underflow interrupt flag bit.

T1IF=1, Timer1 underflow interrupt is occurred.
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T1IF must be clear by firmware.
WDTIF: WDT timeout interrupt flag bit.

WDTIF=1, WDT timeout interrupt is occurred.
W
WDTIF must be clear by firmware.

Note: When corresponding INTE bit is not enabled, the read interrupt flag is 0.
3.2 T0MD Register

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T0MD is a readable/writeable register which is only accessed by instruction T0MD / T0MDR.

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T0MD - - LCKTM0 INTEDG T0CS T0CE PS0WDT PS0SEL[2:0]

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R/W Property R/W

Initial Value(note*) 0 0 1 1 1 111
PS0SEL[2:0]: Prescaler0 dividing rate selection. The rate depends on Prescaler0 is assigned to Timer0 or
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WDT. When Prescaler0 is assigned to WDT, the dividing rate is dependent on which timeout
mechanism is selected.
Dividing Rate
PS0SEL[2:0]
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PS0WDT=0 PS0WDT=1 PS0WDT=1

(Timer0) (WDT Reset) (WDT Interrupt)
000 1:2 1:1 1:2
001 1:4 1:2 1:4
010 1:8 1:4 1:8
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011 1:16 1:8 1:16
100 1:32 1:16 1:32
101 1:64 1:32 1:64
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110 1:128 1:64 1:128
111 1:256 1:128 1:256
Table 3 Prescaler0 Dividing Rate
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PS0WDT: Prescaler0 assignment.
PS0WDT=1, Prescaler0 is assigned to WDT.
PS0WDT=0, Prescaler0 is assigned to Timer0.
Note: Always set PS0WDT and PS0SEL[2:0] before enabling watchdog or timer interrupt, or reset or
T
interrupt may be falsely triggered.
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T0CE: Timer0 external clock edge selection.
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T0CE=1, Timer0 will increase one while high-to-low transition occurs on pin EX_CKI.
ec
T0CE=0, Timer0 will increase one while low-to-high transition occurs on pin EX_CKI.
Note: T0CE is also applied to Low Oscillator Frequency as timer0 clock source condition.
T0CS: Timer0 clock source selection.

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T0CS=1, External clock on pin EX_CKI or Low Oscillator Frequency (I_LRC or E_LXT) is selected.
T0CS=0, Instruction clock FINST is selected.
INTEDG: Edge selection of external interrupt.

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INTEDG=1, INTIF will be set while rising edge occurs on pin PB0.
INTEDG=0, INTIF will be set while falling edge occurs on pin PB0.
LCKTM0: When T0CS=1, timer 0 clock source can be optionally selected to be low-frequency oscillator.
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T0CS=0, Instruction clock FINST is selected as timer0 clock source.

T0CS=1, LCKTM0=0, external clock on pin EX_CKI is selected as timer0 clock source.
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T0CS=1, LCKTM0=1, Low Oscillator Frequency (I_LRC or E_LXT, depends on configuration word
Low Oscillator Frequency) output replaces pin EX_CKI as timer0 clock source.
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Note: For more detail descriptions of timer0 clock source select, please see timer0 section.
3.3 F-page Special Function Register

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3.3.1 IOSTA (PortA I/O Control Register)

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IOSTA F 0x5 - - - - IOPA3 IOPA2 IOPA1 IOPA0

R/W Property - - - - R/W R/W R/W R/W
Initial Value X X X X 1 1 1 1
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IOPAx: PAx I/O mode selection, 0 ≤ x ≤ 3.
IOPAx=1, PAx is input mode.
IOPAx=0, PAx is output mode.
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3.3.2 IOSTB (PortB I/O Control Register)
IOSTB F
R/W Property
W
Initial Value
T 0x6 IOPB7
R/W
1
IOPB6
R/W
1
IOPB5
R/W
1
IOPB4
R/W
1
IOPB3
R/W
1
IOPB2
R/W
1
IOPB1
R/W
1
IOPB0
R/W
1
IOPBx: PBx I/O mode selection, 0 ≤ x ≤ 7.

IOPBx=1, PBx is input mode.
h
A
IOPBx=0, PBx is output mode.
3.3.3
PS0CV
ec
PS0CV (Prescaler0 Counter Value Register)
Name SFR Type
F
Addr.
0xA
Bit7 Bit6 Bit5 Bit4
PS0CV[7:0]
Bit3 Bit2 Bit1 Bit0
-T
R/W Property R
While reading PS0CV, it will get current value of Prescaler0 counter.

W
3.3.4 BODCON (PortB Open-Drain Control Register)

SFR
Type
T
BODCON F 0xC ODPB7 ODPB6 ODPB5 ODPB4 GP3 ODPB2 ODPB1 ODPB0
R/W Property R/W
h
A
ec
ODPBx: Enable/disable open-drain of PBx, 0 ≤ x ≤ 7.

ODPBx=1, enable open-drain of PBx.
ODPBx=0, disable open-drain of PBx.
-T
GP3: General purpose register bit.
3.3.5 PCON1 (Power Control Register1)

TW
PCON1 F 0xF GIE - GP5 GP4 GP3 GP2 GP1 T0EN
R/W Property R/W(1*) - R/W R/W R/W R/W R/W R/W
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T0EN: Enable/disable Timer0.
T0EN=1, enable Timer0.
T0EN=0, disable Timer0.
-T
GIE: Global interrupt enable bit.
GIE=1, enable all unmasked interrupts.
GIE=0, disable all interrupts.
W
GP1~5: General purpose read/write register.
(1*) : set by instruction ENI, clear by instruction DISI, read by instruction IOSTR.
T
3.4 S-page Special Function Register
h
3.4.1 TMR1 (Timer1 Register)
A
TMR1 ec
S
R/W Property
Initial Value
0x0 TMR1[7:0]
R/W
XXXXXXXX
-T
When reading register TMR1, it will obtain current value of 8-bit down-count Timer1. When writing register
TMR1, it will both write data to timer1 reload register and update Timer1 current content.
W
3.4.2 T1CR1 (Timer1 Control Register1)

T1CR1 S 0x1 PWM1OEN PWM1OAL - - - T1OS T1RL T1EN
T
R/W Property W W - - - R/W R/W R/W

Initial Value 0 0 X X X 0 0 0
h
A
This register is used to configure Timer1 functionality.
T1EN: Enable/disable Timer1.

ec
T1EN=1, enable Timer1.

T1EN=0, disable Timer1.
-T
T1RL: Configure Timer1 down-count mechanism while Non-Stop mode is selected (T1OS=0).
T1RL=1, initial value is reloaded from reload register TMR1.
T1RL=0, continuous down-count from 0xFF when underflow is occurred.
T1OS: Configure Timer1 operating mode while underflow is reached.

TW
T1OS=1, One-Shot mode. Timer1 will count once from the initial value to 0x00.
T1OS=0, Non-Stop mode. Timer1 will keep down-count after underflow.
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T1OS T1RL Timer1 Down-Count Functionality
Timer1 will count from reload value down to 0x00.

0 0
-T
When underflow is reached, 0xFF is reloaded and continues down-count.
Timer1 will count from reload value down to 0x00.

0 1
When underflow is reached, reload value is reloaded and continues to down-count.
Timer1 will count from initial value down to 0x00.

1 x
W When underflow is reached, Timer1 will stop down-count.
PWM1OAL: Define PWM1 output active state.

T
Table 4 Timer1 Functionality
PWM1OAL=1, PWM1 output is active low.

PWM1OAL=0, PWM1 output is active high.
h
A
PWM1OEN: Enable/disable PWM1 output.
ec
PWM1OEN=1, PWM1 output will be present on PB6.
PWM1OEN=0, PB6 is GPIO.
-T
3.4.3 T1CR2 (Timer1 Control Register2)
T1CR2 S 0x2 - - T1CS T1CE /PS1EN PS1SEL[2:0]
R/W Property - - R/W R/W R/W R/W R/W R/W
W
Initial Value X X 1 1 1 1 1 1
This register is used to configure Timer1 functionality.

T
PS1SEL[2:0]: Prescaler1 dividing rate selection.
PS1SEL[2:0] Dividing Rate

h
A
000 1:2
ec
001 1:4
010 1:8
011 1:16
-T
100 1:32
101 1:64
110 1:128
TW
111 1:256
Table 5 Prescaler1 Dividing Rate
Note: Always set PS1SEL[2:0] at /PS1EN=1, or interrupt may be falsely triggered.
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/PS1EN: Disable/enable Prescaler1.
/PS1EN=1, disable Prescaler1.
/PS1EN=0, enable Prescaler1.
-T
T1CE: Timer1 external clock edge selection.
T1CE=1, Timer1 will decrease one while high-to-low transition occurs on pin EX_CKI.
T1CE=0, Timer1 will decrease one while low-to-high transition occurs on pin EX_CKI.
W
T1CS: Timer1 clock source selection.
T1CS=1, External clock on pin EX_CKI is selected.
T1CS=0, Instruction clock is selected.
T
3.4.4 PWM1DUTY (PWM1 Duty Register)
h
A
PWM1DUTY S 0x3 PWM1DUTY[7:0]
ec
R/W Property
Initial Value
W
XXXXXXXX
-T
This register is write-only. After Timer1 is enabled and start down-count, PWM1 output will keep at inactive
state. While Timer1 value is equal to PWM1DUTY, PWM1 output will become active state until underflow is
occurred.
W
Moreover, the reload value of Timer1 stored on register TMR1 is used to define the PWM1 frame rate and
register PWM1DUTY is used to define the duty cycle of PWM1.
3.4.5 PS1CV (Prescaler1 Counter Value Register)

T
PS1CV S 0x4 PS1CV[7:0]
h
A
R/W Property R
ec
While reading PS1CV, it will get current value of Prescaler1 counter.

-T
3.4.6 BZ1CR (Buzzer1 Control Register)

BZ1CR S 0x5 BZ1EN - - - BZ1FSEL[3:0]
TW
R/W Property W - - - W
Initial Value 0 X X X 1 1 1 1
BZ1FSEL[3:0]: Frequency selection of BZ1 output.
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BZ1 Frequency Selection
BZ1FSEL[3:0]
Clock Source Dividing Rate
-T
0000 1:2
0001 1:4
0010 1:8
0011 1:16
0100
0101
0110
T W
Prescaler1 output
1:32
1:64
1:128
0111 1:256
1000 Timer1 bit 0
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A
1001 Timer1 bit 1
1010 Timer1 bit 2
1011
1100
1101
ec Timer1 output
Timer1 bit 3
Timer1 bit 4
Timer1 bit 5
-T
1110 Timer1 bit 6
1111 Timer1 bit 7
Table 6 Buzzer1 Output Frequency Selection

W
BZ1EN: Enable/Disable BZ1 output.

BZ1EN=1, enable Buzzer1.
BZ1EN=0, disable Buzzer1.
T
3.4.7 IRCR (IR Control Register)

h
A
IRCR S 0x6 IROSC358M - - - - IRCSEL IRF57K IREN

ec
R/W Property W - - - - W W W
Initial Value 0 X X X X 0 0 0
-T
IREN: Enable/Disable IR carrier output.

IREN=1, enable IR carrier output.
IREN=0, disable IR carrier output.
TW
IRF57K: Selection of IR carrier frequency.

IRF57K=1, IR carrier frequency is 57KHz.
IRF57K=0, IR carrier frequency is 38KHz.
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IRCSEL: Polarity selection of IR carrier.
IRCSEL=0, IR carrier will be generated when I/O pin data is 1.
IRCSEL=1, IR carrier will be generated when I/O pin data is 0.
-T
IROSC358M: When external crystal is used, this bit is determined according to what kind of crystal is used.
This bit is ignored if internal high frequency oscillation is used.
IROSC358M=1, crystal frequency is 3.58MHz.
Note:
W
IROSC358M=0, crystal frequency is 455KHz.
1. Only high oscillation (FHOSC) (See section 3.11) can be used as IR clock source.
T
2. Division ratio for different oscillation type.
OSC. Type 57KHz 38KHz Conditions
h
A
HIRC mode (the input to IR module is set to 4MHz no matter

High IRC(4MHz) 64 96
what system clock is)
Xtal 3.58MHz
Xtal 455KHz
ec 64
8
Table 7
96
12
Xtal mode & IROSC358M=1
Xtal mode & IROSC358M=0
Division ratio for different oscillation type

-T
3.4.8 TBHP (Table Access High Byte Address Pointer Register)
W
TBHP S 0x7 - - - - - TBHP2 TBHP1 TBHP0

R/W Property - - - - - R/W R/W R/W
Initial Value X X X X X X X X
T
When instruction CALLA, GOTOA or TABLEA is executed, the target address is constituted by TBHP[2:0]
and ACC. ACC is the Low Byte of PC[9:0] and TBHP[1:0] is the high byte of PC[9:0]. TBHP[2] is general
h
A
register for AT8A53D.

ec
3.4.9 TBHD (Table Access High Byte Data Register)

TBHD S 0x8 - - TBHD5 TBHD4 TBHD3 TBHD2 TBHD1 TBHD0
-T
R/W Property - - R R R R R R
Initial Value X X X X X X X X
When instruction TABLEA is executed, high byte of content of addressed ROM is loaded into TBHD[5:0]
TW
register. The Low Byte of content of addressed ROM is loaded to ACC.
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3.4.10 OSCCR (Oscillation Control Register)
OSCCR S 0xF - - - - OPMD[1:0] STPHOSC SELHOSC
-T
R/W Property - - - - R/W R/W R/W
Initial Value X X X X 00 0 1
SELHOSC: Selection of system oscillation (FOSC).

W
SELHOSC=1, FOSC is high-frequency oscillation (FHOSC).
SELHOSC=0, FOSC is low-frequency oscillation (FLOSC).
STPHOSC: Disable/enable high-frequency oscillation (FHOSC).

T
STPHOSC=1, FHOSC will stop oscillation and be disabled.
STPHOSC=0, FHOSC keep oscillation.
h
A
OPMD[1:0]: Selection of operating mode.
OPMD[1:0]
00
01
ec Operating Mode
Normal mode
Halt mode
-T
10 Standby mode
11 reserved
Table 8 Selection of Operating Mode by OPMD[1:0]

W
Note: STPHOSC cannot be changed with SELHOSC or OPMD at the same time. STPHOSC cannot be
changed with OPMD at the same time during SELHOSC=1.
T
3.5 I/O Port

AT8A53D provides 12 I/O pins which are PA[3:0] and PB[7:0]. User can read/write these I/O pins through
h
A
registers PORTA and PORTB respectively. Each I/O pin has a corresponding register bit to define it is input pin
or output pin. Register IOSTA[3:0] define the input/output direction of PA[3:0]. Register IOSTB[7:0] define the
ec
input/output direction of PB[7:0].
When an I/O pin is configured as input pin, it may have Pull-High resistor or Pull-Low resistor which is enabled
or disabled through registers. Register ABPLCON[3:0] are used to enable or disable Pull-Low resistor of
-T
PA[3:0]. Register BPHCON[7:0] are used to enable or disable Pull-High resistor of PB[7:4] and PB[2:0]. Register
ABPLCON[7:4] are used to enable or disable Pull-Low resistor of PB[3:0].
When an I/O pin is configured as output pin, there is a corresponding and individual register to select as
TW
Open-Drain output pin. Register BODCON[7:0] determine PB[7:0] is Open-Drain or not. (Except PB[3], which is
always in open-drain mode when configured as output port.)
The summary of Pad I/O feature is listed in the table below.
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Feature PA[3:0] PB[2:0] PB[3] PB[7:4]
Pull-High Resistor X V X V
Input
Pull-Low Resistor V V V X
-T
Output Open-Drain X V always V
Table 9 Summary of Pad I/O Feature
W
The level change on each I/O pin of PB may generate interrupt request. Register BWUCON[7:0] will select
which I/O pin of PB may generate this interrupt. As long as any pin of PB is selected by corresponding bit of
BWUCON, the register bit PBIF (INTF[1]) will set to 1 if there is a level change occurred on any selected pin. An
interrupt request will occur and interrupt service routine will be executed if register bit PBIE (INTE[1]) and GIE
T
(PCON1[7]) are both set to 1.
h
There is one external interrupt provided by AT8A53D. When register bit EIS (PCON[6]) is set to 1, PB0 is used
A
as input pin for external interrupt.
ec
Note: When PB0 is both set as level change operation and external interrupt, the external interrupt will
have higher priority, and the PB0 level change operation will be disabled. But PB7~PB1 level
change function are not affected.
-T
AT8A53D can provide IR carrier generation. IR carrier generation is enabled by register bit IREN (IRCR[0]) and
carrier will be present on a PB1 pin. Configuration word IR Current determines sink current value of IR carrier.
PB3 can be used as external reset input determined by a configuration word. When an active-low signal is
W
applied to PB3, it will cause AT8A53D to enter reset process.
When external crystal (E_HXT, E_XT or E_LXT) is adopted for high oscillation or low oscillation according to
setting of configuration words, PB5 will be used as crystal input pin (Xin) and PB4 will be used as crystal output
T
pin (Xout).
When I_HRC or I_LRC mode is selected as system oscillation and E_HXT, E_XT or E_LXT is not adopted,
h
A
instruction clock is observable on PB4 if a configuration word is enabled.

ec
Moreover, PB2 can be timer 0 external clock source EX_CKI if T0MD T0CS=1 and LCK_TM0=0. PB2 can be
timer 1 external clock source if T1CS=1.
Moreover, PB6 can be PWM output and PB7 can be Buzzer output. If T1CR1[7] PWM1OEN=1, PB6 can be
-T
PWM output. And if BZ1CR[7] BZ1EN=1, PB7 can be Buzzer output.

TW
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3.5.1 Block Diagram of IO Pins
IO_SEL: set pad input or output
-T
WRITE_EN: write data to pad.
READ_EN: read pad.
PULLDOWN_EN: enable Pull-Low.
RD_TYPE : select read pin or read latch.

T W
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-T
W
Figure 5 Block Diagram of PA[3:0]

T
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-T
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OD_EN: open-drain enable.
IO_SEL: set pad input or output.
-T
READ_EN: read pad to DATA_BUS.
WUBx: wake-up enable.

W
PULLUP_ENB: enable pull high.
INTEDGE: external interrupt edge select

T
SET_PBIF: set port change interrupt flag.
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RD_TYPE: select read pin or read latch.
A
ec
-T
T W
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-T
Figure 6 Block Diagram of PB0

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IREN: Enable IR.
-T
W

T
RD_TYPE: read pin or read latch.
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ec
-T
T W
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A
ec

-T
TW
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-T

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EX_CKI: Timer0 EX CLOCK IN.
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-T
T W
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-T

TW
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PB3_RSTPAD: PB3 is set as Reset Pin by configuration word.
-T

W

T
RSTB_IN: Reset signal with Schmitt trigger.
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-T
T W
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-T

TW
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XTL_EN: PB4, PB5 is set as Xtal Pin by configuration word.
-T

W
RD_TYPE: read pin or read latch

T
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-T
T W
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Figure 10 Block Diagram of PB5, PB4

-T
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PWM_OR_BZ_EN: PWM or Buzzer enable.
-T
PWM_OR_BZ_DATA: PWM or Buzzer data.
W

T
h
A
ec
-T
T W
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A
ec
Figure 11 Block Diagram of PB7, PB6

-T
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3.6 Timer0
Timer0 is an 8-bit up-count timer and its operation is enabled by register bit T0EN (PCON1[0]). Writing to Timer0
-T
will set its initial value. Reading from Timer0 will show its current count value.
The clock source to Timer0 can be from instruction clock, external pin EX_CKI or low speed clock Low Oscillator
Frequency according to register bit T0CS and LCK_TM0 (T0MD[5] and T0MD[7]). When T0CS is 0, instruction
clock is selected as Timer0 clock source. When T0CS is 1 and LCK_TM0 is 0, EX_CKI is selected as Timer0
W
clock source. When T0CS is 1 and LCK_TM0 is 1 (and Timer0 source must set to 1), Low Oscillator Frequency
(I_LRC or E_LXT, depends on configuration word) output is selected. Summarized table is shown below. (Also
check Figure. 12)
T
Low Oscillator
Timer0 clock source T0CS LCKTM0 Timer0 source
Frequency
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Instruction clock 0 X X X
0 X
EX_CKI
E_LXT
ec 1
1
X
1
0
1
X
1
-T
I_LRC 1 1 1 0
Table 10 Summary of Timer0 clock source control
Moreover the active edge of EX_CKI or Low Oscillator Frequency to increase Timer0 can be selected by
W
register bit T0CE (T0MD[4]). When T0CE is 1, high-to-low transition on EX_CKI or Low Oscillator Frequency will
increase Timer0. When T0CE is 0, low-to-high transition on EX_CKI or Low Oscillator Frequency will increase
Timer0. When using Low Oscillator Frequency as timer0 clock source, it is suggested to use prescaler0 (see
T
below descriptions) and the ratio set to more than 4, or missing count may happen.
Before Timer0 clock source is supplied to Timer0, it can be divided by Prescaler0 if register bit PS0WDT
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A
(T0MD[3]) is clear to 0. When writing 0 to PS0WDT by instruction, Prescaler0 is assigned to Timer0 and
Prescaler0 will be clear after this instruction is executed. The dividing rate of Prescaler0 is determined by
ec
register bits PS0SEL[2:0] which is from 1:2 to 1:256.
When Timer0 is overflow, the register bit T0IF (INTF[0]) will be set to 1 to indicate Timer0 overflow event is
occurred. If register bit T0IE (INTE[0]) and GIE are both set to 1, interrupt request will occur and interrupt service
-T
routine will be executed. T0IF will not be clear until firmware writes 0 to T0IF.
The block diagram of Timer0 and WDT is shown in the figure below.
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-T
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Figure 12 Block Diagram of Timer0 and WDT
3.7 Timer1/PWM1/Buzzer1
ec
Timer1 is an 8-bit down-count timer with Prescaler1 whose dividing rate is programmable. The output of Timer1
-T
can be used to generate PWM1 output and Buzzer1 output. A write to the Timer1 will both write to a timer1
reload register (T1rld) and timer1 counter. A read to the timer1 will show the content of the Timer1 current count
value.
W
The block diagram of Timer1 is shown in the figure below.

T
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-T
Figure 13 Block Diagram of Timer1
The operation of Timer1 can be enabled or disabled by register bit T1EN (T1CR1[0]). After Timer1 is enabled,
TW
its clock source can be instruction clock or pin EX_CKI which is determined by register bit T1CS (T1CR2[5]).
When T1CS is 1, EX_CKI is selected as clock source. When T1CS is 0, instruction clock is selected as clock
source. When EX_CKI is selected, the active edge to decrease Timer1 is determined by register bit T1CE
(T1CR2[4]). When T1CE is 1, high-to-low transition on EX_CKI will decrease Timer1. When T1CE is 0,
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low-to-high transition on EX_CKI will decrease Timer1. The selected clock source can be divided further by
Prescaler1 before it is applied to Timer1. Prescaler1 is enabled by writing 0 to register bit /PS1EN (T1CR2[3])
and the dividing rate is from 1:2 to 1:256 determined by register bits PS1SEL[2:0] (T1CR2[2:0]). Current value of
-T
Prescaler1 can be obtained by reading register PS1CV.
Timer1 provide two kinds of operating mode: one is One-Shot mode and the other is Non-Stop mode. When
register bit T1OS (T1CR1[2]) is 1, One-Shot mode is selected. Timer1 will count down once from initial value
W
stored on register TMR1 to 0x00, i.e. underflow is occurred. When register bit T1OS (T1CR1[2]) is 0, Non-Stop
mode is selected. When underflow is occurred, there are two selections to start next down-count which is
determined by register bit T1RL (T1CR1[1]). When T1RL is 1, the initial value stored on register TMR1 will be
T
restored and start next down-count from this initial value. When T1RL is 0, Timer1 will start next down-count
from 0xFF.
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A
When Timer1 is underflow, the register bit T1IF (INTF[3]) will be set to 1 to indicate Timer1 underflow event is
occurred. If register bit T1IE (INTE[3]) and GIE are both set to 1, interrupt request will occur and interrupt service
ec
routine will be executed. T1IF will not be clear until firmware writes 0 to T1IF.
The timing chart of Timer1 is shown in the following figure.

-T
T W
Figure 14 Timer1 Timing Chart

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A
The PWM1 output can be available on I/O pin PB6 when register bit PWM1OEN (T1CR1[7]) is set to 1.
Moreover, PB6 will become output pin automatically. The active state of PWM1 output is determined by register
ec
bit PWM1OAL (T1CR1[6]). When PWM1OAL is 1, PWM1 output is active low. When PWM1OAL is 0, PWM1
output is active high. Moreover, the duty cycle and frame rate of PWM1 are both programmable. The duty cycle
is determined by register PWM1DUTY. When PWM1DUTY is 0, PWM1 output will be never active. When
-T
PWM1DUTY is 0xFF, PWM1 output will be active for 255 Timer1 input clocks. The frame rate is determined by
TMR1 initial value. Therefore, PWM1DUTY value must be less than or equal to TMR1. The block diagram of
PWM1 is illustrated in the following figure.
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-T
T W
Figure 15 PWM1 Block Diagram
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The Buzzer1 output (BZ1) can be available on I/O pin PB7 when register bit BZ1EN (BZ1CR1[7]) is set to 1.
Moreover, PB7 will become output pin automatically. The frequency of BZ1 can be derived from Timer1 output
ec
or Prescaler1 output and dividing rate is determined by register bits BZ1FSEL[3:0] (BZ1CR[3:0]). When
BZ1FSEL[3] is 0, Prescaler1 output is selected to generate BZ1 output. When BZ1FSEL[3] is 1, Timer1 output is
selected to generate BZ1 output. The dividing rate can be from 1:2 to 1:256 in order to generate all kinds of
-T
frequency. The block diagram of Buzzer1 is illustrated in the following figure.
T W
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A
Figure 16 Buzzer1 Block Diagram

ec
3.8 IR Carrier
The IR carrier will be generated after register bit IREN (IRCR[0]) is set to 1. Moreover, PB1 will become output
-T
pin automatically. When IREN is clear to 0, PB1 will become general I/O pin as it was configured.
The IR carrier frequency is selectable by register bit IRF57K (IRCR[1]). When IRF57K is 1, IR carrier frequency
is 57KHz. When IRF57K is 0, IR carrier frequency is 38KHz. Because IR carrier frequency is derived from high
TW
frequency system oscillation FHOSC, it is necessary to specify what frequency is used as system oscillation when
external crystal is used. Register bit IROSC358M (IRCR[7]) is used to provide AT8A53D this information. When
IROSC358M is 1, frequency of external crystal is 3.58MHz and when IROSC358M is 0, frequency of external
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crystal is 455KHz. When internal high frequency oscillation is adopted, this register will be ignored, and it will
provide 4MHz clock to IR module.
-T
The active state (polarity) of IR carrier is selectable according to PB1 output data. When register bit IRCSEL
(IRCR[2]) is 1, IR carrier will be present on pin PB1 when its output data is 0. When register bit IRCSEL
(IRCR[2]) is 0, IR carrier will be present on pin PB1 when its output data is 1. The polarity of IR carrier is shown
in the following figure.
T W
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Figure 17 Polarity of IR Carrier vs. Output Data
3.9 ec
Watch-Dog Timer (WDT)
There is an on-chip free-running oscillator in AT8A53D which is used by WDT. As this oscillator is independent
of other oscillation circuits, WDT may still keep working during Standby mode and Halt mode.
-T
WDT can be enabled or disabled by a configuration word. When WDT is enabled by configuration word, its
operation still can be controlled by register bit WDTEN (PCON[7]) during program execution. Moreover, the
mechanism after WDT time-out can reset AT8A53D or issue an interrupt request which is determined by
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another configuration word. At the same time, register bit /TO (STATUS[4]) will be clear to 0 after WDT time-out.
The baseline of WDT time-out period can be 3.5 ms, 15 ms, 60 ms or 250 ms which is determined by two
configuration words. The time-out period can be lengthened if Prescaler0 is assigned to WDT. Prescaler0 will be
T
assigned to WDT by writing 1 to register bit PS0WDT. The dividing rate of Prescaler0 for WDT is determined by
register bits PS0SEL[2:0] and depends on WDT time-out mechanism. The dividing rate is from 1:1 to 1:128 if
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WDT time-out will reset AT8A53D and dividing rate is from 1:2 to 1:256 if WDT time-out will interrupt AT8A53D.
When Prescaler0 is assigned to WDT, the execution of instruction CLRWDT will clear WDT, Prescaler0 and set
ec
/TO flag to 1.
If user selects interrupt for WDT time-out mechanism, register bit WDTIF (INTF[6]) will set to 1 after WDT is
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expired. It may generate an interrupt request if register bit WDTIE (INTE[6]) and GIE both set to 1. WDTIF will
not be clear until firmware writes 0 to WDTIF.
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3.10 Interrupt
AT8A53D provides two kinds of interrupt: one is software interrupt and the other is hardware interrupt. Software
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interrupt is caused by execution of instruction INT. There are 5 hardware interrupts:
 Timer0 overflow interrupt.
 Timer1 underflow interrupt.
 WDT timeout interrupt.
 External interrupt.
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 PB input change interrupt.
GIE is global interrupt enable flag. It has to be 1 to enable hardware interrupt functions. GIE can be set by ENI
T
instruction and clear to 0 by DISI instruction.
After instruction INT is executed, no matter GIE is set or clear, the next instruction will be fetched from address
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A
0x001. At the same time, GIE will be clear to 0 by AT8A53D automatically. This will prevent nested interrupt
from happening. The last instruction of interrupt service routine of software interrupt has to be RETIE. Execution
ec
of this instruction will set GIE to 1 and return to original execution sequence.
While any of hardware interrupts is occurred, the corresponding bit of Interrupt Flag Register INTF will be set to
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1. This bit will not be clear until firmware writes 0 to this bit. Therefore user can obtain information of which event
causes hardware interrupt by polling register INTF. Note that only when the corresponding bit of Interrupt
Enable register INTE is set to 1, will the corresponding interrupt flag be read. And if the corresponding bit of
Interrupt Enable Register INTE is set to 1 and GIE is also 1, hardware interrupt will occur and next instruction
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will be fetched from 0x008. At the same time, the register bit GIE will be clear by AT8A53D automatically. If user
wants to implement nested interrupt, instruction ENI can be used as the first instruction of interrupt service
routine which will set GIE to 1 again and allow other interrupt events to interrupt AT8A53D again. Instruction
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RETIE has to be the last instruction of interrupt service routine which will set GIE to 1 and return to original
execution sequence.
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It should be noted that ENI instruction cannot be placed right before RETIE instruction because ENI instruction
in interrupt service routine will trigger nested interrupt, but RETIE will clear internal interrupt processing after
ec
jump out of ISR, so it is possible for interrupt flag to be falsely cleared.
3.10.1 Timer0 Overflow Interrupt

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Timer0 overflow (from 0x00 to 0xFF) will set register bit T0IF. This interrupt request will be serviced if T0IE
and GIE are set to 1.
TW
3.10.2 Timer1 Underflow Interrupt

Timer1 underflow (from 0xFF to 0x00) will set register bit T1IF. This interrupt request will be serviced if T1IE
and GIE are set to 1.
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3.10.3 WDT Timeout Interrupt
When WDT is timeout and the configuration word selects WDT timeout will generate interrupt request, it will
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set register bit WDTIF. This interrupt request will be serviced if WDTIE and GIE are set to 1.
3.10.4 PB Input Change Interrupt

When PBx, 0 ≤ x ≤ 7, is configured as input pin and corresponding register bit WUPBx is set to 1, a level
W
change on these selected I/O pin(s) will set register bit PBIF. This interrupt request will be serviced if PBIE
and GIE are set to 1. Note when PB0 is both set as level change interrupt and external interrupt, the external
interrupt enable EIS=1 will disable PB0 level change operation.
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3.10.5 External Interrupt
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According to the configuration of EIS=1 and INTEDG, the selected active edge on I/O pin PB0 will set
register bit INTIF and this interrupt request will be served if INTIE and GIE are set to 1.
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3.11 Oscillation Configuration
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Because AT8A53D is a dual-clock IC, there are high oscillation (FHOSC) and low oscillation (FLOSC) that can be
selected as system oscillation (FOSC). The oscillators which could be used as FHOSC are internal high RC oscillator
(I_HRC), external high crystal oscillator (E_HXT) and external crystal oscillator (E_XT). The oscillators which could
be used as FLOSC are internal low RC oscillator (I_LRC) and external low crystal oscillator (E_LXT).
T W
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-T
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Figure 18 Oscillation Configuration of AT8A53D
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There are two configuration words to determine which oscillator will be used as FHOSC. When I_HRC is selected
as FHOSC, I_HRC output frequency is determined by three configuration words and it can be 1M, 2M, 4M, 8M,
16M or 20MHz. Moreover, external crystal oscillator pads PB4 and PB5 can be used as I/O pins. On the other
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hand, PB4 can be the output pin of instruction clock according to a configuration word’s setting. If FHOSC required
external crystal whose frequency ranges from 8MHz to 20MHz, E_HXT is recommended. If FHOSC required
external crystal whose frequency ranges from 455KHz to 6MHz, E_XT is recommended. When E_HXT or E_XT
W
is adopted, PB4/PB5 cannot be used as I/O pins. They must be used as crystal output pin and input pin. PB4 is
crystal output pin (Xout) and PB5 is crystal input pin (Xin).
There is one configuration word to determine which oscillator will be used as FLOSC. When I_LRC is selected, its
T
frequency is centered on 32768Hz. If FLOSC required external crystal, E_LXT is selected and only 32768Hz
crystal is allowed. When E_LXT is adopted, PB4/PB5 cannot be used as I/O pins. They must be used as crystal
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output pin and input pin. PB4 is crystal output pin (Xout) and PB5 is crystal input pin (Xin). The dual-clock
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combinations of FHOSC and FLOSC are listed below:
No.
1
ec
FHOSC
I_HRC
FLOSC
I_LRC
-T
2 E_HXT or E_XT I_LRC
3 I_HRC E_LXT
Table 11 Dual-clock combinations

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When E_HXT, E_XT or E_LXT is used as one of oscillations, the crystal or resonator is connected to Xin and
Xout to provide oscillation. Moreover, a resistor and two capacitors are recommended to connect as following
figure in order to provide reliable oscillation, refer to the specification of crystal or resonator to adopt appropriate
T
C1 or C2 value. The recommended value of C1 and C2 are listed in the table below.
Oscillation Mode Crystal Frequency(Hz) C1, C2 (pF)

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16M 5 ~ 10
E_HXT 10M 5 ~ 30
ec
8M 5 ~ 20
4M 5 ~ 30
E_XT 1M 5 ~ 30
-T
455K 10 ~ 100
E_LXT 32768 10 ~ 30
Table 12 Recommended C1 and C2 Value for Different Kinds of Crystal Oscillation

TW
For 20MHZ resonator in 2 clock CPU cycle mode, An 18pF C2 capacitor is a must.
Moreover, for precision 32.768k crystal, it is recommended to set C1=C2=20pF capacitor.
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Figure 19 Connection for External Crystal Oscillation
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Either FHOSC or FLOSC can be selected as system oscillation FOSC according to the value of register bit SELHOSC
(OSCCR[0]). When SELHOSC is 1, FHOSC is selected as FOSC. When SELHOSC is 0, FLOSC is selected as FOSC.
ec
Once FOSC is determined, the instruction clock FINST can be FOSC/2 or FOSC/4 according to value of a
configuration word.
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3.12 Operating Mode
AT8A53D provides four kinds of operating mode to tailor all kinds of application and save power consumptions.
These operating modes are Normal mode, Slow mode, Standby mode and Halt mode. Normal mode is
W
designated for high-speed operating mode. Slow mode is designated for low-speed mode in order to save
power consumption. At Standby mode, AT8A53D will stop almost all operations except Timer0/Timer1/WDT in
order to wake-up periodically. At Halt mode, AT8A53D will sleep until external event or WDT trigger IC to
T
wake-up.
The block diagram of four operating modes is described in the following figure.
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Figure 20 Four Operating Modes

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3.12.1 Normal Mode
After any Reset Event is occurred and Reset Process is completed, AT8A53D will begin to execute program
under Normal mode or Slow mode. Which mode is selected after Reset Process is determined by the Startup
-T
Clock configuration word. If Startup Clock=fast, AT8A53D will enter Normal mode, if Startup Clock=Slow,
AT8A53D will enter Slow mode. At Normal mode, FHOSC is selected as system oscillation in order to provide
highest performance and its power consumption will be the largest among four operating modes. After power
W
on or any reset trigger is released, AT8A53D will enter Normal mode after reset process is completed.
 Instruction execution is based on FHOSC and all peripheral modules may be active according to
corresponding module enable bit.
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 The FLOSC is still active and running.
 IC can switch to Slow mode by writing 0 to register bit SELHOSC (OSCCR[0]).
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 IC can switch to Standby mode or Halt mode by programming register bits OPMD[1:0] (OSCCR[3:2]).
ec
 For real time clock applications, the AT8A53D can run in normal mode, at the same time the
low-frequency clock Low Oscillator Frequency connects to timer0 clock. This is made possible by setting
LCKTM0 to 1 and corresponding configuration word Timer0 source setting to 1.
-T
3.12.2 Slow Mode
AT8A53D will enter Slow mode by writing 0 to register bit SELHOSC. At Slow mode, FLOSC is selected as
system oscillation in order to save power consumption but still keep IC running. However, FHOSC will not be
W
disabled automatically by AT8A53D. Therefore user can write 0 to register bit STPHOSC (OSCCR[1]) in slow
mode to reduce power consumption further. But it is noted that it is forbidden to enter slow mode and stop
FHOSC at the same time, one must enter slow mode first, then disable FHOSC, or the program may hang on.
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 Instruction execution is based on FLOSC and all peripheral modules may be active according to
corresponding module enable bit.
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 FHOSC can be disabled by writing 1 to register bit STPHOSC.
 IC can switch to Standby mode or Halt mode by programming register bits OPMD[1:0].
ec
 IC can switch to Normal mode by writing 1 to SELHOSC.
3.12.3 Standby Mode

-T
AT8A53D will enter Standby mode by writing 10b to register bits OPMD[1:0]. At Standby mode, however,
FHOSC will not be disabled automatically by AT8A53D and user has to enter slow mode and write 1 to register
bit STPHOSC in order to stop FHOSC oscillation. Most of AT8A53D peripheral modules are disabled but Timer
TW
can be still active if register bit T0EN/T1EN is set to 1. Therefore AT8A53D can wake-up after Timer0/Timer1
is expired. The expiration period is determined by the register TMR0/TMR1, FINST and other configurations
for Timer0/Timer1.
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 Instruction execution is stop and some peripheral modules may be active according to corresponding
module enable bit.
 FHOSC can be disabled by writing 1 to register bit STPHOSC.
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 The FLOSC is still active and running.
 IC can wake-up from Standby mode if any of (a) Timer0/Timer1 (overflow/underflow) interrupt, (b) WDT
timeout interrupt, (c) PB input change interrupt or (d) INT external interrupt is happened.
mode if SELHOSC=0.
W
 After wake-up from Standby mode, IC will return to Normal mode if SELHOSC=1, IC will return to Slow
 It is not recommended to change oscillator mode (normal to slow / slow to normal) and enter standby
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mode at the same time.
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3.12.4 Halt Mode
ec
AT8A53D will enter Halt mode by executing instruction SLEEP or writing 01b to register bits OPMD[1:0].
After entering Halt mode, register bit /PD (STATUS[3]) will be clear to 0, register bit /TO (STATUS[4]) will be
set to 1 and WDT will be clear but keep running.
-T
At Halt mode, all of peripheral modules are disabled, instruction execution is stop and AT8A53D can only
wake-up by some specific events. Therefore, Halt mode is the most power saving mode provided by
AT8A53D.
W
 Instruction execution is stop and all peripheral modules are disabled.
 FHOSC and FLOSC are both disabled automatically.
 IC can wake-up from Halt mode if any of (a) WDT timeout interrupt, (b) PB input change interrupt or (c)
INT or external interrupt is happened.
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 After wake-up from Halt mode, IC will return to Normal mode if SELHOSC=1, IC will return to Slow mode
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if SELHOSC=0.
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Note: Users can change STPHOSC and enter Halt mode in the same instruction.
ec
 It is not recommended to change oscillator mode (normal to slow or slow to normal) and enter halt mode
at the same time.
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3.12.5 Wake-up Stable Time

The wake-up stable time of Halt mode is determined by Configuration word: High Oscillator Frequency or
Low Oscillator Frequency. If one of E_HXT, E_XT and E_LXT is selected, the wake-up period would be
TW
512*FOSC. And if no XT mode are selected, 16*Fosc would be set as wake-up period. On the other hand,
there is no need of wake-up stable time for Standby mode because either FHOSC or FLOSC is still running at
Standby mode.
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Before AT8A53D enter Standby mode or Halt mode, user may execute instruction ENI. At this condition,
AT8A53D will branch to address 0x008 in order to execute interrupt service routine after wake-up. If
instruction DISI is executed or 0 is written to register bit GIE before entering Standby mode or Halt mode, the
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next instruction will be executed after wake-up.
3.12.6 Summary of Operating Mode
FHOSC
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The summary of four operating modes is described in the following table.
Mode Normal
Enabled
Slow
STPHOSC
Standby
STPHOSC
Halt
Disabled
FLOSC Enabled Enabled Enabled Disabled
Instruction Execution Executing Executing Stop Stop
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Timer0/1 T0EN / T1EN T0EN / T1EN T0EN / T1EN Disabled
WDT ec
Other Modules
Option and
WDTEN
Module enable bit
Option and
WDTEN
Module enable bit
Option and
WDTEN
Module enable bit
- Timer0 overflow
Option and
WDTEN
All disabled
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- WDT timeout
- Timer1 underflow
Wake-up Source - - - WDT timeout - PB input change
- PB input change - INT
- INT
W
Table 13 Summary of Operating Modes
3.13 Reset Process

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AT8A53D will enter Reset State and start Reset Process when one of following Reset Event is occurred:
 Power-On Reset (POR) is occurred when VDD rising is detected.
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 Low-Voltage Reset (LVR) is occurred when operating VDD is below pre-defined voltage.
 Pin RSTb is low state.
ec
 WDT timeout reset.
Moreover, value of all registers will be initialized to their initial value or unchanged if its initial value is unknown.
The status bits /TO and /PD could be initialized according to which event causes reset. The /TO and /PD value
-T
and its associated event is summarized in the table below.
Event /TO /PD

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POR, LVR 1 1
RSTb reset from non-Halt mode unchanged unchanged
RSTb reset from Halt mode 1 1
WDT reset from non-Halt mode 0 1
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Event /TO /PD
WDT reset from Halt mode 0 0
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SLEEP executed 1 0
CLRWDT executed 1 1
Table 14 Summary of /TO & /PD Value and its Associated Event
W
After Reset Event is released, AT8A53D will start Reset Process. It will wait certain amount of period for
oscillation stable no matter what kind of oscillator is adopted. This period is called power-up reset time and is
determined by two-bit configuration words which can be 140us, 4.5ms,18ms, 72ms or 288ms. After oscillator is
T
stable, AT8A53D will wait further 16 clock cycles of FOSC (oscillator start-up time, OST) and Reset Process is
complete.
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Figure 21 Block Diagram of On-Chip Reset Circuit

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For slow VDD power-up, it is recommended to use RSTb reset, as the following figure.
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 It is recommended the R value should be not greater than 40kΩ.
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 The R1 value=100Ω to 1kΩ will prevent high current, ESD or Electrical overstress flowing into reset pin.
ec
 The diode helps discharge quickly when power down.

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AT8A53D
Figure 22 Block Diagram of Reset Application
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4. Instruction Set
AT8A53D provides 55 powerful instructions for all kinds of applications.
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OP OP
Inst. Operation Cyc. Flag Inst. Operation Cyc. Flag
1 2 1 2
Arithmetic Instructions Arithmetic Instructions
ANDAR
IORAR
XORAR
ANDIA
R
i
W
d dest = ACC & R
d dest = ACC | R
d dest = ACC ⊕ R
ACC = ACC & i

T 1
1
Z
Z
ADDAR
SUBAR
ADCAR
SBCAR
R d dest = R + ACC
R d dest = R + (~ACC)
R d dest = R + ACC + C
R d dest = R + (~ACC) + C
1
1
Z, DC, C
Z, DC, C
Z, DC, C
Z, DC, C
IORIA i ACC = ACC | i 1 Z ADDIA i ACC = i + ACC 1 Z, DC, C
XORIA i ACC = ACC ⊕ i 1 Z SUBIA i ACC = i + (~ACC) 1 Z, DC, C
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RRR R d Rotate right R 1 C ADCIA i ACC = i + ACC + C 1 Z, DC, C
RLR R d Rotate left R 1 C SBCIA i ACC = i + (~ACC) + C 1 Z, DC, C
BSR
BCR
R
R
ec
bit Set bit in R
bit Clear bit in R

1
1
-
-
DAA
CMPAR R
Decimal adjust for ACC
Compare R with ACC

1
1
C
Z, C
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INCR R d Increase R 1 Z CLRA Clear ACC 1 Z
DECR R d Decrease R 1 Z CLRR Clear R 1 Z
COMR R d dest = ~R 1 Z Other Instructions
Conditional Instructions NOP No operation 1 -

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BTRSC R bit Test bit in R, skip if clear 1 or 2 - SLEEP Go into Halt mode 1 /TO, /PD
BTRSS R bit Test bit in R, skip if set 1 or 2 - CLRWDT Clear Watch-Dog Timer 1 /TO, /PD
INCRSZ R d Increase R, skip if 0 1 or 2 - ENI Enable interrupt 1 -

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DECRSZ R d Decrease R, skip if 0 1 or 2 - DISI Disable interrupt 1 -
Data Transfer Instructions INT Software Interrupt 3 -

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MOVAR R Move ACC to R 1 - RET Return from subroutine 2 -
MOVR R d Move R 1 Z Return from interrupt

ec
RETIE 2 -
MOVIA i Move immediate to ACC 1 - and enable interrupt
SWAPR R d Swap halves R 1 - Return, place immediate

RETIA i 2 -
IOST F Load ACC to F-page SFR 1 - in ACC
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IOSTR F Move F-page SFR to ACC 1 - CALLA Call subroutine by ACC 2 -
SFUN S Load ACC to S-page SFR 1 - GOTOA unconditional branch by ACC 2 -
SFUNR S Move S-page SFR to ACC 1 - CALL adr Call subroutine 2 -

TW
T0MD Load ACC to T0MD 1 - GOTO adr unconditional branch 2 -
T0MDR Move T0MD to ACC 1 - LCALL adr Call subroutine 2 -
TABLEA Read ROM 2 - LGOTO adr unconditional branch 2 -
Table 15 Instruction Set
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ACC: Accumulator.
adr: immediate address.
bit: bit address within an 8-bit register R.
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C: Carry/Borrow bit
C=1, carry is occurred for addition instruction or borrow is NOT occurred for subtraction instruction.
C=0, carry is not occurred for addition instruction or borrow IS occurred for subtraction instruction.
d: Destination
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If d is “0”, the result is stored in the ACC.
If d is “1”, the result is stored back in register R.
T
DC: Digital carry flag.
dest: Destination.
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F: F-page SFR, F is 0x5 ~ 0xF.
i: 8-bit immediate data.
PC: Program Counter. ec
PCHBUF: High Byte Buffer of Program Counter.
/PD: Power down flag bit

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/PD=1, after power-up or after instruction CLRWDT is executed.
/PD=0, after instruction SLEEP is executed.

Prescaler: Prescaler0 dividing rate.
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R: R-page SFR, R is 0x00 ~0x3F.

S: S-page SFR, S is 0x0 ~ 0xF.
T0MD: T0MD register.
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TBHP: The high-Byte at target address in ROM.

TBHD: Store the high-Byte data at target address in ROM.
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/TO: Time overflow flag bit

/TO=1, after power-up or after instruction CLRWDT or SLEEP is executed.
ec
/TO=0, WDT timeout is occurred.

WDT: Watchdog Timer Counter.
Z: Zero flag.
-T
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ADCAR Add ACC and R with Carry ADDAR Add ACC and R
Syntax: ADCAR R, d Syntax: ADDAR R, d
Operand: 0  R  63 Operand: 0  R  63
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d = 0, 1. d = 0, 1.
Operation: R + ACC + C  dest Operation: ACC + R  dest
Status affected: Z, DC, C Status affected: Z, DC, C
Description:
Cycle
W
Add the contents of ACC and
register R with Carry. If d is 0, the
result is stored in ACC. If d is 1,
the result is stored back to R.
1
T Description:
Cycle:
Add the contents of ACC and R. If
d is 0, the result is stored in ACC. If
d is 1, the result is stored back to
R.
1
Example: ADCAR R, d Example: ADDAR R, d
before executing instruction: before executing instruction:
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ACC=0x12, R=0x34, C=1, d=1, ACC=0x12, R=0x34,C=1, d=1,
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after executing instruction: after executing instruction:

R=0x47, ACC=0x12, C=0. R=0x46, ACC=0x12, C=0.
ec
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ADCIA Add ACC and Immediate with
Carry ADDIA Add ACC and Immediate
Syntax: ADCIA i Syntax: ADDIA i
Operand: 0  i < 255 Operand: 0  i < 255

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Operation: ACC + i  ACC

Operation: ACC + i + C  ACC
Status affected: Z, DC, C
Status affected: Z, DC, C
Description: Add the contents of ACC with the
Description: Add the contents of ACC and the
8-bit immediate data i. The result
T
8-bit immediate data i with Carry.

is placed in ACC.
The result is placed in ACC.
Cycle: 1
Cycle: 1
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Example: ADDIA i
Example: ADCIA i
before executing instruction:
ACC=0x12, i=0x34, C=1,
ec
ACC=0x12, i=0x34, C=1,

after executing instruction:
ACC=0x46, C=0,.
ACC=0x47, C=0.
-T
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ANDAR AND ACC and R BCR Clear Bit in R
Syntax: ANDAR R, d Syntax: BCR R, bit
Operand: 0  R  63. Operand: 0  R  63
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d = 0, 1. 0  bit  7
Operation: ACC & R  dest Operation: 0  R[bit]
Status affected: Z Status affected: --

Description: Clear the bitth position in R.
Description:
Cycle:
W
The content of ACC is AND’ed
with R. If d is 0, the result is
stored in ACC. If d is 1, the
result is stored back to R.
1
T Cycle:
Example:
1
BCR R,B2
R=0x5A, B2=0x3,
Example: ANDAR R, d after executing instruction:
before executing instruction: R=0x52.
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ACC=0x5A, R=0xAF, d=1.
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R=0x0A, ACC=0x5A, Z=0.
ec
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ANDIA AND Immediate with ACC BSR Set Bit in R
Syntax: ANDIA i Syntax: BSR R, bit
Operand: 0  i < 255 Operand: 0  R  63
W
0  bit  7
Operation: ACC & i  ACC
Operation: 1  R[bit]
Status affected: Z
Status affected: --
Description: The content of ACC register is
T
Description: Set the bitth position in R.

AND’ed with the 8-bit immediate Cycle: 1
data i. The result is placed in ACC. Example: BSR R,B2
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Cycle: 1 before executing instruction:

R=0x5A, B2=0x2,
Example: ANDIA i
ec

R=0x5E.
ACC=0x5A, i=0xAF,
ACC=0x0A, Z=0.
-T
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BTRSC Test Bit in R and Skip if Clear CALL Call Subroutine
Syntax: BTRSC R, bit Syntax: CALL adr
Operand: 0  R  63 Operand: 0  adr < 255
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0  bit  7
Operation: PC + 1  Top of Stack
Operation: Skip next instruction, if R[bit] = 0.
{PCHBUF, adr}  PC
Status affected: -- Status affected: --
Description:
W
If R[bit] = 0, the next instruction
which is already fetched is
discarded and a NOP is executed
instead. Therefore it makes this
instruction a two-cycle instruction.
T Description: The return address (PC + 1) is
pushed onto top of Stack. The 8-bit
immediate address adr is loaded
into PC[7:0] and PCHBUF[1:0] is
loaded into PC[9:8].
Cycle: 1 or 2(skip) Cycle: 2

Example: BTRSC R, B2 Example: CALL SUB
h
A
Instruction1 before executing instruction:
Instruction2 PC=A0. Stack pointer=1
before executing instruction: after executing instruction:
ec
R=0x5A, B2=0x2,
because R[B2]=0, instruction1
will not be executed, the program
PC=address of SUB, Stack[1] =
A0+1, Stack pointer=2.
-T
will start execute instruction from
instruction2.
BTRSS Test Bit in R and Skip if Set CALLA Call Subroutine

W
Syntax: BTRSS R, bit Syntax: CALLA

Operand: 0  R  63 Operand: --
0  bit  7 Operation: PC + 1  Top of Stack
{TBHP, ACC}  PC
T
Operation: Skip next instruction, if R[bit] = 1.

Status affected: --
Status affected: --
h
Description: The return address (PC + 1) is
A
Description: If R[bit] = 1,, the next instruction

which is already fetched is pushed onto top of Stack. The
discarded and a NOP is executed contents of TBHP[1:0] is loaded
ec
instead. Therefore it makes this into PC[9:8] and ACC is loaded

instruction a two-cycle instruction. into PC[7:0].
Cycle: 1 or 2(skip) Cycle: 2

Example: CALLA
-T
Example: BTRSS R, B2
Instruction2 before executing instruction:
Instruction3 TBHP=0x02, ACC=0x34.
before executing instruction: PC=A0. Stack pointer=1.
R=0x5A, B2=0x3, after executing instruction:
PC=0x234, Stack[1]=A0+1,
TW

Stack pointer=2
because R[B2]=1, instruction2
will not be executed, the program
will start execute instruction from
instruction3.
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CLRA Clear ACC CLRWDT Clear Watch-Dog Timer
Syntax: CLRA Syntax: CLRWDT
Operand: -- Operand: --
-T
Operation: 00h  ACC Operation: 00h  WDT,
1 Z 00h  WDT prescaler
1  /TO
Status affected: Z
1  /PD
Description: ACC is clear and Z is set to 1.
Cycle:
Example:
1
CLRA
W
ACC=0x55, Z=0.
T Status affected:
Description:
/TO, /PD
Executing CLRWDT will reset
WDT, Prescaler0 if it is assigned
to WDT. Moreover, status bits /TO
and /PD will be set to 1.
after executing instruction: Cycle: 1
ACC=0x00, Z=1.
Example: CLRWDT
h
A
/TO=0
ec /TO=1
-T
CLRR Clear R COMR Complement R
Syntax: CLRR R Syntax: COMR R, d
0  R  63
W
Operand: 0  R  63 Operand:
d = 0, 1.
Operation: 00h  R
1Z Operation: ~R  dest
Status affected: Z Status affected: Z

T
Description: The content of R is clear and Z is Description: The content of R is

set to 1. complemented. If d is 0, the result
is stored in ACC. If d is 1, the
h
Cycle: 1 result is stored back to R.
A
Example: CLRR R Cycle: 1

ec
Example: COMR , d
R=0x55, Z=0.
R=0xA6, d=1, Z=0.
R=0x00, Z=1.
-T
R=0x59, Z=0.
TW
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CMPAR Compare ACC and R DECR Decrease R
Syntax: CMPAR R Syntax: DECR R, d
-T
Operation: R - ACC  (No restore) d = 0, 1.
Status affected: Z, C Operation: R - 1  dest
Description: Compare ACC and R by Status affected: Z

subtracting ACC from R with 2’s Description: Decrease R. If d is 0, the result is
Cycle: 1
T W
complement representation. The
content of ACC and R is not
changed.
Cycle:
Example:
stored in ACC. If d is 1, the result is
stored back to R.
1
DECR R, d
Example: CMPAR R before executing instruction:
before executing instruction: R=0x01, d=1, Z=0.
R=0x34, ACC=12, Z=0, C=0. after executing instruction:
h
A
R=0x00, Z=1.
R=0x34, ACC=12, Z=0, C=1.
ec
-T
DAA Convert ACC Data Format from DECRSZ Decrease R, Skip if 0
Hexadecimal to Decimal
Syntax: DAA Syntax: DECRSZ R, d
Operand: -- Operand: 0  R  63
W
Operation: ACC(hex)  ACC(dec) d = 0, 1.

Status affected: C Operation: R - 1  dest,
Description: Convert ACC data format from Skip if result = 0
hexadecimal to decimal after Status affected: --
T
addition operation and restore

result to ACC. DAA instruction Description: Decrease R first. If d is 0, the
must be placed immediately after result is stored in ACC. If d is 1,
h
the result is stored back to R.
A
addition operation if decimal

format is required. Please note If result is 0, the next instruction
that interrupt should be disabled which is already fetched is
ec
before addition instruction and discarded and a NOP is executed

enabled after DAA instruction to instead. Therefore it makes this
avoid unexpected result. instruction a two-cycle instruction.
Cycle: 1 Cycle: 1 or 2(skip)
-T
Example: DISI Example: DECRSZ R, d

ADDAR R,d instruction2
DAA instruction3
ENI before executing instruction:
before executing instruction: R=0x1, d=1, Z=0.
TW
ACC=0x28, R=0x25, d=0. after executing instruction:

after executing instruction: R=0x0, Z=1, and instruction will
ACC=0x53, C=0. skip instruction2 execution
because the operation result is
zero.
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DISI Disable Interrupt Globally GOTO Unconditional Branch
Syntax: DISI Syntax: GOTO adr
Operand: -- Operand: 0  adr < 511
-T
Operation: Disable Interrupt, 0  GIE Operation: {PCHBUF, adr}  PC
Description: GIE is clear to 0 in order to disable Description: GOTO is an unconditional branch
all interrupt requests. instruction. The 9-bit immediate
Cycle:
Example:
1
DISI
W
GIE=1.
T
Cycle:
address adr is loaded into PC[8:0]
and PCHBUF[1] is loaded into
PC[9].
2
After executing instruction: Example: GOTO Level
GIE=0. before executing instruction:
PC=A0.
h
A
PC=address of Level.
ec
-T
ENI Enable Interrupt Globally GOTOA Unconditional Branch
Syntax: ENI Syntax: GOTOA
W
Operation: Enable Interrupt, 1  GIE Operation: {TBHP, ACC}  PC

Description: GIE is set to 1 in order to enable all Description: GOTOA is an unconditional branch
interrupt requests. instruction. The content of
T
TBHP[1:0] is loaded into PC[9:8]

Cycle: 1 and ACC is loaded into PC[7:0].
Example: ENI
Cycle: 2
h
A
GIE=0. Example: GOTOA

After executing instruction: before executing instruction:
ec
GIE=1. PC=A0. TBHP=0x02,

ACC=0x34.
PC=0x234.
-T
TW
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INCR Increase R INT Software Interrupt
Syntax: INCR R, d Syntax: INT
Operand: 0  R  63 Operand: --
-T
d = 0, 1. Operation: PC + 1  Top of Stack,
Operation: R + 1  dest. 001h  PC
Description: Increase R. If d is 0, the result is Description: Software interrupt. First, return
Cycle:
Example:
1
W
stored in ACC. If d is 1, the result
is stored back to R.
INCR R, d
T
Cycle:
address (PC + 1) is pushed onto
the Stack. The address 0x001 is
loaded into PC[9:0].
3
before executing instruction: Example: INT
R=0xFF, d=1, Z=0. before executing instruction:
after executing instruction: PC=address of INT code
h
R=0x00, Z=1.
A
PC=0x01
INCRSZ
ec
Increase R, Skip if 0 IORAR OR ACC with R
-T
Syntax: INCRSZ R, d Syntax: IORAR R, d
d = 0, 1. d = 0, 1.
Operation: R + 1  dest, Operation: ACC | R  dest

W
Skip if result = 0 Status affected: Z

Status affected: -- Description: OR ACC with R. If d is 0, the result
Description: Increase R first. If d is 0, the result is stored in ACC. If d is 1, the result
is stored in ACC. If d is 1, the result is stored back to R.
T
is stored back to R. Cycle: 1

If result is 0, the next instruction
Example: IORAR R, d
which is already fetched is
h
discarded and a NOP is executed
A
instead. Therefore it makes this R=0x50, ACC=0xAA, d=1, Z=0.

instruction a two-cycle instruction. after executing instruction:
ec
R=0xFA, ACC=0xAA, Z=0.

Cycle: 1 or 2(skip)
Example: INCRSZ R, d
instruction2,
instruction3.
-T

R=0xFF, d=1, Z=0.
R=0x00, Z=1. And the program
will skip instruction2 execution
TW
because the operation result is

zero.
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IORIA OR Immediate with ACC IOSTR Move F-page SFR to ACC
Syntax: IORIA i Syntax: IOSTR F
Operand: 0  i < 255 Operand: 5  F  15
-T
Operation: ACC | i  ACC Operation: F-page SFR  ACC

Description: OR ACC with 8-bit immediate data Description: Move F-page SFR F to ACC.
i. The result is stored in ACC.
Cycle:
Example:
1
IORIA i
W
T Cycle:
Example:
1
IOSTR F
F=0x55, ACC=0xAA.
i=0x50, ACC=0xAA, Z=0.
after executing instruction: F=0x55, ACC=0x55.
ACC=0xFA, Z=0.
h
A
ec
-T
IOST Load F-page SFR from ACC LCALL Call Subroutine
Syntax: IOST F Syntax: LCALL adr
0  F  15 Operand: 0  adr  1023
W
Operand:
Operation: ACC  F-page SFR Operation: PC + 1  Top of Stack,
adr  PC[9:0]
Status affected: --
Status affected: --
Description: F-page SFR F is loaded by content
T
of ACC. Description: The return address (PC + 1) is

pushed onto top of Stack. The
Cycle: 1
10-bit immediate address adr is
h
Example: IOST F loaded into PC[9:0].
A

Cycle: 2
F=0x55, ACC=0xAA.
ec
after executing instruction: Example: LCALL SUB

F=0xAA, ACC=0xAA. before executing instruction:
PC=A0. Stack level=1
-T
PC=address of SUB, Stack[1]=

A0+1, Stack pointer =2.
TW
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LGOTO Unconditional Branch MOVIA Move Immediate to ACC
Syntax: LGOTO adr Syntax: MOVIA i
Operand: 0  adr  1023 Operand: 0  i < 255
-T
Operation: i  ACC
Operation: adr  PC[9:0].
Status affected: --
Status affected: --
Description: The content of ACC is loaded with
Description: LGOTO is an unconditional branch 8-bit immediate data i.
Cycle:
Example:
2
LGOTO Level
T W
instruction. The 10-bit immediate
address adr is loaded into PC[9:0]. Cycle:
Example:
1
MOVIA i
i=0x55, ACC=0xAA.
PC=A0.
ACC=0x55.
h
PC=address of Level.
A
ec
-T
MOVAR Move ACC to R MOVR Move R to ACC or R
Syntax: MOVAR R Syntax: MOVR R, d
W
d = 0, 1.
Operation: ACC  R
Operation: R  dest
Status affected: --
Status affected: Z
Description: Move content of ACC to R.
T
Description: The content of R is move to

Cycle: 1 destination. If d is 0, destination is
Example: MOVAR R ACC. If d is 1, destination is R and
h
it can be used to check whether R
A

is zero according to status flag Z
R=0x55, ACC=0xAA.
after execution.
ec
R=0xAA, ACC=0xAA. Cycle: 1

Example: MOVR R, d
R=0x0, ACC=0xAA, Z=0, d=0.
-T

R=0x0, ACC=0x00, Z=1.
TW
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NOP No Operation RETIA Return with Data in ACC
Syntax: NOP Syntax: RETIA i
Operand: -- Operand: 0  i < 255
-T
Operation: No operation. Operation: i  ACC,
Status affected: -- Top of Stack  PC
Description: No operation. Status affected: --
Cycle:
Example:
1
NOP
T W Description:
Cycle:
ACC is loaded with 8-bit immediate
data i and PC is loaded from top of
Stack as return address and GIE is
set to 1.
2
Example: RETIA i
PC=A0
h
GIE=0, Stack pointer =2. i=0x55,
A
PC=A0+1
ACC=0xAA.
ec GIE=1, PC=Stack[2],
pointer =1. ACC=0x55.
Stack
-T
RETIE Return from Interrupt and RET Return from Subroutine
Enable Interrupt Globally
W
Syntax: RETIE Syntax: RET

Operation: Top of Stack  PC Operation: Top of Stack  PC
1  GIE
T
Status affected: --
Status affected: --
Description: PC is loaded from top of Stack as
Description: The PC is loaded from top of Stack return address.
h
as return address and GIE is set to
A
1. Cycle: 2
Cycle: 2 Example: RET
ec

Example: RETIE
Stack level=2.
GIE=0, Stack level=2.
PC=Stack[2], Stack level=1.
-T
GIE=1, PC=Stack[2], Stack

pointer=1.
TW
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RLR Rotate Left R Through Carry SBCAR Subtract ACC and Carry from R
Syntax: RLR R, d Syntax: SBCAR R, d
-T
d = 0, 1. d = 0, 1.
Operation: C  dest[0], R[7]  C, Operation: R + (~ACC) + C  dest
R[6:0]  dest[7:1] Status affected: Z, DC, C
Description: Subtract ACC and Carry from R
Status affected: C
T W with 2’s complement
representation. If d is 0, the result
is placed in ACC. If d is 1, the
result is stored back to R.
Cycle: 1
Description: The content of R is rotated one bit
to the left through flag Carry. If d is Example: SBCAR R, d
0, the result is placed in ACC. If d (a) before executing instruction:
h
A
is 1, the result is stored back to R. R=0x05, ACC=0x06, d=1,
Cycle: 1 C=0.
Example: RLR R, dec
R=0xA5, d=1, C=0.
R=0xFE, C=0. (-2)
(b) before executing instruction:
R=0x05, ACC=0x06, d=1,
C=1.
-T
R=0x4A, C=1.
R=0xFF, C=0. (-1)
(c) before executing instruction:
RRR Rotate Right R Through Carry R=0x06, ACC=0x05, d=1,
C=0.
W
Syntax: RRR R, d after executing instruction:

Operand: 0  R  63 R=0x00, C=1. (-0), Z=1.
d = 0, 1. (d) before executing instruction:
Operation: C  dest[7], R[7:1]  dest[6:0], R=0x06, ACC=0x05, d=1,
T
C=1.
R[0]  C
R=0x1, C=1. (+1)
h
A
ec
Status affected: C
Description: The content of R is rotated one bit
to the right through flag Carry. If d
-T
is 0, the result is placed in ACC. If

d is 1, the result is stored back to
R.
Cycle: 1
TW
Example: RRR R, d
R=0xA5, d=1, C=0.
R=0x52, C=1.
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SBCIA Subtract ACC and Carry from SFUNR Move S-page SFR from ACC
Immediate
Syntax: SBCIA i Syntax: SFUNR S
0  i < 255 0  S  15
-T
Operand: Operand:
Operation: i + (~ACC) + C  dest Operation: S-page SFR  ACC
Status affected: Z, DC, C Status affected: --
Description: Subtract ACC and Carry from 8-bit Description: Move S-page SFR S to ACC.
Cycle:
W
immediate data i with 2’s
complement representation. The
result is placed in ACC.
1
T Cycle:
Example:
1
SFUNR S
S=0x55, ACC=0xAA.
Example: SBCIA i
(a) before executing instruction: S=0x55, ACC=0x55.
i=0x05, ACC=0x06, C=0.
h
A
ACC=0xFE, C=0. (-2)

ec
i=0x05, ACC=0x06, C=1.
ACC=0xFF, C=0. (-1)
(c) before executing instruction:
-T
i=0x06, ACC=0x05, C=0.
ACC=0x00, C=1. (-0), Z=1.
(d) before executing instruction:
W
i=0x06, ACC=0x05, C=1. SLEEP Enter Halt Mode

Syntax: SLEEP
ACC=0x1, C=1. (+1)
Operand: --
Operation: 00h  WDT,
T
00h  WDT prescaler

1  /TO
0  /PD
h
SFUN Load S-page SFR to ACC
A
Status affected: /TO, /PD

Syntax: SFUN S
Description: WDT and Prescaler0 are clear to
ec
Operand: 0  S  15 0. /TO is set to 1 and /PD is clear

to 0.
Operation: ACC  S-page SFR
IC enter Halt mode.
Status affected: --
Cycle: 1
-T
Description: S-page SFR S is loaded by content

Example: SLEEP
of ACC.
Cycle: 1 /PD=1, /TO=0.
Example: SFUN S after executing instruction:
TW
before executing instruction: /PD=0, /TO=1.

S=0x55, ACC=0xAA.
S=0xAA, ACC=0xAA.
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SUBAR Subtract ACC from R SWAPR Swap High/Low Nibble in R
Syntax: SUBAR R, d Syntax: SWAPR R, d
-T
d = 0, 1. d = 0, 1.
Operation: R – ACC  dest Operation: R[3:0]  dest[7:4].
Status affected: Z, DC, C R[7:4]  dest[3:0]
Status affected: --
Description:
Cycle:
W
Subtract ACC from R with 2’s
complement representation. If d is
0, the result is placed in ACC. If d
is 1, the result is stored back to R.
1
T Description: The high nibble and low nibble of R
is exchanged. If d is 0, the result is
placed in ACC. If d is 1, the result
is stored back to R.
Cycle: 1
Example: SBCAR R, d
(a) before executing instruction: Example: SWAPR R, d
h
R=0x05, ACC=0x06, d=1.
A
after executing instruction: R=0xA5, d=1.

R=0xFF, C=0. (-1) after executing instruction:
ec
R=0x06, ACC=0x05, d=1.
R=0x01, C=1. (+1)
R=0x5A.
-T
SUBIA Subtract ACC from Immediate TABLEA Read ROM data
W
Syntax: SUBIA i Syntax: TABLEA

Operand: 0  i < 255 Operand: --
Operation: i – ACC  ACC
Operation: ROM data{ TBHP, ACC } [7:0]
Status affected: Z, DC, C  ACC
T
Description: Subtract ACC from 8-bit immediate ROM data{TBHP, ACC} [13:8]
data i with 2’s complement  TBHD.
h
representation. The result is Status affected: --
A
placed in ACC.
Description: The 8 least significant bits of ROM
Cycle: 1
ec
pointed by {TBHP[2:0], ACC} is

Example: SUBIA i placed to ACC.
The 6 most significant bits of ROM
(a) before executing instruction:
pointed by {TBHP[2:0], ACC} is
i=0x05, ACC=0x06. placed to TBHD[5:0].
-T

Cycle: 2
ACC=0xFF, C=0. (-1)
(b) before executing instruction: Example: TABLEA
i=0x06, ACC=0x05, d=1, . before executing instruction:
after executing instruction: TBHP=0x02,CC=0x34.
TW
ACC=0x01, C=1. (+1) TBHD=0x01.

ROM data[0x234]=0x35AA.
TBHD=0x35, ACC=0xAA.
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T0MD Load ACC to T0MD XORAR Exclusive-OR ACC with R
Syntax: T0MD Syntax: XORAR R, d
Operand: -- Operand: 0  R  63
-T
Operation: ACC  T0MD d = 0, 1.
Operation: ACC  R  dest
Status affected: --
Status Z
Description: The content of T0MD is loaded by affected:
ACC.
Description: Exclusive-OR ACC with R. If d is 0,
Cycle:
Example:
1
T0MD
W
T0MD=0x55, ACC=0xAA.
T
Cycle:
Example:
the result is placed in ACC. If d is
1, the result is stored back to R.
1
XORAR R, d
after executing instruction: before executing instruction:
T0MD=0xAA. R=0xA5, ACC=0xF0, d=1.
h
A
R=0x55.
ec
-T
T0MDR Move T0MD to ACC XORIA Exclusive-OR Immediate with
ACC
W
Syntax: T0MDR Syntax: XORIA i

Operand: -- Operand: 0  i < 255
Operation: T0MD  ACC Operation: ACC  i  ACC
Status affected: -- Status Z
T
Description: Move the content of T0MD to ACC. affected:

Description: Exclusive-OR ACC with 8-bit
Cycle: 1 immediate data i. The result is
h
A
Example: T0MDR stored in ACC.

before executing instruction
Cycle: 1
T0MD=0x55, ACC=0xAA.
ec
after executing instruction Example: XORIA i

ACC=0x55. before executing instruction:
i=0xA5, ACC=0xF0.
-T
ACC=0x55.
TW
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5. Configuration Words
Item Name Options
-T
1 High Oscillator Frequency 1. I_HRC 2. E_HXT 3. E_XT
2 Low Oscillator Frequency 1. I_LRC 2. E_LXT
1. 1MHz 2. 2MHz 3. 4MHz

3 High IRC Frequency
4
W
High Crystal Oscillator
T 4.
1.
3.
8MHz
6MHz＜FHOSC≦8MHz
10MHz＜FHOSC≦12MHz
5. 16MHz
2.
4.
6. 20MHz
5. 16MHz＜FHOSC≦20MHz
5 Instruction Clock 1. 2 oscillator period 2. 4 oscillator period
h
A
1. Watchdog Enable (Software control)

6 WDT
2. Watchdog Disable (Always disable)
8
WDT Event
Timer0 source
ec 1. Watchdog Reset
1. EX_CKI
2. Watchdog Interrupt
2. Low Oscillator
-T
9 PB.3 1. PB.3 is I/O 2. PB.3 is reset
10 PB.4 1. PB.4 is I/O 2. PB.4 is instruction clock output
11 Startup Time 1. 140us 2. 4.5ms 3. 18ms 4. 72ms 5. 288ms

W
12 WDT Time Base 1. 3.5ms 2. 15ms 3. 60ms 4. 250ms
13 LVR Setting 1. Register Control 2. LVR Always On

T
1. 1.6V 2. 1.8V 3. 2.0V 4. 2.2V 5. 2.4V

14 LVR Voltage
6. 2.7V 7. 3.0V 8. 3.3V 9. 3.6 V 10. 4.2V
h
15 VDD Voltage 1. 3.0V 2. 4.5V 3. 5.0V
A
16 Read Output Data 1. I/O Port 2. Register

ec
17 E_LXT Backup Control 1. Auto Off 2. Register Off
18 EX_CKI to Inst. Clock 1. Sync 2. Async

-T
19 Startup Clock 1. Fast (I_HRC/E_HXT/E_XT) 2. Slow (I_LRC/E_LXT)
20 PWM Output Pin 1. PB.6 2. PB.2
21 Buzzer Output Pin 1. PB.7 2. PB.2

TW
22 Input High Voltage (VIH) 1. CMOS (0.7VDD) 2. TTL (0.5VDD)
23 Input Low Voltage (VIL) 1. CMOS (0.3VDD) 2. TTL (0.2VDD)
Table 16 Configuration Words
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6. Electrical Characteristics
6.1 Absolute Maximum Rating
-T
Symbol Parameter Rated Value Unit
VDD - VSS Supply voltage -0.5 ~ +6.0 V
VIN Input voltage VSS-0.3V ~ VDD+0.3 V
TOP Operating Temperature -40 ~ +85 °C
6.2
TST
DC Characteristics
T W
Storage Temperature -40 ~ +125 °C
(All refer FINST=FHOSC/4, FHOSC=16MHz@I_HRC, WDT enabled, ambient temperature TA=25°C unless otherwise specified.)
Symbol Parameter VDD Min. Typ. Max. Unit Condition
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3.3 FINST=20MHz @ I_HRC/2
2.2 FINST=20MHz @ I_HRC/4
VDD
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Operating voltage --
3.0
2.0
2.0 -- 5.5 V
FINST=16MHz @ E_HXT/2
FINST=16MHz @ E_HXT/4
FINST=8MHz @ I_HRC/4 & I_HRC/2
-T
FINST=8MHz @ E_HXT/4 & E_HXT/2
FINST=4MHz @ I_HRC/4 & I_HRC/2
1.8
FINST=4MHz @ E_XT/4 & E_XT/2
FINST=32KHz @ I_LRC/4 & I_LRC/2
1.8
W
FINST=32KHz @ E_LXT/4 & E_LXT/2

5V 4.0 -- --
V RSTb (0.8VDD)
3V 2.4 -- --
5V 3.5 -- -- All other I/O pins, EX_CKI, INT
T
VIH Input high voltage V

3V 2.1 -- -- CMOS (0.7VDD)
5V 2.5 -- -- All other I/O pins, EX_CKI
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V
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3V 1.5 -- -- TTL (0.5VDD)

5V -- -- 1.0
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V RSTb (0.2VDD)
3V -- -- 0.6
5V -- -- 1.5 All other I/O pins, EX_CKI, INT
VIL Input low voltage V
3V -- -- 0.9 CMOS (0.3VDD)
-T
5V -- -- 1.0 All other I/O pins, EX_CKI

V
3V -- -- 0.6 TTL (0.2VDD)
5V -- -20 -- VOH=4.0V
IOH Output high current mA
3V -- -10 -- VOH=2.0V
TW
5V -- 40 --
IOL Output low current mA VOL=1.0V
3V -- 26 --
5V -- 40 --
IIR IR sink current mA Normal IR
3V -- 26 --
69 Ver. 1.6 2020/03/20

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Symbol Parameter VDD Min. Typ. Max. Unit Condition
Normal Mode
5V -- 2.7 --
-T
mA FHOSC=20MHz @ I_HRC/2 & E_HXT/2
3V -- 1.3 --
5V -- 2.1 --
3V -- 1.0 --
5V -- 2.4 --
T W 3V
5V
3V
5V
--
--
--
--
1.1
1.9
0.8
1.5
--
--
--
--
mA
mA
FHOSC=16MHz @ I_HRC/2 & E_HXT/2

3V -- 0.7 --
5V -- 1.3 --
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3V -- 0.5 --
5V -- 1.1 --
IOP
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Operating current
3V
5V
3V
--
--
--
0.5
0.9
0.4
--
--
--
mA
mA

-T
5V -- 0.9 --
3V -- 0.4 --
5V -- 0.8 --
3V -- 0.4 --
W
Slow mode
5V -- 6.0 -- FHOSC disabled,
uA
3V -- 2.7 -- FLOSC=32KHz @ I_LRC/2
T
uA
3V -- 2.9 -- FLOSC=32KHz @ E_LXT/2.
uA
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FLOSC=32KHz @ I_LRC/4
A
3V -- 1.8 --
uA
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3V -- 2.0 -- FLOSC=32KHz @ E_LXT/4.

5V -- 2.7 -- Standby mode, FHOSC disabled,
ISTB Standby current uA
3V -- 1.1 -- FLOSC=32KHz @ I_LRC/4
5V -- -- 0.5
-T
uA Halt mode, WDT disabled.

3V -- -- 0.2
IHALT Halt current
5V -- -- 5.0
uA Halt mode, WDT enabled.
3V -- -- 2.0
TW
5V -- 50 --
RPH Pull-High resistor kΩ Pull-High resistor
3V -- 100 --
5V -- 50 --
RPL Pull-Low resistor kΩ Pull-Low resistor
3V -- 100 --
70 Ver. 1.6 2020/03/20

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6.3 OSC Characteristics
(Measurement conditions VDD Voltage, TA Temperature are equal to programming conditions.)
Parameter Min. Typ. Max. Unit Condition
-T
I_HRC deviation by socket ±1 % Socket installed directly on writer.
I_HRC deviation by handler ±3 % Handler condition with correct setup.
6.4 Characteristic Graph

T W
I_LRC deviation by handler ±5 %
6.4.1 Frequency vs. VDD of I_HRC
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-T
W
6.4.2 Frequency vs. Temperature of I_HRC

T
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-T
TW
71 Ver. 1.6 2020/03/20

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6.4.3 Frequency vs. VDD of I_LRC
-T
T W
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6.4.4 Frequency vs. Temperature of I_LRC
-T
T W
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6.5 Recommended Operating Voltage

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Recommended Operating Voltage (Temperature range: -40 °C ~ +85 °C)
LVR :
LVR : default
Frequency Min. Voltage Max. Voltage Recommended
( 25 °C)
(-40 °C ~ +85 °C)
-T
20M/2T 3.3V 5.5V 3.6V 4.2V
16M/2T 3.0V 5.5V 3.3V 3.6V

TW
20M/4T 2.2V 5.5V 2.4V 3.0V
16M/4T 2.0V 5.5V 2.2V 2.4V
8M(2T or 4T) 2.0V 5.5V 2.2V 2.4V

≦6M(2T or 4T) 1.8V 5.5V 2.0V 2.2V
72 Ver. 1.6 2020/03/20

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6.6 LVR vs. Temperature
-T
T W
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-T
7. Die Pad Diagram
T W
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-T
TW
73 Ver. 1.6 2020/03/20

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8. Package Dimension
8.1 8-Pin Plastic SOP (150 mil)
-T
T W
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-T
Note: For 8-pin SOP, 100 units per tube.
8.2 14-Pin Plastic SOP (150 mil)

T W
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-T
Note: For 14-pin SOP, 50 units per tube.

TW
74 Ver. 1.6 2020/03/20

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8.3 14-Pin Plastic DIP (300 mil)
-T
T W
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Note: For 14-pin Plastic DIP, 25 units per tube.
9. Ordering Information
P/N
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Package Type Pin Count Package Width Shipping
-T
AT8A53D Die -- -- --
Tape & Reel: 2.5K pcs per Reel
AT8A53DS8 SOP 8 150 mil
Tube: 100 pcs per Tube
Tape & Reel: 2.5K pcs per Reel
W
AT8A53DS14 SOP 14 150 mil

Tube: 50 pcs per Tube
AT8A53DP14 PDIP 14 300 mil Tube: 25 pcs per Tube
T
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-T
TW
75 Ver. 1.6 2020/03/20

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h

Mar. 20, 2020

1.0 2016/08/24 Formal release. -

Modify “Input Voltage Level” options in Configuration Words.

1. Modify the pin description of PB3. 11

1. Modify Figure 2 Program Memory Address Mapping.

2 Ver. 1.6 2020/03/20

1. General Description ································································································ 8

2. Memory Organization ····························································································· 12

3. Function Description ······························································································ 16

3.1.3 PCL (Low Byte of PC[9:0]) ······························································································ 16

3.1.6 PortA (PortA Data Register) ···························································································· 18

3.1.8 PCON (Power Control Register) ······················································································ 18

3.1.10 PCHBUF (High Byte of PC) ···························································································· 19

3.1.13 INTE (Interrupt Enable Register) ······················································································ 20

3.3 F-page Special Function Register ·················································································· 22

3 Ver. 1.6 2020/03/20

3.8 IR Carrier ················································································································· 41

3.10.1 Timer0 Overflow Interrupt ······························································································· 43

3.10.3 WDT Timeout Interrupt ·································································································· 44

3.10.5 External Interrupt ·········································································································· 44

3.12 Operating Mode········································································································· 46

3.12.3 Standby Mode ············································································································· 48

4 Ver. 1.6 2020/03/20

4. Instruction Set ······································································································· 52

6. Electrical Characteristics ························································································ 69

8.1 8-Pin Plastic SOP (150 mil) ·························································································· 74

9. Ordering Information ······························································································ 75

5 Ver. 1.6 2020/03/20

在省電的模式下如待機模式(Standby mode)與睡眠模式(Halt mode)中，有多種事件可以觸發中斷喚醒AT8A53D進入

 寬廣的工作電壓：(指令週期為 4 個CPU clock，亦即 4T模式)

6 Ver. 1.6 2020/03/20

7 Ver. 1.6 2020/03/20

 2.0V ~ 5.5V @system clock ≦8MHz.

 Wide operating temperature: -40°C ~ 85°C.

 PB[3] have feature of input or open-drain output.

8 Ver. 1.6 2020/03/20

 Direct and indirect addressing modes for data access.

 One 8-bit reload or continuous down-count timers (Timer1).

 One 8-bit resolution PWM (PWM1) output.

Built-in Power-On Reset (POR).

 Built-in Watch-Dog Timer (WDT) enabled/disabled by firmware control.

 Four kinds of operation mode to reduce system power consumption:

 Five hardware interrupt events:

 WDT timeout interrupt.

 Five interrupt events to wake-up AT8A53D from Standby mode:

 WDT timeout interrupt.

 Three interrupt events to wake-up AT8A53D from Halt mode:

 WDT timeout interrupt.

9 Ver. 1.6 2020/03/20

1.3 Pin Assignment

Figure 1 Package pin assignment

10 Ver. 1.6 2020/03/20

Pin Name I/O Description

PB0 is a bidirectional I/O pin.

PB1/ IR/ SDO I/O

PB2 is a bidirectional I/O pin.

PB2 is output of Buzzer signal by configuration words.