Chap. 2 Basic MOS Device Physics ‘Accumulation ‘Strong Inversion Figure 2.46 Capacitance-voltage Vos characteristic of an NMOS device. vm References [1] R.S. Muller and 7.1, Kamins, Device Electrons for Integrated Circuits, nd ed, (New York: Wiley, 1986). [2] ¥. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. (Boston: MeGraw-Hill, 1999), [3] ¥ Taurand T. H, Ning, Fundamentals of Modern VLSI Devices (New York: Cambridge University Press, 1998), Unless otherwise slated, inthe following problems, use the device data shown in Table 2.1 and assume Vp v where necessary. 2a. 22. 23. 24. 25. For W/L = 50/0.5, plot the drain current of an NFET and a PFET as a function of [Vis] a8 [Vas varies from (0t03 V. Assume that [Vos] = 3 V. For W/L = 50/0.5 and [f[p| = 0.5 mA, calculate the transconductance and output impedance of both NMOS. and PMOS devices. Also find the “intrinsic gain," defined a8 gro Derive expressions for gmro in terms of Ip and W/L. Plot gmro asa function of fp with L as a parameter Note that b 0 L/L Phot fp versus Vas for a MOS transistor (a) with Vps as parameter, and (b) with Vag as a parameter. Identify the break points inthe characteristics. ‘Sketch Fy and the transconductance of the transistor as a function of Vy for each citcuit in Fig. 247 as Vx varies from 0 to Vpp. In part (a) assume that Viz varies from 0 to 1.5 V. Yoo he my HV Hove HVC) © Vx Figure 2.47Problems 39 26, Sketch Ly and the transconductance of the transistor as a function of Vx for each cigcuit in Fig, 2.48 as Vir varies from 010 Vip. Yoo R hx Ry Ix my My Re Rm Vx ® © 42 Figure 2.48 27. Sketch Vous 86 a function of Vix for each circuit in Fig. 2.49 as Vig varies from 0 to Vp. Figure 2.4940 Chap.2 Basic MOS Device Physics 28. Sketch Vous as a function of Vj, for each circuit in Fig, 2.50 as Vin varies from 0to Vip @ o) Figure 2.50 29. Sketch Vy and Jy as a function of time for each cir Tn par (¢), assume thatthe switch turns off at = 0, in Fig. 2.51. The intial voltage of C) is equal to 3 V. My Yoo p he So ve Motta Ee mm Ter Te a) (b) cc) x vy a % “a «vedi te, Yee Tr 4 F 4 () fe) Figure2.51 240, Stetch Vy and Jy asa function of time foreach circuit in ig 2.52. The intl voltage ofeach capacitor i shown 1 Ie Vx Vc +2avediom, Tt 42vedim, TO @ (o) o Figure 2.52,Problems a 2AL. Sketch Vx as a function of time for each circuit in Fig, 2.53. The initial voltage of cach capacitor is shown, mip Yeo Ve 43 hv : ve “T, my AV iQ. ave MOF ° awwite, ° ) Figure 2.53 242, Sketch Vx as a function of time for each circuit in Fig, 2.54, The initial voltage of each capacitor is shown, Yoo o ) Figure 2.54 243, The transit frequency, fr, of a MOSFET is defined as the frequency at which the small-signal current gain of the device drops to unity while the source and drain terminals are held al ae ground {a Prove that fr ess)42 2d. 25. 2.16. 2a. 28. 219. 2.20. 221. 2.22. 223. Chap.2 Basic MOS Device Physics Note that fr docs not include the effect of the S/D junction capacitance: (b) Suppose the gate resistance, Ro, is significant and the device is modeled as adistuibuted set of» transistors, cach with a gate resistance equal to Rg/m, Prove that the fr of the device is independent of Re and still equal (o the value given above. (6) For a given bias current, the minimum allowable drsin-source voltage for operation in saturation can be reduced only by increasing the width and hence the capacitances of the transistor, Using square-law characteristics, prove that, in Vas = Vw -# (2.56) ir This elation indicates how the speed is limited as « device is designed to operate with lower supply voltages Calculate the fr of a MOS device in the subthreshold region and compare the resull with that obtained in Prob. 2.13 For a saturated NMOS device having W = $0 wm and L = 0.5 jum, calculate all the capacitances. Assume thatthe minimum (lateral) dimension of the S/D areas is 15 jam and that the device is folded as shown in Fig. 2.33(b). What is the fr ifthe drain current is | mA? Consider the structure shown in Fig. 2.55, Determine Ip, asa function of Vas and Vps, and prove that the structure can be viewed as a single Wansistor having an aspect ratio W/(2L). Assume that 2. = y = 0. ne Vos ne Figure 2.55 For an NMOS device operating in saturation, plot W/L versus Vas — Vii if (@) Ip is constant, and (©) bm is constant Explain why the structures shown in Fig, 2.56 cannot operate as cutrent sources even though the transistors ae in saturation Voo 4 i Hs @ ®) plain intuitively why y is directly proportional to Nine Figure 2.56 Considering the body effect as “back-gate effect” and inversely proportional to Cox. ‘A “ting” MOS structure is shown in Fig. 2.57. Explain how the device operates and estimate its equivalent aspect ratio, Compare the drain junction capacitance of ths structure with that of the devices shown in Fig. 2.33, ‘Suppose we have received an NMOS transistor in a package with four unmarked pins. Describe the minimum ‘number of de measurement steps using an ohmameter that is necessary to determine the gate, sourceddrain, and bulk terminals ofthe device, Repeat Prob. 2.21 ifthe type ofthe device (NFET or PFET) is not known, For an NMOS transistor, the threshold voltage is known, bu nox and W/L are not, Assume that = y = 0. If we cannot measure C,, independently, is it possible to devise a sequence of de measurement tests 10 determine Jip Cox and W/L? What if we have two transistors and we know that one has twice the aspect ratio of the other?Problems 43 w Figure 2.57 2.24, Sketch Iy versus Vy for each of the composite structures shown in Fig. 2.58 with Vg as a parameter. Also, sketch the equivalent transconductance, Assume that 0 @ ) Figure 2.58 228, An NMOS current source with /p = 0.5 mA must operate with rain-surce vllages a8 low as 0.4. If he ‘minimum required output impedance is 20 X02, determine the width and length ofthe device. Calculate the gate-source, gate-drin, and drain-substrate eapecitance ifthe device is folded asin Fig. 233 and E = 3 jm 2.26, Consider the circuit shown in Fig. 259, whete the inital voltage at node X is equal to Vip. Assuming that 3 = y = O and neglecting other capacitances, plot Vie and Vy versus time if (2) Vig is & postive step with amplitude Vp > Via, and () Vip isa negative step with amplitude Vo = Vier Figure 2.59 2.27. Aa NMOS device operating in the subthreshold region has a£ of 1.5. What variation in Vo results in a tenfold change in Ip? If Ip = 10 eA, what is,”44 Chap.2 Basie MOS Device Physics 2.28. Consider an NMOS device with Vg — 1.5 V and Vs — 0. Explain what happens if we continually decrease Vp below zero or increase Viuy above ze. 2.29. Consider the arrangement shown in Fig. 2.60, Explain what happens tothe pinch-off point as Ve; increases, Figure 2.60 2.30. From Fig. 2.20, plot Ip vs. Ve vs. Vas ~ Vnw if Ip is constant 2.31, Plotted in Fig. 2.61 are the characterstis of a squate-law NMOS device with W/Lirayy = 5 10/40 nm and fox = 18 A. Hete, Vos is incremented in equal steps. Estimate joy, Vir, 2. and the Ves steps. = Vrw if W/L is constant, Vos ~ Vira v8. Ip if W/L is constant, and W/L 35 3 25 Ip (ma) 0.2 4 06 0.8 1 Vos (V) Figure 2.61