LSI/CSI

UL
®

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
LS7210
(631) 271-0400 FAX (631) 271-0405
A3800

PROGRAMMABLE DIGITAL DELAY TIMER February 1998

PIN ASSIGNMENT - TOP VIEW

FEATURES:
• Programmable Delay from 6 ms to "Infinity" B 1 14 V SS (+V)

LSI
• Can be Cascaded for Sequential Events or Extended Delay
• +4.75V to +15V Operation (Vss -VDD) A 2 13 OUT
• On Chip Oscillator or External Clock time base
• High Noise Immunity TRIGGER 3 12 WB0
• LS7210 (DIP), LS7210-S (SOIC)-See Figure 1

LS7210
CLOCK SELECT 4 11 WB1
DESCRIPTION:
The LS7210 is a monolithic MOS integrated circuit programmable OSCILLATOR 5 10 WB2
digital timer that can generate a delay in the range of 6ms to infinity.
EXTERNAL CLOCK 6 9 WB3
The delay is programmed by 5 binary weighted input bits in combina-
tion with the time base provided. The chip can be operated in four 7 8
V DD (-V) WB4
different modes: Delayed Operate, Delayed Release, Dual Delay
and One Shot. These modes are selected by the control inputs A
FIGURE 1
and B.
TABLE 1. WEIGHTING BITS ASSIGNMENTS
INPUT/OUTPUT DESCRIPTION:
OSCILLATOR Input (Pin 5) INPUTS VALUE
The frequency of the internal oscillator is set by an RC network con- WB0 1
nected to the OSC input, as shown in Figure 2. The nominal os- WB1 2
cillator frequency, f, at room temperature is given by f≈1/RC where R WB2 4
values range from a minimum of 47KΩ to a maximum 3MΩ. WB3 8
NOTE: Oscillation accuracy from chip to chip for a fixed value of RC, WB4 16
is + 10%. (Parts can supplied to tighter tolerances.)
Example: For a weighting factor of 25, inputs WB4, WB3, and
EXTERNAL CLOCK Input (Pin 6) WB0 should be programmed to logic 0.
If the internal oscillator is not used, the chip can be driven by an ex-
ternal clock applied to this input. MODE SELECT Inputs A, B (Pins 2, 1)
The chip can be programmed to operate in four different modes
CLOCK SELECT Input (Pin 4) by applying the logic levels to inputs A and B as indicated in
The internal oscillator or the external clock is selected by the proper Table 2. The mode select inputs are clocked into the input latch-
logic level applied to this input. A logic 1 selects the external clock es with the negative edge of the time base clock. These inputs
and logic 0 selects the internal oscillator. (See Note 1) should not be changed while a delay timing is in progress. (See
Note 1)
TRIGGER Input (Pin 3) TABLE 2. MODE SELECTION
A positive or a negative transition at the trigger input initiates a delay
in turning on or off the output. A negative transition always turns on CONTROL MODE
the output with or without delay depending on the selected mode. A A B
positive transition at the trigger input always turns off the output (with 1 1 Dual Delay
the exception of one-shot mode) with or without delay depending on 1 0 Delayed Release
the selected mode. The delay is a function of the time base fre- 0 1 Delayed Operate
quency and the weighting factor programmed at the weighting bit in- 0 0 One Shot
puts. The trigger input is clocked into the input latch with the neg-
ative edge of the selected time base clock. All timings begin after the OUT Output (Pin 13)
latch has been set up. (See Note 1) The output is an open drain FET. To obtain proper switching of
the output between Logic 0 and 1 levels, an external pull down re-
sistor to VDD must be used. If the output is used only as a current
WEIGHTING FACTOR Inputs, WB0-WB4 (Pins 12-8) source, no such pull down is needed. The output is logically in-
A delay from the trigger input to the output is programmed by ap- verted with respect to the trigger input.
plying 1's complement binary weighted numbers at these 5 inputs.
(See Note 1) The exact equation for the delay is: VSS, VDD (Pins 14, 9)
Supply voltage positive, negative terminals.
Delay = (1 + 1, 023N) f = Oscillation Frequency
f N = Weighting Factor NOTE 1: These inputs have internal pullup resistors.

7210-041700-1
MODE DEFINITION TIMING DIAGRAM: (See Figure 3) DELAYED RELEASE MODE
This mode causes a retriggerable delay in turning off the output
DUAL DELAY MODE whenever there is a positive transition at the trigger input. The out-
Thls is the Default Mode when the inputs A and B are left un- put is turned on without delay in response to a negative transition at
programmed. The function of the Dual Delay mode is to provide a the trigger input.
time delay on both the turn-on and turn-off of the output. Once turned
on, the output will remain on as long as the trigger input is Logic 0. ONE-SHOT MODE
Once turned off, the output will remain off as long as the trigger input In this mode, the chip functions like a retriggerable monostable
is a logic 1. multi-vibrator. The output is turned on whenever there is a negative
transition at the trigger input. At the end of the programmed delay,
DELAYED OPERATE MODE the output is turned off automatically. If there is a negative transition
This mode causes a retriggerable delay in turning the output on in re- at the trigger input before the delay is over, the delay is restarted.
sponse to a negative edge at the trigger input. The output is turned A positive transition at the trigger input has no effect on the output
off without delay in response to a positive transition at the trigger in- in this mode. NOTE: In One-Shot mode, the TRIGGER input must
put. be held at logic 1 during a power-up.

ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to VDD)

SYMBOL VALUE UNIT
DC Supply Voltage VSS +18 V
Voltage (Any Pin) VIN 0 to VSS+.3 V
Operating Temperature TA -25 to +70 °C
Storage Temperature TSTG -65 to +150 °C

DC ELECTRICAL CHARACERISTICS:
(-25°C ≤TA ≤+70°C unless otherwise specified. All voltages referenced to VDD)

PARAMETER SYMBOL MIN MAX UNIT CONDITION

Suppy Voltage VSS +4.75 +15.0 V
Supply Current ISS - 3.0 mA VSS = +15V, output off

Trigger Input
Logic 1 VTH VSS -1 VSS V -

Logic 0 VTL 0 .2VSS V -

All Other Inputs

Logic 1 VIH .8VSS VSS V -

Logic 0 VIL 0 .2VSS V -

Output
Source Current Io +1.0 - mA VSS = + 5V
for Vo = Vss - 1V Io +2.8 - mA VSS = +10V
Io +4.2 - mA VSS = +15V

SWITCHING CHARACTERISTICS: (See Figure 4)

PARAMETER SYMBOL MIN MAX UNIT
Oscillator Frequency fOSC - 50 KHz

External Clock Frequency fext DC 160 KHz

External Clock, Positive Pulse Width tH 3 - µs
External Clock, Negative Pulse Width tL 3 - µs

A,B and Trigger Input Set-Up Time tS - 300 ns

Time-base Clock to Output Delay

(turn-on delay in Delayed Release mode
and turn-off delay in Delayed Operate mode) tnd - 1 µs

Time-base Clock to Output Delay at the End of Time Out tod - 1.6 µs

Time-base Clock to Output Delay tsd - 600 ns

(turn-on delay in One- Shot Mode)

7210-020298-2
 +V TRIGGER

14
OUT (Dual Delay)
V SS
+V (C)

C
5 OUT (Delayed Release)
LS7210

OSC

OUT (Delayed Operate)

(D)
V DD
7

FIGURE 2.
LS7210 OSCILLATOR CONNECTION OUT (One-Shot) <

(A) (B) (E)

FIGURE 3. MODE DEFINITION TIMING DIAGRAM

A - Turn-off delay in Dual Delay and Delayed Release mode.

The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems, B - Turn-on delay in Dual Delay and Delayed Operate mode; one-shot period in One-Shot mode.
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may C - Output remains on in Delayed Release and Dual Delay modes due to negative trigger
result from its use. transition before the turn-off delay is over.
D - Output remains off in Delayed Operate mode due to positive trigger transition before
the turn-on delay is over.
E - One-Shot period extended by re-triggering.
Note: ∆ is the programmed delay.

tL

TIME-BASE CLK tH

DELAYED RELEASE MODE ONE-SHOT

MODE

B
ts
TRIGGER

t od t od
t nd t sd

PROGRAMMED
OUT TURN-OFF
DELAY

FIGURE 4. LS7210 TIMING DIAGRAM

N o t e 1 . - A,B and Trigger inputs are clocked into the input latches with the negative edge of the time-base clock.
N o t e 2 . - In all modes except One-Shot, the output changes with the positive transition of the time-base clock.
In One-Shot mode the output is turned on with the negative transition and turned off with the
positive transition of the time-base clock.

7210-020298-3
 +V
FIGURE 5. LS7210 BLOCK DIAGRAM
+V

CLOCK 8 WB4
SELECT 4
9 WB3
EXT 6
10 WB2
CLOCK
+V 11 WB1
CLOCK 12 WB0 +V
SELECT
LOGIC
OSC 5 PRESCALER OUTPUT
÷ 1023 LATCH
(SEE NOTE) TIMER 13 OUT

+V

POR
GENERATOR
A 2 LATCH 2

+V

CONTROL LOGIC
B 1 LATCH

+V

TRIGGER 3 LATCH

V SS 14 +V

V DD 7 -V
NOTE: ÷ 1023 is standard. Any number from 1 to 1022 can be mask programmed.

FIGURE 6. ASYMMETRICAL FLASHER

1 14
B V SS +V

2 13
A OUT OUT

3 12
TRIG WB0
+V 4
LS7210

CS WB1 11
8.068 s
.005µF
f 5 WB2 10
OSC
OUT
68K 6 EXT 9
WB3
CLK
7 8
V DD WB4 323ms

47K
f = 3.17KHz

NOTE: Inputs A, B in Dual-Delay mode. For symmetical flasher tie Pins 8, 9, 10, 11 & 12 to fixed logic level.

7210-020298-4