CLOCK RECOVERY IN HIGH-SPEED MULTILEVEL SERIAL LINKS

Faisal A. Musa and Anthony Chan Carusone

Email: [email protected]
Dept. of Electrical and Computer Engineering, University of Toronto
I O King's College Rd., Toronto, CANADA, MSS 3G4
ABSTRACT ber of signal levels is increased because this method can achieve
clock recovery by monitoring a single level.
This paper introduces a simple and hardware efficient clock
recovery method for high speed serial links and compares its per- 2. TIMING RECOVERY FROM MULTILEVEL SIGNALS
formance with conventional techniques. Conventional methods Timing recovery using linear or hang-bang PD is basically
are conceptually complex and difficult to realize since they rely accomplished by using data transitions to update the phase of the
on data transitions to recover the clock by oversampling the sampling receiver clocks. When considering multilevel signals,
received signal, In contrast, the new method monitors one or more only symmetric zero crossings (i.e. transitions to the same magni-
signal levels and aligns the clock sampling phase with the maxi- tude level but opposite polarity) are to be considered, as illus-
mum vertical data eye opening by using the minimum mean trated in Fig. 1. Conventional methods require on-chip coding to
squared error algorithm. Besides being easily implementable in a guarantee a high enough symmetric zero crossing density for reli-
standard CMOS technology, this new method requires only baud able clock recovery 131.
rate sampling and is independent of the data transition density.
Behavioral simulations predict superior performance of this
method compared to a conventional bang bang phase detector
based architecture.
1. INTRODUCTION
The explosion in the number of Internet users has led to an
enormous amount of data being handled by the Internet backbone.
The resulting demand in network data bandwidth has motivated
the development of high speed serial links. Applications for serial
links include transferring voice, data and high resolution graphics
via coaxial cable, network backplanes and optical fibres a1 data
rates from 622 Mbls to 10GbIs with a near future target of 40Gbls
[I]. However, finite transmission channel bandwidth, CMOS cir- Fig. 1. Symmetric and asymmetric zero crossings in a
cuit speed limitations and stringent jitter requirements on the multilevel signal.
clock sources are the main challenges of increasing the data rate.
One solution is to use multilevel pulse amplitude modulation Instead of monitoring zero crossings. SSMMSE timing recov-
(PAM) signaling which encodes multiple bits per symbol and ery monitors one or more signal levels and adjusts the clock phase
requires less bandwidth than conventional non-return to zero such that the error between the sampled value of data and the cor-
(NRZ) signaling for the same data rate. However, clock and data responding signal level is minimized.
recovery (CDR) of multilevel PAM signals is complicated by the
existence of asymmetric transitions which result in zero crossings 2.1 Linear Phase Detector based CDR
that are misplaced from the midpoint between two consecutive Linear phase detectors produce pulses that are proportional to
symbols. These transitions must he ignored by the phase detector the phase error between the transition edge of the transmitted data
(PD) in the CDR. Moreover, as the number of levels in the PAM and the sampling clock. The width or the amplitude of the PD
signal is increased to save bandwidth over conventional NRZ pulses are varied linearly in accordance to the phase error.
transmission, the CDR circuit increases in complexity and power For multilevel PAM timing recovery, extra circuitry is
consumption. required to allow the PD output to be processed only during sym-
This paper describes a novel multilevel PAM timing recovery metric zero crossings. This is achieved by sampling the data both
technique that neither requires monitoring of the data transitions at the transition edge and at the center of the data eye [31. The
nor oversampling of the received waveform. It basically uses a former samples are used to calculate the phase error whereas the
Bang-Bang PD to generate earlyllate pulses based on minimum latter samples are digitized and are used to detect symmetric zero
mean squared error (MMSE) criteria [2]. Called Sign-Sign crossings in a transition detector. Once a symmetric zero crossing
MMSE (SSMMSE), this method is simple both conceptually and is detected by the transition detector, the corresponding phase
in terms of hardware implementation. Also, it requires only baud error is utilized to correct the sampling phase. Fig. 2 illustrates
rate sampling of the received waveform thus eliminating the need this PD for a full rate clock.
for quadrature clocks in a half rate system. There is almost no The advantage of this technique is the low jitter of the recov-
penalty in circuit complexity and power consumption as the num- ered clock. However. this method is less robust since the PD is

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 basically analog. Also, to reduce the on-chip frequency require- 2.3 SSMMSE Phase Detector based CDR
ment, it is always desirable to recover a half or lower rate clock. In this method. the following two quantities are required:
For oversampling at twice the baud rate using a half or lower rate 1) The slope of the received signal at the sampling instant.
clock, the VCO must be capable of generating precisely matched 2) The error between the sampled value and a particular signal
multiple clock phases. This leads to a complicated VCO structure level.
and higher power consumption. These two quantities are used to correct the VCO sampling
phase (i. e. rising edge of the full rate clock) such that the mean
4- P A v T K b w - TTransition squared error [21 is minimized. As a result the VCO positions the
signal & Hold Detector sampling phase at the maximum data eye opening. The technique
is best understood by referring to the eye diagram of Fig. 4.

Sample
& Hold
Error output
CLK Amplifier

Fig. 2. Multilevel PAM timing recovery using linear phase

detector[3] with a full rate clock.

2.2 Bang-Bang Phase Detector based CDR

The bang-bang (or Alexander) phase detector generates a
binary output that indicates whether the clock leads or lags the
data. The data is sampled during rising and falling edges of the
full rate clock and the PD generates earlyllate pulses by compar-
ing three consecutive data samples (denoted by ‘a’,’b’,’c’).During
a data transition (i.e. a & c are unequal), if the data samples dur- Fig. 4. Eye diagram for &PAM signal.
ing consecutive rising and falling edges of the clock have the
Let A be the sampled data due to a clock sampling phase oft,.
same logic level (i.e. a & b are equal), then the clock is early oth-
The sampling phase being incorrect, the sampled data deviates
erwise the clock is late:
from the desired signal level (which is + O S in this case) thus pro-
a = b f c + EarIyPuIse
ducing a finite positive error. Therefore, to decrease the mean
a f b = c + Latepulse
squared error, the VCO frequency must decrease so that the sam-
These early and late pulses can be used to drive a charge
pled data point is C instead of A. Point C differs from point A in
pump. When the loop is in lock, alternate early and late pulses are
terms of slope and error. Thus a knowledge of these two quantities
applied to the charge pump.
can be utilized to delay the clock sampling phase. Again, if the
For multilevel PAM timing recovery, a,b.c signals only in the sampling phase is 1) (i.e. point B) the VCO frequency must
vicinity of symmetric transitions are applied to the PD logic to
increase to advance the clock phase to t2. The decision to advance
generate earlyfiate pulses. A possible implementation is shown in
or delay the sampling phase can be based on the signs of the error
Fig. 3 for a full rate clock. This method is more robust than the
and the slope at the sampling point as shown in Table I , Here a
linear method since the PD is basically digital. However, this
positive errorlslope is denoted by 1 and a negative errodslope by
method suffers from higher jitter in the recovered clock. Also, for
0
half or lower rate clocks this method requires the VCO to produce
multiple clock phases. TABLE 1. SSMMSE PD Truth T a b l e

Consequently, earlynate pulses can be generated using XOW

XNOR gates:
EarIy = e @ s
Late = ebs
Fig. 3. Multilevel PAM timing recovery using Alexander The error with respect to a particular signal level can be gen-
phase detector with a full rate clock. erated by a comparator. A level detector ensures that data samples
only in between reference levels Vmfl & V,en are used to gener-

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 ate the PD logic. The additional hardware required to generate the the constant parameter instead of the settling time to realize simi-
slope is minimal since this is usually readily available elsewhere. lar loop dynamics for the three CDRs. However, determination of
For example, an integrate and dump circuit, which is commonly the loop bandwidth of nonlinear PD based CDRs is complicated
used to perform filtering in many receivers [4] has the following since the PD gain is not well defined. Again since the loop band-
input-output relationship at any instant 7 : width and settling time are inversely related, constant settling
time would imply fixed loop bandwidth for all practical purposes.
y(kT+7) = fr+' u(r)dr Table 2 shows that for the 5ame charge pump gain, two differ-
(k- I)T+r
ent sampling clock phases are produced for the SSMMSE CDR
where U and y are the input and output signals respectively. Thus when monitoring a maximudminimum level (+1.51-1.5) and a
the derivative of the output can be expressed as, mid-level (+0.5/-0.5). The difference can be explained by refer-
y ( k T + r ) = u(kT+.r)-u((k- I ) T + 7 ) ring to Fig. 6 where the mean squared error is plotted against sam-
The sign of the slope can be obtained by comparing the cur- pling phase for two different levels.
rent value of the input with a sample of U delayed by one symbol TABLE 2. Comparison of SSMMSE PD based
period, T. Fig. 5 shows the complete block diagram of SSMMSE CDR performance (single level)
timing recovery when monitoring + O S level. When monitoring
more than one level, the PD outputs of the individual levels must
be combined by an OR gate.

Fig. 5. Multilevel PAM timing recovery using SSMMSE PD

with a full rate clock (+OS level is being monitored).

As mentioned before, the other two methods if implemented Fig. 6. Mean squared error vs. sampling phase for the
with a half or lower rate clock, would require a complicated VCO SSMMSE CDR for +l.S & 0.5 levels.
that generates perfectly matched multiple clock phases. But The minimum mean squared error (MMSE) occurs at l.lrad
SSMMSE is a simpler alternative for high speed serial links since and 1.35 rad for +0.5 level and + I 3 level respectively, as pre-
it always requires half the number of clock phases as that required dicted in the transient simulation (Table 2). Although the mini-
by the other two methods. For example, to retime the data with a mum error is larger for the + I S level, the jitter is lower. This is
quarter rate clock, the other two methods would require eight because SSMMSE is not concerned with the magnitude of the
clock phases separated in phase by 45' but the SSMMSE method mean squared error: it only uses the MMSE algorithm to detect
requires only four clock phases separated in phase by 90'. How-
whether earlyllate pulses should be applied to the charge pump.
ever, its jitter performance is inferior to that of linear PD based
The width or amplitude of the earlyflate pulses remain unchanged
CDRs.
irrespective of the MSE. The dip of the curves in Fig. 6 near the
3. SIMULATION RESULTS MMSE indicate the jitter. A sharper dip (as observed for the +1.5
level monitoring) implies less variation around the sampling
The behavioral simulation based performance of linear, bang-
phase corresponding to the MMSE, thus producing less jitter. The
bang and SSMMSE PD based CDRs in recovering the clock of a
acquisition of phase for the two CDRs is shown in Fig.7.
4GsymbolsIs 4-PAM signal is presented in this section. The serial
link was realized by a coaxial cable model that introduced addi- ~

tive white gaussian noise at an SNR of 20dB and was based on the 1.5 level
transmission line model in [ 5 ] . The VCO(KVC0 = 0.4 G H f l ) ,
loopfilter(RI=lOkR,Cl = 10pF,C2= 1 pF1andchargepump
models were derived from [6]. All components of the CDRs being 0.5 level
ideal, behavioral simulations predict only pattem dependent jitter. 0.
The VCO and loop filter components were identical for all three 0.3 0.4 0.5 . 0.7 .
CDRs but the charge pump gain was varied to ensure approxi- l i m e (micro sec.)
mately the same settling time (since the PD gain is different for
Fig. 7. Phase acquisition for SSMMSE CDR (single level).
the three CDRs). The loop bandwidth could have been chosen as

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 Monitored
Levels
Charge Settling Average RMS
Pump Time Phase Jitter
Peak
to
3 In-iu
0, . . .. . ....... ... . ...... ........ . ..... ....... ..... . . .

Gain (in lock) Peak

Jitter
V FA/ sec rad ps ps
rad
Twomid-levels 0.8 0.41 1.13 2.8 10.53
Max &min. levels 0.8 0.36 1.36 1.2 5.3
Madminleveland 0.8 0.39 1.27 1.82 lps
mid level Fig. 9.. Eye diagrams for CPAM data and corresponding full
rate clocks recovered by Linear, Alexander and
maxlmin level SSMMSE P D based CDRs.
Max. & min. levels I 0.53 I 0.39 I 1.31 I 1.24 I 5
and one mid-level 4. CONCLUSIONS
Four levels 1 0.4 I 0.4 I 1.28 I 1.5 I 6 Different CDR techniques for multilevel signals were pre-
sented. Simulation results predict that the linear PD based CDR
Table 4 summarizes simulation results for linear,Alexander
has the lowest jitter and Alexander PD based CDR has the most
and SSMMSE PD based CDRs. The linear and Alexander PD
jitter. Both CDRs require oversampling at twice the baud rate. In
based CDRs align the clock rising edge with the mid-point of the
contrast, the SSMMSE PD based CDR requires only baud rate
horizontal data eye opening while the SSMMSE PD aligns it with
sampling of the received data and hence half the number of clock
the maximum vertical data eye opening (Fig. 8). Since theses two
phases as that of the other two methods. The ultimate choice of
points are not the same in the 4GsymboVs 4-PAM data signal
the CDR method may depend upon the particular channel and
shown in Fig. 9, the SSMMSE clock rising edge is not aligned
with the olher two clock "sing edges (Fig. 9). This also accounts
shape of the received eye.
for the difference in average phase in lock (Table 4).
b horizontal eye opening- -)I REFERENCES
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