Proiectarea flux de date

Instrucţiunea de atribuire concurentă directă de semnal

library ieee;
use ieee.std_logic_1164.all;
entity prime is
port (N: in std_logic_vector (3 downto 0); F: out std_logic);
end prime;
architecture prime2_arch of prime is
signal T1, T2, T3, T4 : STD_LOGIC;
begin
T1 <= not N(3) and N(0) ;
T2 <= not N(3) and not N(2) and N(1) ;
T3 <= not N(2) and N(1) and N(0) ;
T4 <= N(2) and not N(1) and N(0) ;
F <= T1 or T2 or T3 or T4;
end prime2_arch;

Instrucţiunea de atribuire concurentă condiţională de semnal when – else

library ieee;
use ieee.std_logic_1164.all;
entity prime is
port (N: in std_logic_vector (3 downto 0); F: out std_logic);
end prime;
architecture prime3_arch of prime is
signal T1, T2, T3, T4 : STD_LOGIC;
begin
T1 <= '1' when N(3)='0' and N(0)='1' else '0' ;
T2 <= '1' when N(3)='0' and N(2)='0' and N(1)='1' else '0' ;
T3 <= '1' when N(2)='0' and N(1)='1' and N(0)='1' else '0' ;
T4 <= '1' when N(2)='1' and N(1)='0' and N(0)='1' else '0' ;
F <= T1 or T2 or T3 or T4;
end prime3_arch;
Instrucţiunea de atribuire concurentă selectivă de semnal
library ieee;
use ieee.std_logic_1164.all;
entity prime is
port (N: in std_logic_vector (3 downto 0); F: out std_logic);
end prime;
architecture prime4_arch of prime is
begin
with N select
F <= `1` when “0001” | “0010” | “0011”,
`1` when | “0101” | “0111”,
`1` when “1011” | “1101”,
`0` when others;
end prime4_arch;

Proiectare comportamentală (secvenţială)

Atribuirea secvenţială de semnal: nume-semnal <= expresie;
Atribuirea secvenţială de variabilă: nume- variabilă := expresie;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity prime is
port ( N: in STD_LOGIC_VECTOR (3 downto 0);
F: out STD_LOGIC) ;
end prime;
architecture prime5_arch of prime is
begin
process (N)
variable T1, T2,T3,T4 : STD_LOGIC;
begin
T1 := not N(3) and N(0) ;
T2 := not N(3) and not N(2) and N(1) ;
T3 := not N(2) and N(1) and N(0) ;
T4 := N(2) and not N(1) and N(0) ;
 F <= T1 or T2 or T3 or T4;
end process;
end prime5_arch;

Instrucţiunea if
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity prime is
port ( N: in STD_LOGIC_VECTOR (3 downto 0);
F: out STD_LOGIC) ;
end prime;
architecture prime6_arch of prime is
begin
process (N)
variable NI : INTEGER;
begin
NI := to_integer(unsigned (N));
if NI=1 or NI=2 or NI=3 or NI=5 or NI=7 or NI=11 or
NI=13 then F<='1' ;
else F <= '0' ;
end if ;
end process ;
end prime6_arch;

Instrucţiunea case
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity prime is
port ( N: in STD_LOGIC_VECTOR (3 downto 0);
F: out STD_LOGIC) ;
end prime; architecture prime7_arch of prime is
begin
process (N)
begin
case to_integer(unsigned (N)) is
when 1 => F <= '1';
when 2 => F <= '1';
when 3 | 5 | 7 | 11 | 13 => F <= '1' ;
when others => F <= '0' ;
end case ;
end process ;
end prime7_arch;

Instrucţiunile for loop, while loop şi loop

a) For loop
library ieee;
use ieee.std_logic_1164.all;
entity parity10 is
port (D: in std_logic_vector(0 to 9);
ODD: out std_logic);
constant WIDTH: integer := 10;
end parity10;
architecture par of parity10 is
begin
process (D)
variable x: Boolean;
begin
x := false;
for i in 0 to D'length - 1 loop -- se utilizează atributul length
if D(i) = '1' then
x := not x;
end if;
end loop;
if x then
 ODD <= '1';
else
ODD <= '0';
end if;
end process;
end par;

b) While-loop
process
begin
while error_flag /= ‘1’ and done /= '1’ loop
Clock <= not Clock;
wait for CLK_PERIOD/2;
end loop;
end process;
c) Loop
loop -- ciclu infinit, se utilizează cu instr. next sau exit
instrucţiune-secvenţială;
. . .
instrucţiune-secvenţială;
end loop;

Instrucţiunile exit şi next

a) exit
process
begin
loop
Clock <= not Clock;
wait for CLK_PERIOD/2;
if done = '1' or error_flag = '1' then
exit;
end if;
end loop;
end process;
b) next
library ieee;
use ieee.numeric_bit.all;
entity count_ones is port (v: in bit_vector (15 downto 0);
count: out signed (3 downto 0));
end count_ones;
architecture functional of count_ones is
begin
process (v)
variable result: signed (3 downto 0);
begin
result := (others => '0');
for i in v'range loop
next when v(i) = '0';
result := result + 1;
end loop;
count <= result;
end process;
end functional;

Instrucţiunea wait
process
begin
RESET_LOOP: loop
wait until CLOCK’event and CLOCK = ’1’;
next RESET_LOOP when (RESET = ’1’);
X <= A;
wait until CLOCK’event and CLOCK = ’1’;
next RESET_LOOP when (RESET = ’1’);
Y <= B;
end loop RESET_LOOP;
end process;
 Descrierea circuitelor combinaţionale în VHDL
Multiplexor
MUX 2->1
Program VHDL bazat pe flux de date:
library IEEE;
use IEEE.std_logic_1164.all;
entity mux2_1 is
port (s: in std_logic;
D1,D0 : in std_logic;
Q : out std_logic);
end mux2_1;
architecture mux2_1_arch of mux2_1 is begin
Q <= D1 when (s = '1') else D0;
end mux2_1_arch;

MUX 4->1 (8 biti pe linie)

Program VHDL bazat pe flux de date, utilizând
instrucţiunea select
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4in8b is
port(
s: in std_logic_vector (1 downto 0);
D3, D2, D1, D0: in std_logic_vector(1 to 8);
Q: out std_logic_vector(1 to 8) );
end mux4in8b;
architecture mux4in8b_arch of mux4in8b is
begin
with S select Q <=
D0 when "00",
D1 when "01",
D2 when "10",
D3 when "11",
(others => 'U' ) when others; -- creaza un
--vector de 8 biti din `U`, valoare
-- neinitializata
end mux4in8b_arch;

MUX 4->1 (8 biti pe linie)

Program VHDL comportamental
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4in8b is
port( S: in std_logic_vector (1 downto 0);
D3, D2, D1, D0: in std_logic_vector(1 to 8);
Q: out std_logic_vector(1 to 8) );
end mux4in8b;
architecture mux4in8b_arch of mux4in8b is
begin
process (S, D3, D2, D1, D0)
begin
case S is
when "00" => Q <= D0;
when "01" => Q <= D1;
when "10" => Q <= D2;
when "11" => Q <= D3;
when others => Q <= (others =>'U') ;
end case;
end process;
end mux4in8b_arch;

MUX 4->1 (18 biti pe linie)

library IEEE; -- comportamental
use IEEE.std_logic_1164.all;
entity mux4in18 is
port(
S: in std_logic_vector (2 downto 0);
A, B, C, D: in std_logic_vector(1 to 18);
Q: out std_logic_vector(1 to 18) );
end mux4in18;
architecture mux4in18b_arch of mux4in18 is
begin
process (S, A, B, C, D)
-- variable i: INTEGER;
begin
case S is
when "000"|"010" |"100" |"110" => Q <= A;
when "001"|"111" => Q <= B;
when "011" => Q <= C;
-- when "101" => Q <= D;
when others => Q <= (others =>'U');
end case;
end process;
end mux4in18b_arch;

Decodificator
Program VHDL comportamental pentru un decodificator 3→8 cu intrări
active pe 0.
DC 3->8
library IEEE;
use IEEE.std_logic_1164.all;
entity dec3to8 is
port ( S: in std_logic_vector (2 downto 0); --intrari de selectare
EN: in std_logic; -- enable
Y: out std_logic_vector (7 downto 0)); -- iesirile sunt active pe zero
end dec3to8;
architecture dec3to8_arch of dec3to8 is
begin
process (S,EN)
begin
y <= "11111111";
if (en = '1') then
case S is
when "000" => Y(0) <= '0';
when "001" => Y(1) <= '0';
when "010" => Y(2) <= '0';
when "011" => Y(3) <= '0';
when "100" => Y(4) <= '0';
when "101" => Y(5) <= '0';
when "110" => Y(6) <= '0';
when "111" => Y(7) <= '0';
when others => null;
end case;
end if;
end process;
end dec3to8_arch;

Un program VHDL comportamental mai flexibil care nu include tabelul de

adevăr în cod:
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.numeric_std.ALL;
entity dec3to8 is
port ( S: in std_logic_vector (2 downto 0); --intrari de selectare
EN: in std_logic; -- enable
Y: out std_logic_vector (7 downto 0)); -- iesirile sunt active pe zero
end dec3to8;
architecture dec3to8_comp of dec3to8 is
begin
process (S,EN)
variable i : INTEGER range 0 to 7;
begin
Y <= "11111111";
if (EN = '1') then
for i in 0 to 7 loop
if i = to_integer(unsigned(S)) then Y(i) <= '0' ;
end if;
end loop;
end if;
end process;
end dec3to8_comp ;

library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.numeric_std.ALL; entity dec3to8 is
port ( S: in std_logic_vector (2 downto 0); --intrari de selectare
EN: in std_logic; -- enable
Y: out std_logic_vector (7 downto 0)); -- iesirile sunt active pe zero
end dec3to8;
architecture dec3to8_comp of dec3to8 is
begin
process (S,EN)
begin
Y <= "11111111";
if (EN = '1') then
Y(to_integer(unsigned(S))) <= '0';
end if;
end process;
end dec3to8_comp ;

O altă variantă de cod VHDL pentru decodificator, de data aceasta bazat pe

conceptul de flux de date:
library IEEE;
use IEEE.std_logic_1164.all;
entity dec3to8_alt is
port (S: in std_logic_vector(2 downto 0);
En: in std_logic;
Y_L: out std_logic_vector(0 to 7));
end dec3to8_alt;
architecture dec3to8_alt of dec3to8_alt is
signal YI : STD_LOGIC_VECTOR (0 to 7);
begin
with S select YI <=
"01111111" when "000" ,
"10111111" when "001" ,
"11011111" when "010" ,
"11101111" when "011" ,
"11110111" when "100" ,
"11111011" when "101" ,
"11111101" when "110" ,
"11111110" when "111" ,
"11111111" when others;
Y_L <= YI when En ='1' else "11111111";
end dec3to8_alt;

Codificatoare
Program VHDL bazat pe flux de date
CD 8->3
library IEEE;
use IEEE.std_logic_1164.all;
entity CD is port (
X : in std_logic_vector (7 downto 0);
Y : out std_logic_vector (2 downto 0));
end CD;
architecture CD_arch of CD is
begin
Y <=
"000" when X(0)='1' else "001" when X(1)='1' else
"010" when X(2)='1' else
"011" when X(3)='1' else
"100" when X(4)='1' else
"101" when X(5)='1' else
"110" when X(6)='1' else
"111" when X(7)='1' else
"000";
end CD_arch;
construcţia VHDL if-then-else – de prioritate, comportamentala
library IEEE;
use IEEE.std_logic_1164.all;
entity CD_PR is port (
X : in std_logic_vector (7 downto 0);
Y : out std_logic_vector (2 downto 0));
end CD_PR;
architecture CD_PR_arch of CD_PR is
begin
process(X)
begin
Y <= "000";
if X(7)='1' then Y <= "111";
elsif X(6)='1' then Y <= "110";
elsif X(5)='1' then Y <= "101";
elsif X(4)='1' then Y <= "100";
elsif X(3)='1' then Y <= "011";
elsif X(2)='1' then Y <= "010";
elsif X(1)='1' then Y <= "001";
elsif X(0)='1' then Y <= "000";
end if;
end process;
end CD_PR_arch;
 Porti logice
AND2 (Comportamental)
library ieee;
use ieee.std_logic_1164.all;
entity Gate_And2 is
port (x, y: in std_logic;
F: out std_logic);
end Gate_And2;
architecture Gate_And2_beh of Gate_And2 is
begin
process (x, y)
begin
F <= x and y;
end process;
end Gate_And2_beh;

XOR2 (Comportamental)
library ieee;
use ieee.std_logic_1164.all;
entity Gate_XOR2 is
port (x, y: in std_logic;
F: out std_logic);
end Gate_XOR2;
architecture Gate_XOR2_beh of Gate_XOR2 is
begin
process (x, y)
begin
F <= x XOR y;
end process;
end Gate_XOR2_beh;
OR3 (Comportamental)
library ieee;
use ieee.std_logic_1164.all;
entity Gate_OR3 is
port (x, y, z: in std_logic;
F: out std_logic);
end Gate_OR3;
architecture Gate_OR3_beh of Gate_OR3 is
begin
process (x, y, z)
begin
F <= x OR y OR z;
end process;
end Gate_OR3_beh;