UNIT - 1

OPERATIONAL AMPLIFIER FUNDAMENTALS

1.1 Basic operational amplifier circuit-

hT
e basic circuit of an operational amplifier is as shown in above fig. has a differential amplifier input
stage and an emitter follower output. Supply voltages +Vcc and -Vcc are provided. Transistors Q 1 and Q 2
constitute a differential amplifier, which produces a voltage change as the collector of Q2 where a
difference input voltage is applied to the bases of Q 1 and Q 2 . Transistor Q 2 operates as an emitter follower
to provide low output impedance.

Vo = Vcc –VRC –VBE3

= Vcc – IC2 Rc – VBE

Assume that Q 1 and Q 2 are matched transistors that are they have equal VBE levels and equalcurrent
gains.

With both transistor bases at ground level, the emitter currents are equal and both IE1 and IE2 flow
through the common emitter resistor RE.

The emitter current is given by:-

 IE1 + IE2 = VRE/RE

With Q 1 and Q 2 bases grounded,

0 – VBE – VRE + VEE = 0

VEE – VBE = VRE

VRE = VEE – VBE

IE1 + IE2 = –

Vcc = 10 V, VEE = - 10 V, RE = 4.7 K, Rc = 6.8 K, VBE = 0.7,

IE1 + IE2 = (10 – 0.7)/4.7 K + 2 mA

IE1 = IE2 = 1mA

Ic2 = IE2 = 1 mA

Vo = 10 – 1mA x 6.8 K – 0.7

Vo = 2.5 V

If a positive going voltage is applied to the non-inverting input terminal, Q1 base is pulled up by the input
voltage and its emitter terminal tends to follow the input signal. Since Q1 and Q2 emitters are connected
together, the emitter of Q 2 is also pulled up by the positive going signal at the non-inverting input terminal. The
base voltage of Q2 is fixed at ground level, so the positive going movement at its emitter causes a reduction in
its base-emitter voltage (VBE2 ). The result of the reduction in VBE2 is that its emitter current is reduced and
consequently its collector current is reduced.

Positive going input at the base of Q 1 reduces Ic2 by 0.2 mA (from 1mA to 0.8mA)

VO = 10 – (0.8 mA x 6.8 KΩ) – 0.7 = 3.9 V

It is seen that a positive going signal at pin 3 has produced a positive going output voltage

A basic operational amplifier circuit consists of a differential amplifier stage with two input terminals and a
voltage follower output stage. The differential amplifier offers high impedance at both input terminals and it
produces voltage gain. The output stage gives the op-amp low op output impedance. A practical op-amp
circuit is much more complex than the basic circuit.

1.2 OPERATIONAL AMPLIFIER PARAMETERS

INPUT VOLTAGE RANGE
 The circuit is designed to have a VCE of 5V across Q2 and Q4. With a ±10 V supply and the bases of Q1
and Q2 at ground level, the voltage drops across R1 and R4 is 5.7 V and 4.3 V respectively. If the input voltage
at Q1 base goes down to -4 V, the output terminal and Q2 base also goes down to -4 V as the output follows the
input.

This means that the emitter terminals of Q1 and Q2 are pushed down from -0.7 to -4.7 V. Consequently,
the collector of Q4 is pushed down by 4 V, reducing VCE4 from 5 V to 1 V. Although Q4 might still be
operational with a VCE of 1 V, it is close to saturation. It is seen that there is a limit to the negative going input
voltage that can be applied to the op-amp if the circuit is to continue to function correctly.

There is also a limit to positive going input voltages. Where VB1 goes to +4 V, the voltage drop across
resistor R1 must be reduced to something less than 1 V, in order to move VB2 and VE3 up by 4 V to follow the
input. This requires a reduction in Ic2 to a level that makes Q2 approach cutoff. heT input voltage cannot be
allowed to become large enough to drive Q2 into cutoff.

The maximum positive going and negative going input voltage that may be applied to an op-amp is
termed as its input range.

OUTPUT VOLTAGE RANGE

The maximum voltage swing is limited by the input voltage range.

The output voltage can swing in a positive or negative direction depe nds on
the supply voltage and the op-amp output circuitry. Referring to the
hat the
complementary emitter follower output stage in fig., it would appear t

Dept of ECE/SJBIT Page 7

output voltage should be able to rise until Q5 is near saturation and fall until Q6 approaches saturation.

But because of the circuits that control the output stage, is normally not possible to drive the output transistors
close to saturation levels.

A rough approximation for most op-amps is that the maximum output voltage swing is approximately
equal to 1 V less than the supply voltage.

For the 741 op-amp with a supply of ±15 V, the data sheet lists the output voltage swing as typically
±14 V.

COMMON MODE AND SUPPLY REJECTION

Common mode rejection:-

When the same voltage is applied to both the input

terminals of op-amp, the voltage is called ‘Common
Mode Voltage Vin ’, and the op-amp is said to be
operating in the ‘ Common Mode Configuration ‘.
Both input terminals are at the same potential, so
ideally the output should be zero. Because the base
voltages of Q 1 and Q 2 are biased to 1 V above ground,
the voltage drop across emitter resistor RE is increased
by 1 V and consequently, IC1 and IC2 are increased.
The increased level of IC2 produces an increased
voltage drop across RC , which results in a
change in the output voltage at the emitter of Q 3 .

The common mode gain is given by,

The success of the op-amp rejecting common mode inputs is defined in the common mode rejection ratio
(CMRR). This is the ratio of the open loop gain A to the common mode gain Acm.

CMRR = A/A cm

It is expressed in decibel, CMRR = 20 log A/Acm dB. The typical value of 741 is 90 dB.

Significance:

The CMRR expresses the ability of an op-amp to reject a common mode signal. Higher the value of
CMRR, better is its ability to reject a common mode signal. Thus any unwanted signals such as noise or pick-

Dept of ECE/SJBIT Page 8

up would appear as common to both the input terminals and therefore the output due to this signal would be
zero. Hence no undesirable noise signal will be amplified along with the desired signal.

Consider the non-inverting amplifier circuit as shown below, with the input terminal grounded. The
circuit output should also be at ground level. Now, suppose a sine wave signal is picked up at both inputs, this
is a common mode input. The output voltage should tend to be,

Vo cm = Acm x Vi cm

Any output voltage will produce a feedback voltage across resistor Ri, which results in a differential
voltage at the op-amp input terminals. The differential input produces an output which tends to cancel the
output voltage that caused the feedback. The differential input voltage required to cancel Vo cm is,

Vd = = Acm x

Vdis the feedback voltage developed across R1

Vdc= xVocm

= x

x Af

Problem

A 741 op-amp is used in a non-inverting amplifier with a voltage of 50. Calculate the typical output
voltage that would result from a common mode input with a peak level of 100mV.

Solution

Typical value of CMRR for 741 op-amp = 90

dB.

CMRR = antilog = 31623

We have, Vocm= x Af

Dept of ECE/SJBIT Page 9

 = x 50

Therefore, Vocm = 158 µV

POWER SUPPLY VOLTAGE REJECTION:

Any change in –VEE would produce a change in the voltage drop across RE. This would result in an
alteration in IE1 , IE2 and IC2 . The change in IC2 would alter VRC and thus affect the level of the dc output
voltage. The variation in –VEE would have an effect similar to an input voltage.

This can be minimized by replacing the emitter resistor with constant current circuit (or constant current
tail) as shown in fig below.

A constant voltage drop is maintained across resistor RE by providing a constant voltage V at Q 4 base.
Now, any change in supply voltage is developed across the collector-emitter terminal of Q4 and the emitter
currents of Q 1 and Q 2 are not affected. Even with such circuitry, variations in VCC and VEE do produce some
changes at the output. The Power Supply Rejection Ratio (PSRR) is a measure of how effective the op-amp is
in dealing with variations in supply voltage.

A constant voltage drop is maintained across resistor RE by providing a constant voltage V at Q 4 base.
Now, any change in supply voltage is developed across the collector-emitter terminal of Q4 and the emitter
currents of Q 1 and Q 2 are not affected. Even with such circuitry, variations in VCC and VEE do produce some
changes at the output. The Power Supply Rejection Ratio (PSRR) is a measure of how effective the op-amp is
in dealing with variations in supply voltage.

If a variation of 1V in VCC or VEE causes the output to change by 1V, then the supply voltage rejection
ratio is 1V/V. If output changes by 10mV when one of the supply voltages hacnges by 1V, then SVRR is
10mV/V. In 741 op-amps it is 30 mV/V.

Problem

A 741 op-amp uses a ± 15 V supply with 2 mV, 120 Hz ripple voltage superimposed. Calculate the
amplitude of the output voltage produced by the power supply ripple.

Vo (rip) = Vs (rip) x PSRR

= 2mV x 30µV/V

= 60 nV

OFFSET VOLTAGE AND CURRENTS:

Input offset voltage

Dept of ECE/SJBIT Page 10

 Basic operational circuit connected to function as a voltage follower as shown in fig 2. The output
terminal and the inverting terminal follow the voltage at the non-inverting input.

For the output voltage to be exactly equal to the input voltage, transistors Q1 and Q2 must be perfectly
matched. The output voltage can b e calculated as,

Vo = Vi – VBE + VBE2

With VBE1 = VBE → Vo = Vi

If the input voltage is zero then output voltage is also zero. i.e., Vo = Vi.

Suppose that the transistors are not perfectly matched and that VBE1 = 0,7 V while VBE2 = 0.6 V with the
input at ground level,

Vo = 0 – 0.7V + 0.6V = - 0.1V

This unwanted output is known as ‘Output Offset Voltage’. To set Vo to ground level the input would
have to be raised to + 0.1V (i.e. the input voltage applied to reduce the output offset voltage to zero) is known
as ‘Input Offset Voltage’. Although transistors in integrated circuits are very well matched, there is always
some input offset voltage. The typical offset voltage is listed as 1 mV on 741 data sheet (max –5 mV).

Input Offset Current

If the input transistors of an op-amp not being perfectly

matched, as well as the transistor base-emitter voltages
being unequal, the current gain of one transistor may not
be exactly equal to that of the other. Thus, when both
transistors have equal levels of collector current, the base
current may not be equal. So, the algebraic difference
between these input currents (base currents) is referred as
‘Input Offset Current (IOS) ’.

IOS = IB1 – IB2 І

IB1 = Current in the non-inverting input

IB2 = Current in the inverting input

This typical value for 741 op-amps is 20 nA (min) and the max is 200 nA.

Input Bias Current (IB )

Dept of ECE/SJBIT Page 11

 Input bias current is the average of the currents that flow in to the inverting and non-inverting input
terminals of the op-amp.

IB =

Typical value of input bias current IB for 741 op-amps is 80 nA and max is 600 nA.

Offset Nulling

One method of dealing with input offset voltage and

current is as shown in fig below, which shows a low
resistance potentiometer (RP ) connected at the
emitters of Q1 and Q2. Adjustment of RP alters the
total voltage drop from each base to the common
point at the potentiometer moving contact, because
an offset voltage is produced by the input offset
current. This adjustment can null the effects of both
input offset current and input offset voltage.

INPUT AND OUTPUT IMPEDANCE

Input Impedance :

The input impedance offered by any op-amp is substantially

modified by its application. From negative feedback theory, the
impedance at the op-amp input terminal becomes,

Zip = (1 + A ) Zi

Zi = the op-amp input impedance without negative feedback.

A = op-amp open loop gain, typical value for 741 op-amp is 50000

β = Feed back factor

Ri= Input impedance, typical value for 741 op-amp is 0.3 MΩ

Output impedance:

Dept of ECE/SJBIT Page 12

 The typical output resistance specified for the 741 op-amp is 75Ω. Any stray capacitance in parallel
with this is certain to have a much larger resistance than 75Ω. So 75 is also effectively the amplifier output
impedance.

The output impedance of the op-amp is affected by ne gativfeeedback.

Zout =

Zo = op-amp output impedance without negative feedback

Slew Rate

The slew rate (S) of any op-amp is the maximum rate at which the output voltage can change. When the
slew rate is too slow for the input, distortion results. This is illustrated in fig below, which shows a sine wave
input to a voltage follower producing a triangular output waveform. The triangular wave results because the op-
amp output simply cannot fast enough to follow thee sine wave input.

The typical slew rate of the 741 op-amp is 0.5 V/µs. This means that 1µs is required orf output to
change by 0.5 V

Frequency limitations

Fig below shows the graph of open loop gain (A) plotted versus frequency (f) for a 741 op-amp.

f = 100 Hz, A = 80 dB

f = 1 KHz, A = 60 dB

Dept of ECE/SJBIT Page 13

 The open loop gain (A) falls by 20 dB when
the frequency increases from 100 Hz to 1
KHz. The ten times increase in frequency is
termed a decade. So, the rate of the gain is
said to be 20 dB per decade. Where internal
gain equals to or greater than 80 dB is
required for a particular application, it is
available with a 741 only for signal
frequencies up to ≈100 Hz. A greater than 20
dB is possible for signal frequencies up to ≈
90 kHz. Other op-amp maintains substantial
internal gain to much higher frequencies than
the 741.

1.3 OP-AMP AS DC AMPLIFIERS: Biasing op-amps

Bias Current Paths :

Op-amps must be correctly biased if they are to function properly. The inputs of most op-amps are the
base terminals of the transistors in a differential amplifier. Base currents must flow into these terminals for the
transistors to be operational.

One of the two input terminals is usually connected in some way to the op-amp output to facilitate negative
feedback. The other input might be biased directly to ground via a signal source.

From the fig given below, current IB1 flows into the op-amp via the signal source while IB2 flows from
the output terminal. The next fig shows a situation in which resistor R1 is added in series with inverting
terminal to match signal source resistance Rs in series with the non-inverting terminal.

Op-amp input currents produce voltage drops IB1 x Rs and IB2 x R1 across the resistors. Rs and R1
should be selected as equal resistors so that the resistor voltage drops are approximately equal. Any difference
in these voltage drops will have the same effect as an input offset voltage.

Maximum Bias Resistor Values :

If very small resistance values are selected for Rs and R1 in the circuit the voltage drops across them
will be small. On the other hand, if Rs and R1 are very large the voltage drops IB1 x Rs and IB2 x R1 might be
several volts. For good bias stability the maximum voltage drop across these resistors should be less than the
typical forward biased VBE level for the op-amp input transistors.

Usually the resistor voltage drop made at least ten times smaller than VBE.

Dept of ECE/SJBIT Page 14

 IB(max) x R(max) ≈ VBE/10 ≈ 0.07 V

F romhet 741 data sheet IB(max) = 500nA.

Therefore, R(max) ≈ 0.07/500nA ≈ 140 kΩ.

This is a maximum value for the bias resistors for a 741 op-amp. R(max) can be calculated using the
specified IB(max)for the particular op-amp.

R(max) ≈ 0.1 VBE/IB(max)

1.4 Direct – Coupled Voltage Followers

As shown in the figure the resistor R1 is frequently included in

series with the inverting terminal to match the source resistance Rs
in series with the non-inverting terminal.

The input and output impedances of the voltage follower are

Zin = (1+A) Zi and Zou t = Zo \ (1+A)

The voltage follower has very high input impedance and very low output impedance. Therefore, it is
normally used to convert a high impedance source to low output impedance. In this situation it is said to be used
as a ‘buffer’ between the high impedance source and the low impedance load. Thus, it is termed a ‘buffer
amplifier’.

From the fig, a signal voltage is potentially divided across Rsand RL when
connected directly to a load. But when the load and source are joined by
the voltage follower, it presents its very high impedance to the signal
source. Because Zin is normally very much larger than Rs, there is
virtually no loss at this point and effectively all the input appears at the
op-amp input.

The voltage follower output is

And

Dept of ECE/SJBIT Page 15

 The output voltage can be thought of as
being divided across RL and the voltage follower
output impedance Zout . But Zout is much smaller
than any load resistance that might be connected.
So, there is effectively no signal loss and all Vi
appears as Vo at the circuit output.

Example:

1. A voltage follower using a 741 op-amp is connected to a signal source via a 47kΩ. Select a suitable
value for resistor R1. Also calculate the maximum voltage drop across each resistor and the maximum
offset voltage produced by the input offset current.

From a 741 data sheet IB(max) = 500nA and Ii(offset) = 20nA

Problem 2

The voltage follower in the above problem has a 1V signal and a 20kΩ load. Calculate the load voltage

Dept of ECE/SJBIT Page 16

 (a) When the load is directly connected to the source.
(b) When the voltage follower is between the load and the source.

Solution: (a)

(b) For 741 op-amp,

When the voltage follower is used with a potential divider to produce a low impedance dc
voltage source, as in fig (a), load resistor RL is directly connected in series with R1 to derive a
voltage VL from the supply VCC. This simple arrangement has the disadvantage that the VL
varies if the load resistance changes. In fig (b), the presence of the voltage follower maintains
the VL constant regardless of the load resistance.

Dept of ECE/SJBIT Page 17

Example:

A 1 kΩ load resistor is to have 5V developed across it from a 15V source. Design suitable circuits as
shown above circuit fig (a) and (b) and calculate het load voltage variation in each case when the load
resistance varies by -10%. Use a 741 op-amp.

Solution: For circuit in fig. (a)

When RL changes by -10%

For circuit in fig. (b)

For 741

When RL changes by -10%

Voltage Follower compared to an Emitter Follower

Dept of ECE/SJBIT Page 18

  Both voltage follower and the emitter follower are buffer amplifiers.
 The voltage follower has a much higher input impedance and much lower output impedance than
the emitter follower.
 The disadvantage of the emitter follower is the dc voltage loss due to the transistor base-emitter
voltage drop. But the voltage follower dc loss of Vi/A is insignificant.
 There can also be a greater loss of ac signal voltage in the emitter follower than in the voltage
follower because of the lower input impedance and higher output impedance with the emitter
follower.

1.5 Direct coupled non-inverting amplifiers:

The voltage gain of a non-inverting amplifier,

Af = 1 +

As always with a bipolar op-amp, design commences by selecting the potential divider current (I 2 ) very
much larger than the maximum input bias current IB( max).

Because VR2 = Vi (virtual short)

Dept of ECE/SJBIT Page 19

 R2 = Vi/I2

And Vo appears across (R2 + Rf).

So, R2 + Rf = Vo /I2

Finally, to equalize the IBR voltage drops at the op-amp input, R1 is calculated as

R com ≈ R2 ll R3

If R1 is not very much larger than the source resistance,

Rs + Rcom R2 ll R3

Example

Using a 741 op-amp design a non-inverting amplifier to have a voltage gain of approximately 66. The
signal amplitude is to be 15mV.

Solution :

Performance

Dept of ECE/SJBIT Page 20

The input impedance of the op-amp circuit is,1

The impedance seen from the signal source

is,

Since is always much larger than Rcom in

a non-inverting amplifier, the inclusion of R1
normally makes no significant difference.
The output impedance of the op-amp circuit
is,

Problem

Calculate the input impedance of the non-inverting amplifier as shown below . Use the typical
parameters for the LF 353 op-amp.

Solution: For LF 353 A=100000 and

1.6 Direct - Coupled Inverting Amplifier:

Resistor Rcom is included at the non-inverting

terminal to equalize the dc voltage drops due
to the input bias currents approximately equal

Dept of ECE/SJBIT Page 21

resistance should be ‘seen’ when ‘looking out’ from input terminal of the op-amp .

Therefore, Rcom ≈ R1 llRf

And if Rf is not very much larger than the source resistance, then

Rcom ≈ (R1 = Rs) llRf

As with other bipolar op-amp circuits, the resistor current (I1 ) is first selected very much larger than the
maximum input bias current (IB max ).

Since op-amp input terminal does not draw any current so, I1 flows to feedback resistance.

Rf = Vo /I1

Example
Design an inverting amp using a 741 op-amp. The voltage gain is to be 50 and the output voltage
amplitude is to be 2.5 V

Solution:

Performance

Dept of ECE/SJBIT Page 22

The output impedance of the inverting amplifier is determined exactly as for any other op-amp circuit.

1.7 Summing Amplifiers:

Inverting Summing Circuit:

Fig below shows a circuit that amplifies the sum of two or more inputs and since inputs are applied to
the inverting input terminal, hence the amplifier is called ‘Inverting Summing Amplifier’.
Va,Vb and Vc are three inputs applied to the inverting terminal through resistors Ra ,Rb and Rc.
Applying Kirchoff’s law at node V2

Because of Virtual Ground, V2 =0

Dept of ECE/SJBIT Page 23

 Here the output voltage is equal to the average of all the three inputs. Hence this can be used as an
‘Averaging Circuit’.

Non-Inverting Summing Circuit:

Here the three inputs are connected to the non-inverting input through resistors of equal value R. The
voltage V1 is determined using superposition theorem. Let Vb and Vc are grounded and let V1a be at V1
due to Va, corresponding voltage.

Similarly when Va and Vc are grounded, then

When Va and Vb are grounded, then

The output voltage is

Dept of ECE/SJBIT Page 24

Output voltage is equal to the sum of all the three input voltages.
If the gain of the amplifier is 1 I.e. , then the output is,

1.8 Difference Amplifier:

A difference amplifier or a differential amplifier amplifies the difference between two input signals. A
differential amplifier is a combination of inverting and non-inverting configurations. Vy and Vx are two
inputs applied to inverting and non-inverting input terminals respectively. Apply superposition theorem
to determine the output voltage Vo.
When Vx = 0, the configuration becomes an
inverting amplifier and hence the output is
Voy = Vy
When Vy = 0, the configuration is a non-
inverting amplifier. Hence the output is,

The total output voltage is,

Dept of ECE/SJBIT Page 25

When RF and R1 are equal value resistors, the output is the direct difference of the two inputs. By
selecting RF greater than R1 the output can be made an amplified version of the input difference.

Input Resistance

Problems with selecting the difference amplifier resistors as R1 = R2 and RF = R3 is that the two input
resistances are unequal. The input resistance for voltage at inverting terminal is R1 as in the case of an
inverting amplifier. At the op-amp non-inverting input terminal, the input resistance is very high, as it is
for a non-inverting amplifier.

From the output voltage equation it is shown that het same result would be obtained if het ratio RF/R1 is
the same as R3/R2 instead of making RF = R3 and R1 = R2.
Therefore, when the resistance of R1 has been determined, R2 = R3 can be made equal to R1, as long as
the ratio of the resistance is correct. This will give equal input resistances at the two input terminals of
the circuit.

There are two types of differential input resistance and common mode input resistance .

The differential input resistance is the resistance offered to a signal source which is connected directly
across the input terminals. It is the sum of the two input resistances.

The common mode input resistance is the resistance offered to a

signal source which is connected between the ground and both input
terminals, that is, the parallel combination of the two input resistances.

Common Mode Voltage

If the ratio RF/R1 and R3 /R2 are not exactly equal, one input voltage
will be amplified by a greater amount than the other. Also, the
common mode voltage at one input will be amplified by a greater
amount than that at the other input. Consequently, common mode
voltages will not be completely cancelled. One way of minimizing the
common mode input from a difference amplifier is as shown in the fig
below.

R3 is made up of a fixed value resistor and a much smaller adjustable resistor . This allows the ratio
R3 /R2 to be adjusted to closely match RF/R1 in order to null the common mode output voltage to zero.

Dept of ECE/SJBIT Page 26

 Output Level Shifting

R3 is connected to a VB instead of grounding it in the usual way. To understand the effect of V B, assume
that both input voltages are zero. The voltage at the op-amp non-inverting input terminal will be

The voltage at the op-amp inverting input terminal will be ,

V- = V+

The output will be, +

Substituting for V+ and using the resistor relationships ( = ), the output voltage is ,
Vo = VB
Therefore, if VB is adjustable, the dc output voltage level can be shifted as desired.

UNIT – 2

OP-AMPS AS AC AMPLIFERS

2.1 CAPACITOR-COUPLED VOLTAGE FOLLOWER

When a voltage follower is to have its input and output capacitor-coupled, the non-inverting input
terminal must be grounded via a resistor. The resistor is required to pass bias current to the amplifier non-

Dept of ECE/SJBIT Page 27