Subject: Digital Integated Cicuit Design (ECE-312)

Open Ended Experiment

On

C2MOS Latch

Submitted To:-
Dr. Anu Mehra
Department of Electronics And Communication Engineering
Amity School Of Engineering And Technology
Amity University Uttar Pradesh

Submitted By:
Meghna Sinha (A2305118011)
Manisha Samal (A2305118019)
Radhika Raghav (A2305118020)
Shivang Misra (A2305118055)
Hardik Goel (A2305118067)

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 TABLE OF CONTENTS

SL.No. TOPIC PAGE No.

1. AIM 3

2. SOFTWARE USED 3

3. THEORY 3-6

4. PROCEDURE 6-7

5. SCHEMATIC DIAGRAM 7

6. OBSERVATION 8

7. CONCLUSION 8

8. RESULT 8

9. IET OPEN ENDED MARKS DISTRIBUTION 9-10

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 OPEN ENDED EXPERIMENT

AIM: To design and simulate C2MOS Latch.

SOFTWARE USED: Pyxis Schematic (Mentor Graphics)

THEORY:

Latches are level triggered bistable multivibrator with the two outputs set as either high or
low, and one output being the complementary state of the other. A latch has a feedback path,
so information can be retained by the device. Therefore, latches can be memory devices and
store one bit of data for as long as the device is powered. As the name suggests, latches are
used to "latch onto" information and hold in place.

D latches are called Data latches because of their ability to ‘remember data or Delay latchs
because latching and remembering data can be used to create a delay in the progress. D latch
is the simplified version of SR latch. This has a single input D and two outputs Q(t) & Q(t)’.

It is obtained by connecting the same input ‘D’ to both inputs of SR with an additional
inverter before R input to ensure that the S and R inputs cannot both be high or both low at
the same time to avoid the invalid condition. This modification prevents both the
indeterminate and non-allowed states of the SR latch. The operation of D latch is same as
that of SR latch where the inputs of SR latch were taken as S = D and R= D’ in order to
utilize the modified latch for 2 combinations of inputs. Next state of D latch is always equal
to data input for every transition of the clock signal. Hence, D latches always hold the input
information which is available on data input.

Q(t+1) = D

D Q (t+1)

0 0

1 1

Table 1 Truth Table for D Latch Figure 1 Timing diagram of D latch

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Circuit Description

The core of the circuit is the C2MOS latch to build an ingenious dynamic register, based on
the master slave concepts. C2MOS Logic combines the static logic design with the
synchronization by employing a clock signals, this logic used to decrease complexity, to
increase speed, and a lower dissipation of power. The fundamental idea behind dynamic logic
is to use the capacitive entry of transistor MOSFET to store a load and remember thus logical
level to use it later.

A C2MOS circuit is a combination of the pull-up network (PUN) and the pull-down network
(PDN). The function of the PUN is to provide a connection between the output and VDD and
the PDN connects the output to ground. The PDN is constructed using NMOS devices, while
PMOS transistors are used in the PUN.

In master stage, clock signal, CLK, is provided to pull up network (to transistor M4) and its
complement, CLK’, to pull down network (to transistor M4). Input D is connected to
transistor M2 in pull up network and transistor M1 in pull down network. Transistor M2 in
pull up network is connected to external voltage VDD and Transistor M1 in pull down
network is connected to ground. Output of master stage makes the input of slave stage.

In slave stage, in contrast to master stage, CLK is provided to pull down network (to
transistor M7) and CLK’ to pull up network (to transistor M8). Transistor M6 in pull up
network is connected to external voltage VDD and Transistor M5 in pull down network is
connected to ground.

Figure 2 C2MOS master-slave positive edge- triggered latch

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Working-

Since both master and slave stages are inverters, when cascaded together they produce output
similar to input state.

For CLK=0 and CLK’=1, transistors M4 and M3 are on and transistors M8 and M7 are off
and the master stage acts as an inverter.

For D=0, M2 is on and M1 is off. There is a break in pull down network but pull up
network is on and VDD gets a direct path to node X which stores a 1. Due to this logic
1, M6 turns off and M5 is on. Since both M8 and M7 are off, neither VDD nor ground
gets a path to output Q, and the slave stage is in hold state.

For D=1, M2 is off and M1 is on. There is a break in pull up network but pull-down
network is on and ground gets a direct path to node X which stores a 0. Due to this
logic 0, M6 turns on and M5 is off. Since both M8 and M7 are off, neither VDD nor
ground gets a path to output Q, and the slave stage is in hold state.

For CLK= 1 and CLK’= 0, transistors M4 and M3 are off and transistors M8 and M7 are on
and the slave stage acts as an inverter.

For D=0, M2 is on and M1 is off. Since both M4 and M3 are off, neither VDD nor ground
gets a path to node X, and the master stage is in hold state. Output of master stage stored
at X when CLK=0 and CLK’=1 is taken to be the input of slave stage, which was 1.
This logic 1 turns off M6 and turns on M5. There is a break in pull up network but
pull-down network is on and ground gets a direct path to output Q which stores a 0.

For D=1, M2 is off and M1 is on. Since both M4 and M3 are off, neither VDD nor ground
gets a path to node X, and the master stage is in hold state. Output of master stage stored
at X when CLK=0 and CLK’=1 is taken to be the input of slave stage, which was 0. This
logic 0 turns off M5 and turns on M6. There is a break in pull down network but pull up
network is on and VDD gets a direct path to output Q which stores a 1.

Clock 0 1
Master stage Evaluate stage- acts as High impedance: Hold ‘Z’
inverter X retains value at CL1
D’ stored as X
Slave stage High impedance: Hold ‘Z’ Evaluate stage- acts as
Q retains value at CL2 inverter
CL1 propagates to Q
Output Previous value stored in CL2 New value of CL1

Table 2- Working of C2MOS latch

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 Overlap Conditions-

A C2MOS register with CLK-CLK’ clocking is insensitive to overlap, as long as the rise and
fall times of the clock edges are sufficiently small.

In the 0-0 overlap case, pull up transistors M4 and M8 are on and pull-down transistors M3
and M7 are off. For D = 0, M2 is on and M1 is off. VDD gets a path to node X which stores a
1. This 1 turns off M6 and turns on M5. The pull-down network is off due to clock signal and
pull up due to logic 1 at X. Neither VDD nor ground gets a path to output Q. For D = 1, M2 is
off and M1 is on. Neither VDD nor ground gets a path to node X. In both cases, circuit does
not work, and 0-0 overlap is avoided.

In the (1-1) overlap case, both NMOS devices M3 and M7 are turned on and PMOS devices
M4 and M8 are off. For D = 0, M2 is on and M1 is off. Since M4 is also off, neither VDD nor
ground gets a path to node X. For D = 1, M2 is off and M1 is on. Ground gets a path to node
X which stores a 0. This 0 turns on M6 and turns off M5. The pull-down network is off due to
logic 0 at X and pull up due to clock signal. Neither VDD nor ground gets a path to output Q.
In both cases, circuit doesn’t work and 1-1 overlap is avoided.

As the circuit consists of a cascade of inverters, signal propagation requires one pull-up
followed by a pull-down, or vice-versa, which is not feasible in the situation presented.

Figure 3. C2MOS D latch during overlap periods.

PROCEDURE:

1. Open Xmanager icon which is on dektop.

→
2. Open Xstart a new window will appear, then click on run tab. After that, a terminal window will
appear.
3. Write the following commands in terminal as:
→
mkdir directory name (Rad) Enter
→
cd test Enter
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 →
csh Enter
source /home/software/cshrc/tanner_18.cshrc
→ Enter da_ic →
Enter
4. Click on new schematic and then click on new directory.
5. From device library, select N- Mos, P-Mos and ideal capacitor and connect them.
6. From generic library, select VDD, ground, port-in and port-out and connect it.
7. From source library, select DC voltage and connect it.
8. Select DC voltage and set DC value to 4V.
9. Select pulse and set delay equal to 0 and pulse equal to VDD.
10. Set period of D = 200, width =100 and period of Clk= 300, width = 200.
11. Change N-Mos to ‘N’ and P-Mos to ‘P’.
12. Change names of NET as ‘D’, ‘clk’, ‘clk bar’ and ‘Q’.
13. Check and save, check log window for errors, if any.
14. Enter Simulation mode, click on Lib/temp/ Includes
15. Browse the folder: home/Software/Foundary/adk3_0/technology/ic/models/tsmc 035.mod,
then press OK.
16. Go to Analysis, select tran, select start time 0 and stop time = 500nS then apply.
17. Click on outputs on pallate area and select inputs and outputs.
18. Go to Analysis- tran, Task- Plot, Type-Voltage, then add and apply.
19. Click on Run Eldo for successful simulation.
20. Click on View Waves for output wave.

SCHEMATIC DIAGRAM:

Figure 4 Schematic Diagram of C2MOS based Latch (using 10 Transistors)

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OBSERVATION:

Figure 5 Output waveform of C2MOS based Latch

CONCLUSION:

It can be concluded that the C2MOS latch is insensitive to clock overlaps because those
overlaps activate either the pull-up or the pull-down networks of the latches, but never both
of them simultaneously. If the rise and fall times of the clock are sufficiently slow, however,
there exists a time slot where both the NMOS and PMOS transistors are conducting. This
creates a path between input and output that can destroy the state of the circuit. The circuit
operates correctly as long as the clock rise time (or fall time) is smaller than approximately
five times the propagation delay of the register. This criterion is not too stringent and is easily
met in practical designs.

RESULT:

Design and simulation of C2MOS Latch is done successfully using Mentor Graphics.

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 IET OPEN-ENDED MARKS DISTRIBUTION

1. Meghna Sinha
Criteria Total Marks Marks Obtained Comments
Designing Concept (D) 3
Application of Knowledge (E) 2
Performance(F) 3
Result (G) 2
Total 10

2. Manisha Samal
Criteria Total Marks Marks Obtained Comments
Designing Concept (D) 3
Application of Knowledge (E) 2
Performance(F) 3
Result (G) 2
Total 10

3. Radhika Raghav
Criteria Total Marks Marks Obtained Comments
Designing Concept (D) 3
Application of Knowledge (E) 2
Performance(F) 3
Result (G) 2
Total 10

4. Shivang Misra
Criteria Total Marks Marks Obtained Comments
Designing Concept (D) 3
Application of Knowledge (E) 2
Performance(F) 3
Result (G) 2
Total 10

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5. Hardik Goel
Criteria Total Marks Marks Obtained Comments
Designing Concept (D) 3
Application of Knowledge (E) 2
Performance(F) 3
Result (G) 2
Total 10

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