Lab 2 - Flip Flops and Counters

HCMC UNIVERSITY OF TECHNOLOGY AND EDUCATION
FACULTY FOR HIGH QUALITY TRAINING

INDUSTRIAL ELECTRONICS - BIOMEDICAL ENGINEERING DEPARTMENT
DIGITAL SYSTEM IN PRACTICE
Lab 2
FLIP FLOPS & COUNTERS

Instructor: NGUYEN THANH NGHIA
Date: ....................................................................
Student’s Name: ..................................................
ID: .......................................................................
I/ OBJECTIVES
Upon completion of this experiment, you are able to know:
 The operation of flip-flops.
 How to convert a flip-flop into other flip-flop.
 The operation of 7-segment LED, decoder IC and how to design counters
using flip-flops.
II/ COMPONENTS REQUIRED

1. Main board and sub board of Digital Logic Systems (DLS) Kit
2. Materials.
III/ CONTENTS
1. Flip Flops
a. The operation of JK – FF.
b. The operation of D – FF.
c. Convert JK-FF into D-FF.
2. Design asynchronous counters
a. Implement an asynchronous 3-bit up counter having M = 8 by using IC
74LS112
b. Implement an asynchronous 3-bit up counter having M = 5 by using IC
74LS112
c. Implement an asynchronous 3-bit down counter having M =8 by using IC
74LS112.
d. Implement an asynchronous 3-bit up counter having M=8, with a control
input for up/down counting using 74LS112 and 74LS86
3. Synchronous counters
a. Analyze and implement a synchronous counter
b. Design and implement a synchronous 2-bit counter M = 3
IV/ PRE-LAB
The student must complete the questions in this section and read the book before
going to the class.
- Pre-lab includes reading the lab assignment in advance, answering the
questions or doing the calculations, and if necessary reviewing the material in the
textbook. All pre-lab preparation must be recorded and dated in the pre-lab sheet
prior doing the lab. The lab instructor will check your pre-lab write-up and sign
your pre-lab sheet.
- Answering all the questions and comments, draw the waveforms and
circuits, fulfill the truth tables and present diagrams on this experiment before doing
the lab.
- If you don’t prepare the pre-lab, you will not be allowed to do experiment.
Lab 2 - FLIP FLOPS AND COUNTERS.doc
Page | 2
1. Flip Flop RS(NAND): Symbol: truth-table Boolean function
2. Flip Flop JK: Symbol: truth-table Boolean function
3. Flip Flop D: Symbol: truth-table Boolean function
4. Flip Flop T: Symbol: truth-table Boolean function

Page | 3
V/ EXPERIMENT
1. R’S’ FLIP FLOPS
a. R’S’-FF using NAND gate
Figure 2.1. The R’S’-FF using NAND gate

 Implement the circuit shown in figure 2.1
 Toggle switch of SW1 and SW2 to change input logic level and write down
the result to table 2.1
Table 2.1: The truth-table of the FF R’S’ using NAND gate

S’ (SW1) R’ (SW2) Q LED1 Q\ LED2
0 0 1 1
0 1 1 0
1 0 0 1
1 1 0;1 1;0
b. RS-FF using NOR gate
Figure 2.2. The R’S’-FF using NAND gate


Page | 4
 Toggle switch of SW1 and SW2 to change input logic level and write down
the result to table 2.2
Table 2.2: The truth-table of the FF RS using NOR gate
S’ (SW1) R’ (SW2) Q LED1 Q\ LED2
0 0 0;1 1;0
0 1 1 0
1 0 0 1
1 1 0 0
2. JK FLIP FLOPS (74LS112)

a. The datasheet of 74LS112
 Look up the datasheet of 74LS112 to know the pin connections, truth table,
functions and parameters of IC. The summary of the pin connections, logic
diagram and truth table shown as follows:
Figure 2.3. The pin connections and IEC logic symbol of Flip Flop 74LS112
The function table of the JK Flip Flop is shown as table 2.3.
Table 2.3: The truth-table (function table) of the 74LS112

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The pin descriptions of the JK Flip Flop are shown as table 2.4.
Table 2.4: The pin descriptions of the 74LS112
Write down the answer of the following questions:

How many Flip Flop in the 74LS112?
What is the Toggle state?
VCC pin? GND pin?
Is the rising edge clock or falling edge clock?
b. The schematics of 74LS112 in the Digital Logic Systems kit
There are two 74LS112 on the DLS kit. The schematic and name of ICs on the DLS
kit is shown as figure 2.4
Figure 2.4. The schematics and output name of Flip Flop 74LS112
Page | 6
 The name of two ICs is IC8 and IC9 which the power supply is connected.
 The PRE input and CLR input are connected to power through a 4,7 kΩ
resistor. It means that, when we don’t use, the PRE input and CLR input are
high.
 Because of the time response of the FFs is different, the output Q of four FF
is wired to four 1nF capacitor for delay when we implement the feedback
function of the counter circuit mod M.
 The schematic and location of two ICs on DLS kit is shown in figure 2.5.
Figure 2.5. The Flip Flop 74LS112 on DLS kit and name of input and output
c. Checking the Flip Flop
Figure 2.6. The schematics for checking the Flip Flop 74LS112.

Page | 7
 Toggle switch of SW0, SW1, SW2 and SW3 to change input logic level
following the truth-table and observe the output state (LED 0 and LED 1).
Compare the output state of FF with the truth-table in datasheet. If the output
is the same, the FF is good.
Tick “×” if the logic gate is damage, tick “√” if the logic gate is good.
Table 2.5: Determine the status of 74LS112
ICs No. IC8A IC8B IC9A IC9B
Good/Damage (“√/×”)
3. ANALYSE AND DESIGN ASYNCHRONOUS COUNTERS

a. The 2-bit up counter
Figure 2.7. The 2-bit asynchronous up counter using 74LS112
 On the input, the symbol “1” is connected to +5V or Vcc.

 Observe and write down the result to table 2.6.
Table 2.6: The 2-bit asynchronous up counter
CP1 LED1 LED0 Decimal
0 0 0 0
1 0 0 1
2 0
1 2
3 1
1 3
4 0 0 0

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b. The 2-bit down counter

Figure 2.8. The 2-bit asynchronous down counter using 74LS112

Table 2.7: The 2-bit asynchronous down counter
0 0 0 0
1 1 1 3
2 1 0 2
3 0 1
1
4 0 0 0
c. The 4-bit up counter

Figure 2.9. The 4-bit asynchronous up counter using 74LS112

Page | 9

Table 2.8: The output status of 4-bit up counter
CP1 Led3 Led2 Led1 Led0

0 0 0 0 0
1 0 0 1
0
2 0 0 1 0
3 0 0 1
1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1
1
12 1 1 0 0
13 0 1
1 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0
d. The 4-bit down counter

 Implement the circuit in figure 2.10.

Page | 10
Figure 2.10. The 4-bit asynchronous down counter using 74LS112

Table 2.9: The output status of 4-bit down counter

0 0 0 0 0
1 1 1 1 1
2 1 1 1 0
3 1 1 0 1
4 1 1 0 0
5 1 0 1 1
6 1 0 1 0
7 1 0 0 1
8 1 0 0 0
9 0 1 1 1
10 0 1 1 0
11 0 1 0 1
12 0 0 0
1
13 0 1 1
0
14 0 0 1 0
15 0 0 0 1
16 0 0 0 0

Page | 11
e. The asynchronous up counter having mod M = 10

Figure 2.11. The asynchronous up counter having mod M = 10
 Press the “RSTL” button and observe the clock CP1 and the output signal in
four led.
 Write down the output signal in four led into the table 2.10
Table 2.10: The output status of up counter having mod M = 10

0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 0 0 0 0

Page | 12
f. The asynchronous down counter from 15 down to 5
Table 2.11: The output status of asynchronous down counter from 15

down to 5
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 0 0
1 1
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 1 1
0 1
9 0 1 1 0
10 0 1 0 1
11 1 1 1 1
12 1 1 1 0
13 1 1 0 1
14 1 1 0 0
15 1 0 1 1
16 1 0 1 0

four led.
 Write down the output signal in four led into the table 2.11

Page | 13
Figure 2.12. The asynchronous down counter from 15 down to 5
g. Design an asynchronous up counter having M = 6 by using IC 74LS112
 Show the way to make it (step by step)
 Implement the circuit and observe the results.
Figure 6 - Logic diagram asynchronous up counter having M=6

Page | 14
4. ANALYSE AND DESIGN SYNCHRONOUS COUNTERS

a. The 2-bit up counter
Figure 2.13. The 2-bit synchronous up counter using 74LS112

two led.
 Write down the result to table 2.12.
Table 2.12: The 2-bit synchronous up counter
0 0 0 0
1 0 1 1
2 0 2
1
3 1 1 3
4 0 0
0
 Explain the operation of circuit.

Page | 15
b. The 2-bit down counter

Figure 2.14. The two bit synchronous down counter using 74LS112

two led.
 Write down the result to table 2.13.
Table 2.13: The 2-bit synchronous down counter
0 0 0 0
1 1 3
1
2 1
0 2
3 0 1 1
4 0 0 0
 Explain the operation of circuit.

Page | 16
c. The 4-bit up counter

Table 2.14: The output status of 4-bit up counter

0 0 0 0 0
1 0 0 1
0
2 0 0 0
1
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 1 1 1
0
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0


Page | 17
Figure 2.15. The 4-bit synchronous up counter using 74LS112
d. The 4-bit down counter

Table 2.15: The output status of 4-bit down counter

0 0 0 0
0
1 1 1 1 1
2 1 1 1 0
3 1 1 0 1
4 1 1 0 0
5 1 0 1 1
6 1 0 1 0
7 1 0 0 1
8 1 0 0 0
9 0 1 1 1
10 0 1 1 0
11 0 1 0 1
12 0 1 0 0
13 0 0 1 1
14 0 0 0
1
15 0 0 0 1
16 0 0 0 0

Page | 18

Figure 2.16. The 4-bit synchronous down counter using 74LS112
5. D FLIP FLOPS (74LS74)

a. The datasheet of 74LS74
 Look up the datasheet of 74LS74 to know the pin connections, truth table,
functions and parameters of IC. The summary of the pin connections, logic
diagram and truth table shown as follows:
Figure 2.17. The pin connections and IEC logic symbol of Flip Flop 74LS74
The function table of the JK Flip Flop is shown as table 2.3.
Table 2.16: The truth-table (function table) of the 74LS74
Write down the answer of the following questions:

How many Flip Flop in the 74LS74?
What is the Toggle state?
VCC pin? GND pin?
Is the rising edge clock or falling edge clock?
Page | 19
d. The schematics of 74LS74 in the Digital Logic Systems kit

There are two 74LS74 on the DLS kit. The schematic and name of ICs on the DLS
kit is shown as figure 2.18
Figure 2.18. The schematics and output name of Flip Flop 74LS74
 The name of two ICs is IC8 and IC9 which the power supply is connected.
 The PRE input and CLR input are connected to power through a 4,7 kΩ
resistor. It means that, when we don’t use, the PRE input and CLR input are
high.
 The schematic and location of two ICs on DLS kit is shown in figure 2.19.
Figure 2.19. The Flip Flop 74LS74 on DLS kit and name of input and output

Page | 20
e. Checking the Flip Flop

Figure 2.20. The schematics for checking the Flip Flop 74LS74.
 Toggle switch of SW0, SW1, SW2 and SW3 to change input logic level
following the truth-table and observe the output state (LED 0 and LED 1).
Compare the output state of FF with the truth-table in datasheet. If the output
is the same, the FF is good.
Tick “×” if the logic gate is damage, tick “√” if the logic gate is good.
Table 2.17: Determine the status of 74LS112
ICs No. IC10A IC10B IC11A IC11B
Good/Damage (“√/×”)
6. SHIFT REGISTER DESIGN
a. The 4-bit shift register

Figure 2.21. The 4-bit shift register using 74LS74.

Page | 21
 Toggle switch of SW1 = ‘1’ (the input D corresponding the logic high,
LED8 is on), press the “RSTL” button and observe clock CP1 and LED0,
LED1, LED2, LED3 until all LED is on.
 Write down the result into the table 2.18.
Table 2.18: The 4-bit shift register – input is high

Input Output
CP 1 D Led3 Led 2 Led 1 Led 0
1 0 0 0 0
0
1 1 0 0 0 1
1 0 0 1 1
2
3 1 0 1 1 1
1 1 1 1 1
4
5 1 1 1 1 1
1 1 1 1
6 1
1 1 1 1 1
7
 Toggle switch of SW1 = ‘0’ (the input D corresponding the logic low, LED8
is on), observe clock CP1 and LED0, to LED3 until all LED is off.
 Write down the result to the table 2.19.
Table 2.19: The 4-bit shift register – input is high
Input Output
0 0 1 1 1
1
0 1 1 1 0
1
0 1 0
2 1 0
3 0 1 0 0 0
4 0 0 0 0 0
5 0 0 0
0 0
0 0
6 0 0 0
0 0 0
7 0 0

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b. The 4-bit Johnson ring counter

Figure 2.22. The 4-bit Johnson ring counter using 74LS74.
 Press the “RSTL” button and observe clock and output signal.
Table 2.20: The 4-bit Johnson ring counter

Input Output
0 1 0 0 0 0
0
1 1 0 0 1
1 0 0 1 1
2
1 0 1 1 1
3
0 1 1 1 1
4
0 1 1 1 0
5
1 1 0
6 0 0
0 1 0 0 0
7
 Explain the operation of the 4-bit Johnson ring counter.

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c. The 4-bit ring counter

Figure 2.23. The 4-bit Johnson ring counter using 74LS74.
 Press the “RSTL” button and observe clock and output signal.
Table 2.21: The 4-bit Johnson ring counter

Input Output
0 0 0 0 0 1
1 0 0 0 1 0
2 0 0 1 0 0
3 1 1 0 0 0
4 0 0 0 1
0
5 0 0 0 1 0
6 0 0 1 0 0
7 1 1 0 0 0
 Explain the operation of the 4-bit ring counter.

Page | 24
7. CONVERT FLIP FLOP SCHEMATICS
a. Convert D-FF into T-FF
Figure 2.24. Create T-FF from D-FF 74LS74.
 Toggle switch of SW1 = ‘1’ and SW1 = ‘0’, observe the clock CP1 and
LED0.
Table 2.22: The truth table of T-FF
Inputs Output
CP1 SW1 = T Led0 - Q
↑ 0 0
↑ 1 0
b. Convert JK-FF into D-FF
Figure 2.25. Convert JK-FF into D-FF.

Page | 25
 From the block diagram shown in figure 2.25, design the circuit to convert
JK-FF to D-FF:
The way to convert
 Implement the circuit to verify the operation of the new FF (fulfill the true
table in Table 2.23).
 Draw the circuit appropriately in figure 2.26.
Table 2.23: True table of

the new FF
D Q Q+
0 0
1 0
0 1
1 1
Figure 2.26 - Logic diagram convert JK-FF into D-FF
c. The 2-bit asynchronous up counter using D-FF
Figure 2.27. The 2-bit asynchronous counter using 74LS74.
 Observe the clock CP1 and LED0 and LED1.
 Write down the results to the table 2.24.

Page | 26
Table 2.24: True table 2-bit asynchronous

counter using 74LS74
Inputs Output
CP1 Led1 – Q1 Led0 – Q0
↑ 0 0
↑ 0 1
↑ 1 0
↑ 1 1
d. The ON-OFF control using JK-FF
Figure 2.28. The ON-OFF control using 74LS112.
 Observe the signal on LED1 (Q) and LED2 when the button MONO1
was pressed at the first times, second times, third times.
 This circuit can use to enable/disable the clock CP1 by AND gate. The
blink frequency of LED3 equal to the clock CP1.
 When the output is Q = 1, the LED1 is ON and the clock CP1 is pass
through AND gate. The LED2 blink the same with LED3.
 When the output is Q = 0, the LED1 is OFF and the clock CP1 is
disabled by AND gate. The LED2 is OFF.
 By using the MONO clock, we can enable/disable the clock CP1 by
AND gate.
 This circuit can use to control the start and pause the counter circuit.

Page | 27

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HCMC UNIVERSITY OF TECHNOLOGY AND EDUCATION

FACULTY FOR HIGH QUALITY TRAINING

DIGITAL SYSTEM IN PRACTICE

FLIP FLOPS & COUNTERS

HCMC UNIVERSITY OF TECHNOLOGY AND EDUCATION

Instructor: NGUYEN THANH NGHIA

II/ COMPONENTS REQUIRED

1. Flip Flop RS(NAND): Symbol: truth-table Boolean function

2. Flip Flop JK: Symbol: truth-table Boolean function

3. Flip Flop D: Symbol: truth-table Boolean function

4. Flip Flop T: Symbol: truth-table Boolean function

Lab 2 - FLIP FLOPS AND COUNTERS.doc

Figure 2.1. The R’S’-FF using NAND gate

Table 2.1: The truth-table of the FF R’S’ using NAND gate

b. RS-FF using NOR gate

Figure 2.2. The R’S’-FF using NAND gate

Lab 2 - FLIP FLOPS AND COUNTERS.doc

S’ (SW1) R’ (SW2) Q LED1 Q\ LED2

2. JK FLIP FLOPS (74LS112)

Lab 2 - FLIP FLOPS AND COUNTERS.doc

Write down the answer of the following questions:

Lab 2 - FLIP FLOPS AND COUNTERS.doc

3. ANALYSE AND DESIGN ASYNCHRONOUS COUNTERS

Figure 2.7. The 2-bit asynchronous up counter using 74LS112

 On the input, the symbol “1” is connected to +5V or Vcc.

Lab 2 - FLIP FLOPS AND COUNTERS.doc

b. The 2-bit down counter

Figure 2.8. The 2-bit asynchronous down counter using 74LS112

 On the input, the symbol “1” is connected to +5V or Vcc.

c. The 4-bit up counter

Figure 2.9. The 4-bit asynchronous up counter using 74LS112

Lab 2 - FLIP FLOPS AND COUNTERS.doc

 On the input, the symbol “1” is connected to +5V or Vcc.

CP1 Led3 Led2 Led1 Led0

d. The 4-bit down counter

Lab 2 - FLIP FLOPS AND COUNTERS.doc

Figure 2.10. The 4-bit asynchronous down counter using 74LS112

CP1 Led3 Led2 Led1 Led0

Lab 2 - FLIP FLOPS AND COUNTERS.doc

e. The asynchronous up counter having mod M = 10

Figure 2.11. The asynchronous up counter having mod M = 10

CP1 Led3 Led2 Led1 Led0

Lab 2 - FLIP FLOPS AND COUNTERS.doc

f. The asynchronous down counter from 15 down to 5

Table 2.11: The output status of asynchronous down counter from 15

 Implement the circuit in figure 2.12.

Lab 2 - FLIP FLOPS AND COUNTERS.doc

Figure 2.12. The asynchronous down counter from 15 down to 5

g. Design an asynchronous up counter having M = 6 by using IC 74LS112

 Show the way to make it (step by step)

 Implement the circuit and observe the results.

Figure 6 - Logic diagram asynchronous up counter having M=6

4. ANALYSE AND DESIGN SYNCHRONOUS COUNTERS

Figure 2.13. The 2-bit synchronous up counter using 74LS112

 On the input, the symbol “1” is connected to +5V or Vcc.

 Explain the operation of circuit.

Lab 2 - FLIP FLOPS AND COUNTERS.doc

b. The 2-bit down counter

 On the input, the symbol “1” is connected to +5V or Vcc.

CP1 LED1 LED0 Decimal