460 FUNDAM ENTALS OF DIGITAL CIRCUIT S

Figure 10.1 shows a block diagram of a sequential circuit. The memor y elemen ts are connec
ted
to the combinational circuit as a feedback path.

Inputs Outputs
Combinational ,_'$0,

circuit

Memory
~

elements

Figure 10.1 Block diagram of a sequential circuit.

The information stored in the memory element at any given time defines th~lres ent state
of
the sequential circuit. The present state and the external inputs detenn ine the outputs and
the next
state of the· sequential circuit. Thus, we can specify the sequential circuit by a time sequen
ce of
external inputs, internal states (present state and next state) and outputs. Table 10.1 present
s the
comparison between combinational and sequential circuits.

Table 10.1 Comparison between combinational and sequential circuits

Combinational circuits Sequential circuits

1. In combinational circuits, the output variables 1. In sequential circuits, the output variables at
at any instant of time are dependent only on any instant of time are dependent not only on
the present input variables. the present input variables, but also on the
present state, i.e. on the past history of the
system.
2., Memory unit is not required in combinational 2. Memory unit is required to store the past history
circuits . of the input variables in sequential circuits.
3. Combinational circuits are faster because the 3. Sequen tial circuit s are slower than
delay between the input and the output is due combinational circuits .
to propagation delay of gates only.
4. Combinational circuits are easy to design. 4. Sequential circuits are comparatively harder ·
to design.

10.2 CLASSiFICATION OF SEQUENTIAL CIRCUITS

The sequential circuits may be classified as synchronous sequential circuits and asynchr
onous
sequential circuits depending on the timing of their signals. The sequential circuits which
are
controlled by a clock are called synchronous sequ~ntial circuits . These circuits will be active
only
when clock signal is present. The sequential circuits which are not controlled by a clock
are called
asynchronous sequential circuits, i.e. the sequential circuits in which events can take
place any
time the inputs are applied are called asynchronous sequential circuits. Periodically,
recurring
pulse is called a clock. It is generated by a pulse generator. In sequential circuits the
desired
operations take place only when the clock pulse occurs, as they are enabled using AND
gates
where ver needed. All flow of information occurs only when the clock pulse occurs. Table
10.2
shows the compari son between synchronous and asynchronous sequential circuits.
 FLIP-FLOPS 461

Table 10.2 Comparison between synchronous and asynchronous sequential circuits

- - Synchronous sequential circuits . Asynchronous sequential circuits

1.
In synchronous circuits, memory elements are 1. In asynchronous circuits, memory elements are
clocked FFs. either unclocked FFs or time delay elements.
circuits, the change in input 2. In asynchronous circuits, change in input
2. In synchronous
signals can affect memory elements upon signals can affect memory elements at any
activation of clock signal. instant of time.
3. The maximum operating speed of the clock 3. Because of the absence of the clock,
depends on time delays involved. asynchronous circuits can operate faster than
synchronous circuits.
4. Easier to design. 4. More difficult to design.

10.3 LEVEL MODE AND PULSE MODE ASYNCHRONOUS SEQUE NTIAL

CIRCUITS

Figure 10.2 shows a block diagram of an asynchronous sequential circuit. It consists of a

combinational circuit and delay elements connected to form the feedback loops. There are n input
variables, m output variables and k internal states. The delay elements provide a short-term memory
for the sequential circuit. The present state and next state variables in asynchronous sequential
circuits are called secondary variables and excitation variables respectively.

. • Z1
X1 .
n input
variables
X2
.. -
.

..
• Z2
m output
variables
.
Xn - • Zm
Combinational
circuit
Vi Y1
k excitation
kseconda ry Y2
variables
(present state)
Y2
.. - . variables
(next state)

Yk·:-+ _·Yk

I Delay
I_
I I

...
I
I
Delay ,~
I_

I Delay
I
I 1-

Figure 10.2 Block diagram of an asynchronous sequential circuit.

When an input variable changes in value, the secondary va~ables, _i.e. Yp y2, ... , yk do not
change instantaneously. Certain amount of time is required for the mput signal to propagate from
 FLIP-FLOPS 463

- Q ~ (Normal output)
-
Inputs
.. FF

-
a (Inverted output)

Figure 10.3 General flip-flop symbol.

As the symbol in Figure 10.3 implies, a flip-flop can have one or more inputs. The input
signals which command the flip-flop to change state are called excitations. These inputs are used
to cause the flip-flop to switch back and forth (i.e. 'flip-flop') between its possible output states. A
flip-flop input has to be pulsed momentarily to cause a change in the flip-flop output, and the
output will remain in that new state even after the input pulse has been removed. This is the
flip-flop's memory characteristic.
There are a number of applica.tions of flip-flops. As such, the flip-flop serves as a storage
device. It stores a I when its Q output is a I, and stores a Owhen its Q output is a 0. Flip-flops are
the fundamental components of shift registers and counters.
The term 'latch' is used for certain flip-flops. It refers to non-clocked flip-flops, because
these flip-flops 'latch on' to a I or a O immediately upon receiving the input pulse called SET or
RESET. They are not dependent on the clock signal for their operation, i.e. a latch is a sequential
device that checks all its inputs continuously and changes its outputs accordingly at any time .
independent of a clock signal. Gated latches (clocked flip-flops) are latches which respond to the
inputs and latch on to a I or a Oonly when they are enabled, i.e. onlY, when the input ENABLE or
gating signal is HIGH. In the absence of ENABLE or gating signal, the latch does not respond to
the changes in its inputs (The gating signal may be a clock pulse). On the other hand, a flip-flop is
a sequential device that normally samples its inputs and changes its outputs only at times determined
by clock pulses.
A latch may be an active-HIGH input latch or an active-LOW input latch. Active-HIGH
means that the SET and RESET inputs are normally resting in the LOW state and one of them will
. I '

be pulsed HIGH whenever we want to change the latch outputs. Active-LOW means that the SET
and RESET inputs are normally resting in the HIGH state and one of them will be pulsed LOW
whenever we want to change the latch outputs.

10.4.1 The S-R Latch

The simplest type of flip-flop is called an S-R latch. It has two outputs labelled Q and Q and two
inputs labelled S and R. The state of the latch corresponds to the level of Q (HIGH or LOW, I or O)
and Qis, of course, the complement of that state. It can be constructed using either two cross-coupled
NANO gates or two-cross coupled NOR gates. Using two NOR gates, an active-HIGH S-R latch
can be constructed and using two NAND gates an active-LOW S-R latch can be constructed. The
name of the latch, S-R or SET-RESET, is derived from the names of its inputs.
Figure 10.4a shows the logic symbol of an S-R latch. When the SET input is made HIGH, Q
b~omes J (and Qequals 0). When the RESET input is made HIGH, Q becomes O(and Qequals I).
It both the inputs Sand Rare made LOW, there is no change in the state of the latch. It means that
I:

462 FUNDAMENTALS OF DIGITAL CIRCUITS

the input terminals through the combinational circuit and the delay elements. The combinational
1
• circuit generates k excitation variables which give the next state of the circuit. The excitation
variables are propagated through delay elements to become the new present state for the secondary
variables. i.e. Y p y 2, ... , yk. In the steady state condition excitation and secondary variables are the
same. but during transition they are different. In other words, we can say that for a giv~n value of
input variables, the system is stable if the circuit reaches a steady-state condition with Y; = Y;for
i = I , 2, ..., k; otherwise the circuit is in a continuous transition and is said to be unstable. · "
To ensure proper operation, it is necessary for asynchronous sequential circuits to attain a
stable state before the input is changed to a new value. Because of unequal delays in the wires and
gate circuits, it is impossible to have two or more input variables change at exactly the same instant.
Therefore, simultaneous changes of two or more input variables are usually avoided. In other words,
we can say that only one input variable is allowed to change at any one time and the time between
two input changes is kept longer than the time it takes the circuit to reach a stable state.
According to how the input variables are to be considered, there are two types of asynchronous
circuits: fundamental mode circuits and pulse mode circuits.
Fundamental mode circuit assumes that:
1. The input variables change only when the circuit is stable.
1
) 2. Only one input variable can change at a given time.
Ii 3. Inputs are levels and not pulses.
Pulse mode circuit assumes that:
I. The input variables are pulses instead of levels.
2. The width of the pulses is long enough for the circuit to respond to the input.
3. The pulse width must not be so long that it is still present after the new state is reached.

10.4 LATCHES AND FLIP-FLOPS

The most important memory element is the flip-flop, which is inade up of an assembly of logic
gates. Even though a logic gate by itself has no storage capability, several logic gates can be
connected together in ways that permit information to be stored. There are several different gate
arrangements that are used to construct flip-flops in a wide variety of ways. Each type of flip-flop
has special features or characteristics necessary for particular applications. Flip-flops are the basic
building blocks of most sequential circuits.
A flip-flop (FF), known more formally as a bistable multivibrator, has two stable states. It
can remain in either of the states indefinitely. Its state can be changed by applying the proper
triggering signal. It is also called a binary or one-bit memory.
Figure 10.3 shows the general type of symbol used for a flip-flop. The flip-flop has two
outputs, labelled Q and Q. Actually any letter can be used to represent the output, but Q is the one
most often used . The Q output is the normal output of the flip-flop and Q is the inverted output.
The output as well as its complement are available for each flip-flop. The state of the flip-flop
always r~fers_to the s~ate of the normal ou~put Q. The inverted output Q is in the opposite state. A
flip-fl op 1s said to be m HIGH state or logic I state or SET state when Q = 1, and in LOW state or
logic O state or RES ET state or CLEAR state when Q = O.
 464 FUNDAMENTALS OF DIGITAL CIRCUITS

the latch remains in the same state in which it was, prior to the application of inputs. If both the
inputs are made HIGH , the output is unpredictable, i.e. both Q and Q may be HIGH, or both may
be LOW or any one of them may be HIGH and the other LOW. This condition is descri bed as not-
allowed. unpredictable. invalid or indeterminate. The S-R latch is also called R-S latch or S-C
(SET-CL EAR) latch. Resetting is also called clearing because we CLEAR out the 1 in the output
by resetting to 0. In more complex flip-flops, called gated latches, the change of state does not take
place immediately after the application of the inputs. The change of state takes place only after
applying a gate pulse.

s Q

R Q -
}I s
0
A
0
Qn
0
Qn+1
0
State
No Change (NC)
0 0 1 1
(a) Logic symbol
0 1 0 0 Reset
A 0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 X Indeterminate
1 1 1 X (invalid)
s
(b) Logic diagram (c) Truth table
Figure 10.4 Active-HIGH S-R latch.

The NOR gate S-R latch (active-high S-R latch): Figure 10.4b shows the logic diagram of an
active-H IGH S-R latch compose d of two cross-coupled NOR gates. Note that the output of each
gate is connecte d to one of the inputs of the other gate. The latch works as per the truth table of
Figure 10.4c. Qn represents the state of the flip-flop before applying the inputs (i.e. the present
state PS of the flip-flop). Qn+I represents the state of the flip-flop after the applicati on of the inputs
(i.e. the next state NS of the flip-flop).
It is necessar y only to pulse a SET or RESET input' to change the state of the latch. For
example , if the latch is initially RESET, a pulse applied to its SET is the same as making S
momenta rily a 1, followed by a 0. The 1 sets the latch, after which R and S are once again a 0, the
no-chang e condition. Since a pulse must remain HIGH long enough for NOR gates to change
states, the minimum pulse width is the sum of the propagation delays through the gates. One gate
must change from LOW to HIGH and the other from HIGH to LOW. Thus, ·
'
' I PWmin = tPLH + tPHL
where PW min is ~he minimum pu~se widt_h required for proper operation of the gate, tPLH and fpHL,
are the propagation delays associated with the gates when the output is changing from LOW to
HIGH and HIGH to LOW, respectively.
The analysis of the operation of the active-HIGH NOR latch can be summari zed as follows .
1. SET = 0, RESET = 0: This is the normal resting state of the NOR latch and it has no
effect on the output state. Q and Q will remain in whateve r state they were prior to the
occurren ce of this input condition. , .
 FLIP-FLOPS 465

2. SET= 1, RESET= 0: This will always set Q = I, where it will remain even after SET
returns to O.
3. SET= 0, RESET= 1: This will always reset Q = 0, where it will remain even after
RESET returns to 0.
4. SET= 1, RESET= 1: This condition tries to SET and RESET the latch at the same
time, and it produces Q = Q = O. If the inputs are returned to zero simultaneously, the
resulting output state is erratic and unpredictable. This input condition should not be
used. It is forbidden.
The SET and RESET inputs are normally in the LOW state and one of them will be pulsed
HIGH, whenever we want to change the latch outputs.
The NAND gate S-R latch (active-low S-R latch): Figures 10.5a and b show the logic diagram
and truth table of an active-LOW S-R latch. Since the NAND gate is equivalent to an active-LOW
OR gate, an active-LOW S-R latch using OR gates may also be represented as shown in Figure 10.5c.

s R an Qrn-1 State
0 0 0 X Indeterminate
0 0 1 X (invalid)
s [J-1-a 0 1 0 1
Set
0 1 1 1
1 0 0 0
Reset
1 0 1 0
1 1 0 0
R
[l-4-a 1 1 1 1
No Change (NC)
R---c1
(a) Using NAND gates (b) Truth table (c) Using OR gates
Figure 10.5 An active-LOW S-R latch.

The operation of this latch is the reverse of the operation of the NOR gate latch discussed
earlier. That is why it is called an active-LOW S.,R latch. If the Os are replaced by ls and ls by Os
in Figure 10.5b, we get the same truth table as that of the NOR gate latch shown in Figure 10.4c.
The SET and RESET inputs are normally resting in the HIGH state and one of them will be
pulsed LOW, whenever we want to change the latch outputs.

The S-R latch (active-high NAND latch): An active-LOW NAND latch can be converted into
an active-HIGH NAND latch by inserting the inverters at the Sand R inputs. Figure 10.6 shows the
proof.

s s
Q s a s
Q
a
= = =
a A
a A Q a
R R

(a) Logic diagram (b) Using OR gates (c) Using NOR gates (d) Using NOR gates
Figure 10.6 An active-HIGH NANO latch.
I

·1

466 FUNDAMENTALS OF DIGITAL CIRCUITS

When power is applied to a circuit, it is not possible to predict the starting state of a flip-flop
output, when its SET and RESET inputs are in their inactive states (i.e. S = R = 1 for a NAND
latch, and S = R = 0 for a NOR latch). There is just as much chance that the starting state will be a
Q = 0 as Q = 1. It will depend on things like internal propagation delays, parasitic capacitance and
external loading.

10.4.2 Gated Latches (Clocked Flip-Flops)

The gated S-R latch: In the latches described earlier, the output can change state any time the
input conditions are changed. So, they are called asynchronous latches. A gated S-R latch requires
an ENABLE (EN) input. Its S and R inputs will control the state of the flip-flop only when the
ENABLE is HIGH. When the ENABLE is LOW, the inputs become ineffective and no change of
state can take place. The ENABLE input may be a clock. So, a gated S-R latch is also called a
clocked S-R latch or synchronous S-R latch. Since this type of flip-flop responds to the changes in
inputs only as long as the clock is HIGH, these types of flip-flops are also called level triggered
flip-flops. The sequential circuits (machines) controlled by a clock are called synchronous sequential
:I circuits (machines). The logic diagram, the logic symbol and. the truth table for a gated S-R latch
!I are shown in Figure 10. 7. In this circuit, the invalid state occurs when both S and Rare simultaneously
HIGH.
I

EN s A an Qn+1 State
1 0 0 0 0
No change (NC)
1 0 0 1 1
1 0 1 0 0 Reset
1 0 1 1 0
s 1 1 0 0 1
Set
a s 1 1 0 1 1
a
1 1 1 0 X Indeterminate
EN EN 1 1 1 1 X (invalid)

A a 0 X X 0 0
No Change (NC)
0 X X 1 1
A
(a) Logic diagram (b) Logic symbol (c) Truth table
Figure 10.7 A gated S-R latch.

EXAMPLE 10.1 Determine the output waveform Q if the inputs shown in Figure 10.8a
are applied to a gated S-R latch shown in Figure 10.8b, that was initially SET.
Solution
The output waveform Q shown in Figure 10.8c is drawn as follows:
I,
11
j
Prior to t0 , Q is HIGH. Even though R goes HIGH prior to t0 , Q will not change because
I EN is LOW. Similarly, even though S goes HIGH prior to t 1, Q will not change because EN
is LOW. Any time S is HIGH .and R is LO:W; ~ HIGH on the EN sets the latch, and any time
S is LOW and R is HIGH, a HIGH on the EN resets the latch.
p
FLIP-FLOPS 467

□.
: : t

(a) Input waveforms r____l.l. ________....L_-.:-_-'-1-....L[. .

R

ENI----.-D~D~__.~
; t

t
Il a
.

(b) Logic symbol

(c) Output waveform

on t

Figure 10.8
:

to 1 t2
□.
t3 f4 t
Example · 10.1: Wavefo rms-the gated S-R latch.
inputs to
The gated D-latch: In many applications, it is not necessary to have separat e S and R
R are always
a latch. If the input combin ations S = R = 0 and S = R = 1 are never needed , the S and
obtain the R
the comple ment of each other. So, we can construct a latch with a single input (S) and
D-latch . So,
input by invertin g it. This single input is labelled D (for data) and the device is called a
has only one
another type of gated latch is the gated D-latch. It differs from the S-R latch in that it
to SET when
input in addition to EN. When D = 1, we have S = 1 and R = 0, causing the latch
ENABL ED.
ENABL ED. When D = 0, we have S = 0 and R = 1, causing the latch to RESET when
not affect
When EN is LOW, the latch is ineffective, and any change in the value of D input does
p and a
the output at all. When EN is HIGH, a LOWD input makes Q LOW, i.e. resets the flip-flo
the output Q
HIGH D input makes Q HIGH, i.e. sets the flip-flop. In other words, we can say that
diagram ,
follows the D input when EN is HIGH. So, this latch is said to be transpa rent. The logic
the logic symbol and the truth table of a gated D-latch are shown in Figure 10.9.
D--+- ----1
·---a
D a
EN
a
(a) Logic diagram (b) Logic symbol

EN D on Qn+1 State

1 0 0 0
Reset
1 0 1 0
1 1 0 1
Set
1 1 1 1
0 X 0 0
No Change (NC)
0 X 1 1
(c) Truth table
Figure 10.9 A gated D-latch.