DIGITALLOGICFAMILIES build the circuit to accomplish the same logic function or the number of components

fabricated on the chip.

Basically, there are two types of semiconductor devices: bipolar and unipolar. Based
on these devices, digital integrated circuits have been made which are commercially The classification of digital ICs is given in Table 4.1.
available. Various digital functions are being fabricated in a variety of forms using
bipolar and unipolar technologies. A group of compatible ICs with the same logic
levels and supply voltages for performing various logic functions have been fabricated
using a specific circuit configuration which is referred to as a logic family 
Bipolar Logic Families
The main elements of a bipolar IC are resistors, diodes (are also capacitors) and
transistors. Basically, there are two types of operations in bipolar ICs:
1.Saturated, and The various characteristics of digital ICs used to compare their performances are:
2.Non-saturated. 1. Speed of operation,
2. Power dissipation,
In saturated logic, the transistors in the IC are driven to saturation, whereas in the 3. Figure of merit,
case of non-saturated logic, the transistors are not driven into saturation. 4 . F a n - o u t ,
The saturated bipolar logic families are: 5. Current and voltage parameters,
1. Resistor–transistor logic (RTL), 6. Noise immunity,
2. Direct–coupled transistor logic (DCTL), 7. 7.Operating temperature range,
3. Integrated–injection logic (I2L) 8. 8.Power supply requirements, and
4. Diode–transistor logic (DTL), 9. 9.Flexibilities available
5. High–threshold logic (HTL), and
6. Transistor-transistor logic (TTL)

Unipolar Logic Families
MOS devices are unipolar devices and only MOSFETs are employed in MOS logic
circuits.
The MOS logic families are:
1 . P M O S ,
2 . N M O S ,   a n d
3 . C M O S
While in PMOS only p -channel MOSFETs are used and in NMOS only n -channel
MOSFETs are used, in complementary MOS (CMOS), both
 p – and n -channel MOSFETs are employed and are fabricated on the same silicon
chip.

CHARACTERISTICS OF DIGITAL ICs

With the widespread use of ICs in digital systems and with the development of various
technologies for the fabrication of ICs, it has become necessary to be familiar with the
characteristics of IC logic families and their relative advantages and disadvantages.
Digital ICs are classified either according to the complexity of the circuit, as the
relative number of individual basic gates (2-input NAND gates) it would require to
Characteristics of logic families Unused inputs of CMOS devices should never be left floating or unconnected. A floating input is
highly susceptible to picking up noise and accumulating static
Gates with Open Collector/Drain Outputs
charge. Figure 5.48 Tristate buffer in CMOS.
These are gates where we need to connect an external resistor, called the pull-up resistor, between the
output and the DC power supply to make the logic gate perform the intended logic function.
Depending on the logic family used to construct the logic gate, they are referred to as gates with open
collector
output (in the case of the TTL logic family) or open drain output (in the case of the MOS logic
family).
The advantage of using open collector/open drain gates lies in their capability of providing an
ANDing operation when outputs of several gates are tied together through a common pull-up resistor,
without having to use an AND gate for the purpose. This connection is also referred to as WIRE-
This can often lead to simultaneous conduction of P-channel and N-channel devices on the chip,
AND
which causes increased power dissipation and overheating. Unused inputs of CMOS gates should
connection. Figure 4.26(a) shows such a connection for open collector NAND gates. The output in
either be connected to ground or VDD or shorted to another input. The same is applicable to the inputs
this case would be
of all those gates that are not in use.
For example, we may be using only two of the four gates available on an IC having four gates. The
inputs of the remaining two gates should be tied to either ground or VDD.

Input Protection
Owing to the high input impedance of CMOS devices, they are highly susceptible to static charge
build-up. As a result of this, voltage developed across the input terminals could become sufficiently
high to cause dielectric breakdown of the gate oxide layer.
In order to protect the devices from this static charge build-up and its damaging consequences, the
inputs of CMOS devices are protected by using a suitable resistor–diode network, as shown in Fig.
5.49(a).
The protection circuit shown is typically used in metal-gate MOSFETs such as those used in 4000-
series CMOS devices. Diode D2 limits the positive voltage surges to VDD + 0.7 V, while diode D3
clamps the negative voltage surges to −0.7 V. Resistor R1 limits the static discharge current amplitude
and thus prevents any damagingly large voltage from being directly applied to the input terminals.
Diode D1 does not contribute to input protection.
It is a distributed P–N junction present owing to the diffusion process used for fabrication of resistor input of the other, the same is not true if we have to interconnect digital ICs belonging to different
logic families.
R1. The protection diodes remain reverse biased for the normal input voltage range of 0 to VDD, and
Incompatibility of ICs belonging to different families mainly arises from different voltage levels and
therefore do not affect normal operation. current requirements associated with LOW and HIGH logic states at the inputs and outputs.
Figure 5.49(b) shows a typical input protection circuit used for silicon-gate MOSFETs used in 74C,
74HC, etc., series CMOS devices. A distributed P–N junction is absent owing to R1 being a
polysilicon resistor. Diodes D1 and D2 do the same job as diodes D2 and D3 in the case of metal-gate
devices.
Diode D2 is usually fabricated in the form of a bipolar transistor with its collector and base terminals
shorted.

Tristate Logic Gates

Tristate logic gates have three possible output states, i.e. the logic ‘1’ state, the logic ‘0’ state and a
high-impedance state. The high-impedance state is controlled by an external ENABLE input. The
ENABLE input decides whether the gate is active or in the high-impedance state. When active, it can
be ‘0’ or ‘1’ depending upon input conditions. One of the main advantages of these gates is that their
inputs and outputs can be connected in parallel to a common bus line. Figure (a) shows the circuit
symbol of a tristate NAND gate with active HIGH ENABLE input, along with its truth table. The one
shown in Fig. (b) has active LOW ENABLE input. When tristate devices are paralleled, only one of
them is enabled at a time.

Interfacing with Different Logic Families

CMOS and TTL are the two most widely used logic families. Although ICs belonging to the same
logic family have no special interface requirements, that is, the output of one can directly feed the
CMOS-to-TTL Interface CMOS-to-ECL and ECL-to-CMOS Interfaces
The first possible type of CMOS-to-TTL interface is the one where both ICs are operated from a CMOS-to-ECL and ECL-to-CMOS interfaces are similar to the TTL-to-ECL and ECL-to-TTL
common supply. We have read in earlier sections that the TTL family has a recommended supply interfaces described. Again, dedicated level translators are available. MC10352, for instance, is a
voltage of 5 V, whereas the CMOS family devices can operate over a wide supply voltage range of quad CMOS-to-ECL level translator chip. A CMOS-to-ECL interface is also possible by having
3–18 V. In the present case, both ICs would operate from 5 V. firstly a CMOS-to-TTL interface followed by a TTL-to-ECL interface using MC10124 or a similar
As far as the voltage levels in the two logic states are concerned, the two have become compatible. chip.
The CMOS output has a VOH(min.) of Figure 5.65(a) shows the arrangement. Similarly, an ECL-to-CMOS interface is possible by having
4.95V (for VCC=5 V) and a VOL(max.) of 0.05 V, which is compatible with VIH(min.) and an ECL-to-TTL interface using MC10125 or a similar chip followed by a TTL-to-CMOS interface.
VIL(max.)Requirements of approximately 2 and 0.8V respectively for TTL family devices. In fact, in Figure 5.65(b) shows a typical interface schematic.
a CMOS-to-TTL interface, with the two devices operating on the same VCC, voltage level
compatibility is always there. It is the current level compatibility that needs attention. That is, in the
LOW state, the output current sinking capability of the CMOS IC in question must at least equal the
input current-sinking requirement of the TTL IC being driven. Similarly, in the HIGH state, the
HIGH output current drive capability of the CMOS IC must equal or exceed the HIGH-level input
current requirement of TTL IC. For a proper interface, both the above conditions must be met. As a
rule of thumb, a CMOS IC belonging to the 4000B family (the most widely used CMOS family) can
feed one LS TTL or two
low-power TTL unit loads. When a CMOS IC needs to drive a standard TTL or a Schottky TTL
device, a CMOS buffer (4049B or 4050B) is used. 4049B and 4050B are hex buffers of inverting and
non-inverting types respectively, with each buffer capable of driving two standard TTL loads. Figure
5.62(a) shows a CMOS-to-TTL interface with both devices operating from 5V supply and the CMOS
IC driving a low-power TTL or a low-power Schottky TTL device. Figure 5.62(b) shows a
CMOS-to-TTL interface where the TTL device in use is either a standard TTL or a Schottky TTL.
The CMOS-to-TTL interface when the two are operating on different power supply voltages can be
achieved in several ways. One such scheme is shown in Fig. 5.62(c). In this case, there is both a
voltage level as well as a current level compatibility problem.
TTL-to-CMOS Interface
In the TTL-to-CMOS interface, current compatibility is always there. The voltage level compatibility
in the two states is a problem. VOH (min.) of TTL devices is too low as regards the VIH (min.)
requirement of CMOS devices. When the two devices are operating on the same power supply
voltage, that is, 5 V, a pull-up resistor of 10 k achieves compatibility [Fig. 5.63(a)]. The pull-up
resistor causes the TTL output to rise to about 5V when HIGH. When the two are operating on
different power supplies, one of the simplest interface techniques is to use a transistor (as a
switch) in-between the two, as shown in Fig. 5.63(b). Another technique is to use an open collector
type TTL buffer [Fig. 5.63(c)].

TTL-to-ECL and ECL-to-TTL Interfaces

TTL-to-ECL and ECL-to-TTL interface connections are not as straightforward as TTL-to-CMOS and
CMOS-to-TTL connections owing to widely different power supply requirements for the two types
and also because ECL devices have differential inputs and differential outputs. Nevertheless, special
chips are available that can take care of all these aspects. These are known as level translators.
MC10124 is one such quad TTL-to-ECL level translator. That is, there are four independent single-
input and complementary-output translators inside the chip.

Figure 5.64(a) shows a TTL-to-ECL interface using MC10124. MC10125 is a level translator for
ECL-to-TTL interfaces; it has differential inputs and a single-ended
output.
Figure 5.64(b) shows a typical interface schematic using MC10125. Note that in the interface
schematics of Figs 5.64(a) and (b), only one of the available four translators has been used.
LACTHES AND FLIPFLOP We know that a 2-input NOR gate produces an output, which
is the complement of another input when one of the input is ‘0’.
There are two types of memory elements based on the type of
Similarly, it produces ‘0’ output, when one of the input is ‘1’.
triggering that is suitable to operate it.
 If S = 1, then next state Q(t + 1) will be equal to ‘1’ irrespective of
 Latches present state, Q(t) values.
 Flip-flops  If R = 1, then next state Q(t + 1) will be equal to ‘0’ irrespective of
Latches operate with enable signal, which is level sensitive present state, Q(t) values.
whereas, flip-flops are edge sensitive At any time, only of those two inputs should be ‘1’. If both
inputs are ‘1’, then the next state Q(t + 1) value is undefined.
SR Latch
The following table shows the state table of SR latch.
SR Latch is also called as Set Reset Latch. This latch affects the
outputs as long as the enable, E is maintained at ‘1’. The circuit S R Q(t + 1) FUNCTIONS
diagram of SR Latch is shown in the following figure.
0 0 Q(t) HOLD

0 1 0 RESET

1 0 1 SET

1 1 undefined INVALID
Therefore, SR Latch performs three types of functions such as
Hold, Set & Reset based on the input conditions.

D Latch
There is one drawback of SR Latch. That is the next state value
This circuit has two inputs S & R and two outputs Q(t) & Q(t)’.
can’t be predicted when both the inputs S & R are same. So, we
The upper NOR gate has two inputs R & complement of
can overcome this difficulty by D Latch. It is also called as Data
present state, Q(t)’ and produces next state, Q(t+1) when
Latch. The circuit diagram of D Latch is shown in the
enable, E is ‘1’.
following figure.
Similarly, the lower NOR gate has two inputs S & present state,
Q(t) and produces complement of next state, Q(t+1)’ when
enable, E is ‘1’.
 FLIP-FLOPS
Latches are the basic building blocks of flip-flops. We can
implement flip-flops in two methods.
In first method, cascade two latches in such a way that the
first latch is enabled for every positive clock pulse and second
latch is enabled for every negative clock pulse. So that the
combination of these two latches become a flip-flop.
In second method, we can directly implement the flip-flop,
This circuit has single input D and two outputs Q(t) & Q(t)’. D which is edge sensitive.
Latch is obtained from SR Latch by placing an inverter between
S & R inputs and connect D input to S. That means we Types of flip-flops
eliminated the combinations of S & R are of same value.
 SR Flip-Flop
 If D = 0 → S = 0 & R = 1, then next state Q(t + 1) will be equal to ‘0’
 D Flip-Flop
irrespective of present state, Q(t) values. This is corresponding
to the second row of SR Latch state table.  JK Flip-Flop

 If D = 1 → S = 1 & R = 0, then next state Q(t + 1) will be equal to ‘1’  T Flip-Flop

irrespective of present state, Q(t) values. This is corresponding
to the third row of SR Latch state table.
SR Flip-Flop
SR flip-flop operates with only positive clock transitions or
The following table shows the state table of D latch.
negative clock transitions. Whereas, SR latch operates with
D Q(t + 1) Function enable signal. The circuit diagram of SR flip-flop is shown in
the following figure.
0 0 HOLD

1 1 HOLD
Therefore, D Latch Hold the information that is available on
data input, D. That means the output of D Latch is sensitive to
the changes in the input, D as long as the enable is High.
The latches in this chapter are implemented by providing the
cross coupling between NOR gates. Similarly, you can
implement these Latches using NAND gates.
 Present Inputs Present State Next State

S R Q(t) Q(t + 1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1
This circuit has two inputs S & R and two outputs Q(t) & Q(t)’.
1 1 0 x
The operation of SR flip-flop is similar to SR Latch. But, this flip-
flop affects the outputs only when positive transition of the 1 1 1 x
clock signal is applied instead of active enable. By using three variable K-Map, we can get the simplified
The following table shows the state table of SR flip-flop. expression for next state, Q(t + 1). The three variable K-
Map for next state, Q(t + 1) is shown in the following figure.
S R Q(t + 1) function

0 0 Q(t) hold

0 1 0 reset

1 0 1 set

1 1 undefined invalid
Here, Q(t) & Q(t + 1) are present state & next state respectively.
So, SR flip-flop can be used for one of these three functions such
as Hold, Reset & Set based on the input conditions, when
positive transition of clock signal is applied. The following table The maximum possible groupings of adjacent ones are already
shows the characteristic table of SR flip-flop. shown in the figure. Therefore, the simplified expression for
next state Q(t + 1) is
 Q(t+1)=S+R′Q(t)Q(t+1)=S+R′Q(t)D Flip-Flop 0 1

D flip-flop operates with only positive clock transitions or Therefore, D flip-flop always Hold the information, which is
negative clock transitions. Whereas, D latch operates with available on data input, D of earlier positive transition of clock
enable signal. That means, the output of D flip-flop is signal. From the above state table, we can directly write the
insensitive to the changes in the input, D except for active next state equation as
transition of the clock signal. The circuit diagram of D flip-flop Q(t + 1) = D
is shown in the following figure.
Next state of D flip-flop is always equal to data input, D for
every positive transition of the clock signal. Hence, D flip-flops
can be used in registers, shift registers and some of the
counters.

JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop. It operates
with only positive clock transitions or negative clock
transitions. The circuit diagram of JK flip-flop is shown in the
following figure.
This circuit has single input D and two outputs Q(t) & Q(t)’. The
operation of D flip-flop is similar to D Latch. But, this flip-flop
affects the outputs only when positive transition of the clock
signal is applied instead of active enable.

The following table shows the state table of D flip-flop.

D Q(t + 1)

0 0
This circuit has two inputs J & K and two outputs Q(t) & Q(t)’. 1 0 1 1
The operation of JK flip-flop is similar to SR flip-flop. Here, we
considered the inputs of SR flip-flop as S = J Q(t)’ and R = 1 1 0 1
KQ(t) in order to utilize the modified SR flip-flop for 4
1 1 1 0
combinations of inputs.
By using three variable K-Map, we can get the simplified
The following table shows the state table of JK flip-flop. expression for next state, Q(t + 1). Three variable K-Map for
next state, Q(t + 1) is shown in the following figure.
J K Q(t + 1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Q(t)'
Here, Q(t) & Q(t + 1) are present state & next state respectively.
So, JK flip-flop can be used for one of these four functions such
as Hold, Reset, Set & Complement of present state based on the
input conditions, when positive transition of clock signal is The maximum possible groupings of adjacent ones are already
applied. The following table shows the characteristic table of shown in the figure. Therefore, the simplified expression for
JK flip-flop. next state Q(t+1) is

Present Inputs Present State Next State Q(t+1)=JQ(t)′+K′Q(t)Q(t+1)=JQ(t)′+K′Q(t)

J K Q(t) Q(t+1)
T Flip-Flop
0 0 0 0
T flip-flop is the simplified version of JK flip-flop. It is obtained
0 0 1 1 by connecting the same input ‘T’ to both inputs of JK flip-flop. It
operates with only positive clock transitions or negative clock
0 1 0 0
transitions. The circuit diagram of T flip-flop is shown in the
0 1 1 0 following figure.

1 0 0 1
 Inputs Present State Next State

T Q(t) Q(t + 1)

0 0 0

0 1 1

1 0 1

1 1 0
From the above characteristic table, we can directly write
the next state equation as
This circuit has single input T and two outputs Q(t) & Q(t)’. The
Q(t+1)=T′Q(t)+TQ(t)′Q(t+1)=T′Q(t)+TQ(t)′
operation of T flip-flop is same as that of JK flip-flop. Here, we
considered the inputs of JK flip-flop as J = T and K = T in order ⇒Q(t+1)=T⊕Q(t)⇒Q(t+1)=T⊕Q(t)
to utilize the modified JK flip-flop for 2 combinations of inputs.
So, we eliminated the other two combinations of J & K, for The output of T flip-flop always toggles for every positive
which those two values are complement to each other in T flip- transition of the clock signal, when input T remains at logic
flop. High (1). Hence, T flip-flop can be used in counters.

The following table shows the state table of T flip-flop. In this chapter, we implemented various flip-flops by providing
the cross coupling between NOR gates. Similarly, you can
D Q(t + 1) implement these flip-flops by using NAND gates.

0 Q(t) In previous chapter, we discussed the four flip-flops, namely SR

flip-flop, D flip-flop, JK flip-flop & T flip-flop. We can convert
1 Q(t)’
one flip-flop into the remaining three flip-flops by including
Here, Q(t) & Q(t + 1) are present state & next state respectively. some additional logic. So, there will be total of twelve flip-flop
So, T flip-flop can be used for one of these two functions such as conversions.
Hold, & Complement of present state based on the input
Follow these steps for converting one flip-flop to the other.
conditions, when positive transition of clock signal is applied.
The following table shows the characteristic table of T flip-  Consider the characteristic table of desired flip-flop.
flop.
  Fill the excitation values (inputs) of given flip-flop for each  SR flip-flop to D flip-flop
combination of present state and next state. The excitation  SR flip-flop to JK flip-flop
table for all flip-flops is shown below.
 SR flip-flop to T flip-flop
Present Next SR flip-flop D flip-flop JK flip-flop SR flip-flop to D flip-flop conversion
State State inputs input inputs
Here, the given flip-flop is SR flip-flop and the desired flip-flop
is D flip-flop. Therefore, consider the following characteristic
Q(t) Q(t+1) S R D J table of D flip-flop.

D flip-flop input Present State Next State

0 0 0 x 0 0

D Q(t) Q(t + 1)
0 1 1 0 1 1
0 0 0
1 0 0 1 0 x
0 1 0

1 1 x 0 1 x
1 0 1

 Get the simplified expressions for each excitation input. If

necessary, use Kmaps for simplifying. 1 1 1
 Draw the circuit diagram of desired flip-flop according to the
simplified expressions using given flip-flop and necessary logic We know that SR flip-flop has two inputs S & R. So, write down
gates. the excitation values of SR flip-flop for each combination of
present state and next state values. The following table shows
Now, let us convert few flip-flops into other. Follow the same
the characteristic table of D flip-flop along with the excitation
process for remaining flipflop conversions.
inputs of SR flip-flop.
SR Flip-Flop to other Flip-Flop D flip-flop input Present State Next State SR flip
Conversions
Following are the three possible conversions of SR flip-flop to D Q(t) Q(t + 1) S
other flip-flops.
 0 0 0 0

0 1 0 0

1 0 1 1

1 1 1 x

From the above table, we can write the Boolean functions for

each input as below.

S=m2+d3S=m2+d3 This circuit consists of SR flip-flop and an inverter. This

inverter produces an output, which is complement of input, D.
R=m1+d0R=m1+d0 So, the overall circuit has single input, D and two outputs Q(t) &
Q(t)'. Hence, it is a D flip-flop. Similarly, you can do other two
We can use 2 variable K-Maps for getting simplified
conversions.
expressions for these inputs. The k-Maps for S & R are shown
below.
D Flip-Flop to other Flip-Flop
Conversions
Following are the three possible conversions of D flip-flop to
other flip-flops.

 D flip-flop to T flip-flop
 D flip-flop to SR flip-flop
 D flip-flop to JK flip-flop

D flip-flop to T flip-flop conversion

So, we got S = D & R = D' after simplifying. The circuit
diagram of D flip-flop is shown in the following figure. Here, the given flip-flop is D flip-flop and the desired flip-flop is
T flip-flop. Therefore, consider the following characteristic
table of T flip-flop.
T flip-flop input Present State Next State 1 1 0

T Q(t) Q(t + 1) From the above table, we can directly write the Boolean
function of D as below.
0 0 0
D=T⊕Q(t)D=T⊕Q(t)

0 1 1 So, we require a two input Exclusive-OR gate along with D flip-

flop. The circuit diagram of T flip-flop is shown in the
1 0 1 following figure.

1 1 0

We know that D flip-flop has single input D. So, write down the
excitation values of D flip-flop for each combination of present
state and next state values. The following table shows the
characteristic table of T flip-flop along with the excitation
input of D flip-flop.

T flip-flop input Present State Next State

T Q(t) Q(t + 1) This circuit consists of D flip-flop and an Exclusive-OR gate.

This Exclusive-OR gate produces an output, which is Ex-OR of T
and Q(t). So, the overall circuit has single input, T and two
0 0 0
outputs Q(t) & Q(t)’. Hence, it is a T flip-flop. Similarly, you can
do other two conversions.
0 1 1
JK Flip-Flop to other Flip-Flop
1 0 1 Conversions
Following are the three possible conversions of JK flip-flop to
other flip-flops.
  JK flip-flop to T flip-flop We can use 2 variable K-Maps for getting simplified
 JK flip-flop to D flip-flop T flip-flop Present State Next State JK flip-flop inputs
 JK flip-flop to SR flip-flop input

JK flip-flop to T flip-flop conversion

Here, the given flip-flop is JK flip-flop and the desired flip-flop is T Q(t) Q(t + 1) J K
T flip-flop. Therefore, consider the following characteristic
table of T flip-flop. 0 0 0 0 x

T flip-flop input Present State Next State

0 1 1 x 0
T Q(t) Q(t + 1)

1 0 1 1 x
0 0 0

1 1 0 x 1
0 1 1

expressions for these two inputs. The k-Maps for J & K are

1 0 1
shown below.

1 1 0

We know that JK flip-flop has two inputs J & K. So, write down
the excitation values of JK flip-flop for each combination of
present state and next state values. The following table shows
the characteristic table of T flip-flop along with the excitation
inputs of JK flipflop.
So, we got, J = T & K = T after simplifying. The circuit
From the above table, we can write the Boolean functions for each diagram of T flip-flop is shown in the following figure.
input as below.

J=m2+d1+d3J=m2+d1+d3

K=m3+d0+d2K=m3+d0+d2
 following table shows the characteristic table of D flip-flop
along with the excitation input of T flip-flop.

D flip-flop input Present State Next State T flip-flop input

D Q(t) Q(t + 1) T

0 0 0 0

This circuit consists of JK flip-flop only. It doesn’t require any 0 1 0 1

other gates. Just connect the same input T to both J & K. So, the
overall circuit has single input, T and two outputs Q(t) & Q(t)’.
Hence, it is a T flip-flop. Similarly, you can do other two 1 0 1 1
conversions.
1 1 1 0
T Flip-Flop to other Flip-Flop
Conversions From the above table, we can directly write the Boolean
function of T as below.
Following are the three possible conversions of T flip-flop to
other flip-flops. T=D⊕Q(t)T=D⊕Q(t)

 T flip-flop to D flip-flop So, we require a two input Exclusive-OR gate along with T flip-
 T flip-flop to SR flip-flop flop. The circuit diagram of D flip-flop is shown in the
following figure.
 T flip-flop to JK flip-flop
10.4 Level-Triggered and Edge-Triggered Flip-Flops
T flip-flop to D flip-flop conversion In a level-triggered flip-flop, the output responds to the data present at the inputs during the time the
clock pulse level is HIGH (or LOW). That is, any changes at the input during the time the clock is
Here, the given flip-flop is T flip-flop and the desired flip-flop is active
D flip-flop. Therefore, consider the characteristic table of D flip- (HIGH or LOW) are reflected at the output as per its function table. The clocked R-S flip-flop
described
flop and write down the excitation values of T flip-flop for each in the preceding paragraphs is a level-triggered flip-flop that is active when the clock is HIGH.
combination of present state and next state values. The In an edge-triggered flip-flop, the output responds to the data at the inputs only on LOW-to-HIGH
or HIGH-to-LOW transition of the clock signal. The flip-flop in the two cases is referred to as
positive
edge triggered and negative edge triggered respectively. Any changes in the input during the time
the clock pulse is HIGH (or LOW) do not have any effect on the output. In the case of an Q(t). So, the overall circuit has single input, D and two outputs
edgetriggered
flip-flop, an edge detector circuit transforms the clock input into a very narrow pulse that is Q(t) & Q(t)’. Hence, it is a D flip-flop. Similarly, you can do
a few nanoseconds wide. This narrow pulse coincides with either LOW-to-HIGH or HIGH-to-LOW other two conversions.
transition of the clock input, depending upon whether it is a positive edge-triggered flip-flop or a
negative edge-triggered flip-flop. This pulse is so narrow that the operation of the flip–flop can be
considered to have occurred on the edge itself. Master–Slave Flip-Flops
Figure 10.23 shows the clocked R-S flip-flop of Fig. 10.21 with the edge detector block incorporated Whenever the width of the pulse clocking the flip-flop is greater than the propagation delay of the
in the clock circuit. Figures 10.24 (a) and (b) respectively show typical edge detector circuits for flip-flop, the change in state at the output is not reliable. In the case of edge-triggered flip-flops, this
positive and negative edge triggering. The width of the narrow pulse generated by this edge detector pulse width would be the trigger pulse width generated by the edge detector portion of the
circuit is flip-flop
equal to the propagation delay of the inverter. Figure 10.25 shows the circuit symbol for the flip-flop
of and not the pulse width of the input clock signal. This phenomenon is referred to as the race
Fig. 10.23 for the positive edge-triggered mode [Fig. 10.25(a)] and the negative edge-triggered mode problem. As the propagation delays are normally very small, the likelihood of the occurrence of
[Fig. 10.25(b)]. a race condition is reasonably high. One way to get over this problem is to use a master–slave
configuration. Figure 10.30(a) shows a master–slave flip-flop constructed with two J-K flip-flops.
The first flip-flop is called the master flip-flop and the second is called the slave. The clock to
the slave flip-flop is the complement of the clock to the master flip-flop. When the clock pulse
is present, the master flip-flop is enabled while the slave flip-flop is disabled. As a result, the
master flip-flop can change state while the slave flip-flop cannot. When the clock goes LOW, the
master flip-flop gets disabled while the slave flip-flop is enabled. Therefore, the slave J-K flip-flop
changes state as per the logic states at its J and K inputs. The contents of the master flip-flop
are therefore transferred to the slave flip-flop, and the master flip-flop, being disabled, can acquire
new inputs without affecting the output. As would be clear from the description above, a master–
slave flip-flop is a pulse-triggered flip-flop and not an edge-triggered one. Figure 10.30(b) shows
the truth table of a master–slave J-K flip-flop with active LOW PRESET and CLEAR inputs and
active HIGH J and K inputs. The master–slave configuration has become obsolete. The newer IC
technologies such as 74LS, 74AS, 74ALS, 74HC and 74HCT do not have master–slave flip-flops in
their series.

This circuit consists of T flip-flop and an Exclusive-OR gate. This

Exclusive-OR gate produces an output, which is Ex-OR of D and