ASSIGNMENT -4 VLSI DESIGN

NARENDER SINGH
ECE-E
01496302818

Q.1 (a) Explain MOSFET capacitance model with the help of suitable diagram

Ans MOSFET Capacitance

•All electronic gadgets have interior capacitances that limit the high recurrence execution of the
gadget. In rationale applications, these capacitances limit the exchanging rate of the circuits and
in intensifiers, as far as possible the recurrence at which helpful enhancement can be acquired.

•The charge in the MOSFET reversal layer and In the exhaustion locale relies upon the voltage
applied to the entryway, source , channel and substrates. The subordinates of this accuse of
regard to the terminal voltages might be characterized as MOSFET capacitances. The MOSFET
identical circuit is displayed in fig

•The diodes between channel substrate and source-substrate address the spillage flows in the
actuated channel to substrate intersections. This comparable circuit is utilized for the re-
enactment of MOSFET circuits.
•In the straight locale (when Vds < V) the all out charge Q0 can be composed as,
QC = ∫0LQ(x)ds = W ∫0L ci Vi (x)dx

Where Q(x) is the channel charge per unit length.

W = Gate width

Ci = Gate insulator capacitance per unit area

Vi(x) = Voltage drop across the gate insulator

The gate charge Qo can be expressed as,

Q0 = 2/3Ci((Vgd-Vth)^2-(Vgs-Vth)^2)/((Vgd - Vth)^2 – (V-q - Vth)^2)

Where C = ciWL

Q1(b) Draw and explain the layout of CMOS inverter, follow all lambda based rules.

Ans. The CMOS inverter includes 2 transistors. One is a n-channel transistor, the other a p-
channel transistor

Q1(c) Explain body effect and flat band voltage with the help of suitable diagrams.
Ans. The body impact will make the number of inhabitants in electrons in the channel decline,
which will be showed remotely as a reduction in channel current. As such, we can say that body
goes about as another door, alluded as back entryway. Applying the negative potential on the
body will lessen the number of inhabitants in electrons.

Level Band Condition

1. The energy band is level (Flat band condition) when there is no applied voltage.

2. The solitary charges that exist in the diede under any biasing conditions are those in the
semiconductor and these with equivalent bu: inverse sign on the metal surface nearby the oxide.

3. There is no transporter transport through the oxide under direct current biasing conds or
resistivity of the oxide is limitless.

The above condition is also known as flat band condition

Where, ɸTP = kT /q ln(ni / N A )( N A ≫n i)

ɸyn = kT /q ln(N D /ni)(N D ≫ni )

❑

ND = Donor ion concentration

NA = Acceptor ion concentration

Q. 1. (d) Discuss how charge sharing problem can be avoided in dynamic CMOS logic
style.
Ans. One possible solution to avoid charge distribution is to include a weak pMOS transistor as
shown in Fig. A weak pMOS transistor is one that has low value of (W/L) ratio which gives high
ON resistance. The inclusion of weak pMOS transistor reduces the high impedance of output
node Y, From figure it is clear that the weak pMOS transistor will turn ON only when the output
of the inverter is low that is, when the precharge node voltage Y1 is high. If output voltage at the
inverter node in high, the weak pMOS is turned OFF. This extra pMOS transistor is known as
Keeper MOSFET MP2

In other solution, we can use separate pMOS transistors to precharge all intermediate nedes in
nMOS pull-down tree as shown in fig. The precharging of high capacitance node within the
circuit effectively eliminates the charge sharing problem during the evaluation phase. The
inclusion of extra pMOS transistors will increase the delay, area and power consumption.

The third possible solution is to use a CMOS inverter of low threshold voltage so that the final
stage output is not affected by lowering of node voltage due to charge sharing.
Q. 1. (e) Explain why substrate and well contacts are important in CMOS.

Ans. Substrate is either a semiconductor or an insulator. An insulator such as silicon oxide is

used as a substrate, a thin layer of semiconducting material, is placed on top of the oxide. This
provides superior insulation between adjacent transistors.

Q2. (a) Explain the fabrication steps of CMOS inverter in p-well CMOS technology.

Ans - cMOS fabrication:

CMOS technology is recognized as the leading VLSI technology. CMOS provides an inherently
low power static circuit technology that has the capability of providing lower power-delay
product than bipolar, nMOS or GaAs technology.

The four main CMOS technologies are:

1. P-well process
2. N-well process
3. Twin-tub process
4. Silicon on insulation process

The p-well process:

In this process of CMOS, the structure consists of an n-type substrate in which p-type devices
may be formed by suitable masking and diffusion. In order to accommodate n-type devices, a
deep p-well is diffused into the n-type substrate as shown in fig.

The diffusion must be carried out with special care since the p-well doping concentration and
depth with affect. The threshold voltages as well as the breakdown voltages of the n-transistors.
To achieve low threshold voltage (0 to 1.0 V), we need either deep well diffusion or high well
resistivity. However, deep wells require larger spacing between the n-type and p-type transistors
and wires because of lateral diffusion and hence a large chip area.

The p-wells act as substrates for the n-devices within the parent n-substrate and the two areas are
electrically isolated.

In summary, typical processing steps are:

Mask 1: Define the area in which the deep p-well diffusion is to take place.
Mask 2: Defines the thin oxide regions, namely those areas where the thick oxide is to be
stripped and thin oxide grown to accommodate p and n-transistors and wires.

Mask 3: Used to pattern the polysilicon layer which is deposited after the thin oxide.

Mask 4: A p* mask is now used (to be in effect "Andee” with mask 2) to define all areas where
p-diffusion is to take place.
Mask 5: This is usually performed using the negative form of the p* Mask and define these areas
where n type diffusion is to take place.

Mask 6: Contact cuts are now defined.

Mask 7: The metal layer pattern is defined by this mask.

Mask 8: An overall passivation (over glass) layer is now applied and a thick mask is needed to
define the openings for access to bonding pads.

Q2. (b) Describe the operation of a basic MOS inverter. Derive the expression for pull-
up to pull-down ratio for a CMOS inverter.

Ans - Complementary transistor pull-up CMOS.

A circuit diagram of the basic MOS inverter is shown in the figure below. It consist of two
enhancement mode (normally off) transistors, one used as the driver whose gate forms the input
of the inverter and a second transistor whose gate is connected to the drain and acts as a load
device:

The enhancement load inverter is the basic logic element of the first transistor-only technology.
The historic importance of this technology is that only one type of transistor was used which led
to a simple process while being very space efficient since no resistors are needed. This
technology was quickly replaced with depletion load circuits followed by complementary MOS
circuits.
Current through n-channel pull-down transistor
βn 2
I n= ( V ¿−Vt ,n )
2

Current through p-well pull-down transistor

βp 2
I p= (−( V ¿ −V DD ) +V ip )
2

At logic threshold, I n=I p

βn 2 β 2
( V ¿ −V t , n ) = p [−( V ¿ −V DD ) +V t , p ]
2 2
β

⇒ V ¿=
β
√
V DD +V t , p +V t , p n
βp

1+ n
√ βp

If β n=β p ans V t , p=−V t ,n

V DD
V ¿=
2
μ p W p μn W n
=
Lp Ln
Mobilities are unequal: μn=2.5 μ p
L
Z=
W
Z pw 2.5
=
Z pd 1
For a symmetrical CMOS inverter.
Q. 3. (a) Explain the MOS structure with N-type substrate in Accumulation, Depletion
and inversion regions with the help of energy band diagram.

Ans.
(i) The cross-sectional view and energy band diagram of the MOS structure operating in
accumulation region is

(ii) The cross-sectional view and the energy band diagram of the MOS structural operation in
depletion mode, under small gate bias.

(iii) The cross-sectional view and the energy band diagram of the MOS structure in surface
inversion, under larger bias voltage.
Q. 3. (b) Find the threshold voltage and body factory y for a N-channel transistor with
n+ silicon gate if t. = 200A*, NA = 3 x 1016/cm3, gate doping ND = 4 x1019/cm3 and
positively charged ions at the oxide silicon interface per unit area is 1010/cm2, T =
300 K.

Ans. Assuming temperature T = 300°K

Q5

a)Design the circuit descrived by the function Y=A[B+C(D+E)] using CMOS logic.Also
find the equivalent CMOS inverter circuit if (W/L)p=10 and (W/L)n=5

b)Draw the circuit of function Z=(A+B)(A'+C')(A+B'+C) using

i)Transmission gate

ii)Pseudo Logic

(a)Given Function

Y=(A(B+C(D+E))’

The CMOS design function is shown below

It is given that (W/L)p=10 and (W/L)n =5

Equivalent (W/L) can be obtained as

(W/L)n,eq between D and E = 1/(1/((W/L)D+(W/L)E)) = 1/1/(5+5)=10

The equivalent of 10 is in series with C . Hence equivalent (W/L) is

(W/L)n,eq=1/(1/10 +1/5)=10/3

This equivalent is connected in parallel with B.So

(W/L)n,eq = 1/(1/(10/3+(W/L)B))= 1/1/25/3=25/3

This equivalent is in series with A

So

(W/l)n,eq =1/((1/25/3)+(1/(W/L)A))= 25/8

Similarly to find (W/L)p,eq

D and E are connected in Series

(W/L)p,eq =1/(1/(W/L)D)+(1/(W/L)E)=1/2/10=5

Equivalent 5 and C are connected in parallel

(W/L)p,eq =5+1/(1/10)=15

Equivalent 15 and B are connected in series

(W/L)p,eq=1/((1/15)+(1/10))=1/(5/30)=6

Now equivalent 6 and A are connected in parallel, so

(W/L)p,eq=6+(1/(1/10))=6+10=16

(b)ii)using pseudo logic

Q.6.(a) Draw and explain the negative edge triggered D flip and verify it.
 Ans. The first stage is driven by the clock signal, while the second stage is driven by the
inverted clock signal, Thus, the master stage is positive level- sensitive, white the slave stage is
negative level-sensitive.

When the clock is high, the master stage follows the D input while the slave stage holds
the previous value. When the clock changes from logic ‘’1’’ to logic ‘’0’’,the master latch ceases
to sample the input and store the D value at the time of the clock transition. At the same time, the
slave latch becomes transparent, passing the stored master value Qm to the output of the slave
stage, Qs. The input cannot affect the output because the master stage is disconnected from the
D input. When the clock changes again from logic "0" to 1', the slave latch locks in the master
latch output and the master stage starts sampling the input again. Thus, this circuit is a negative
edge-triggered D flip-flop by virtue of the fact that it samples the input at the falling edge of the
clock pulse.

Q.6. (b) Explain CMOS logic based NAND SR latch circuit and explain its working.

Ans. An SR latch can also be constructed by cross-coupling NAND gates as shown in Figure
(a). The circuit operates in the shown manner as the NOR latch, but it does have few subtle
differences. Unlike the NOR leteh, the NAND latch inputs are normally 1 and must be changed
to 0 to change the output. An ambiguous output results when both the Set and resets input are at
0 .Fig(b) shows the truth NAND latch. The logic symbol for the NAND latch is shown in Fig(c);
denote that the latch responds to 0 on its inputs (i.e., it has active-low inputs)

fig(a) NAND latch fig(b) truth table fig(c) logic symbol for NAND gate

The basic SR latch circuit using two NAND2 gates is shown in Fig (d). Here, one input of each
NAND gate is used to cross-couple to the output of the other NAND gate, while the second input
enables external triggering.

• A close inspection of the NAND-based SR Latch circuit reveals that in order to hold (preserve)
a state, both of the external trigger inputs must be equal to logic ‘1’. The state of the circuit can
be changed only by pulling the set input to logic zero or by pulling the reset input to zero.

• We can observe that if S is equal to "0" and R is equal to: 1 the output Q attains a logic "1"
value and the complementary output Q becomes logic "0" Thus, in order to reset the NAND SR
latch, logic ‘0’ must be applied to the set (S) input. Similarly, in order to reset the latch, logic "0"
must be applied to the reset (R) input.

• The conclusion is that the NAND-based SR latch responds to active low input signals, as
opposed to the NOR-based SR latch, which responds to active high inputs. Note that if both input
signals are equal to logie ‘0’, both output nodes assume a logic- high level, which is not allowed
because it violates the complementarity of the two outputs.

Fig(d) CMOS SR latch circuit based on NAND2 gates

Q. 7. (a) Explain the advantages of dynamic logic circuit over static logic
circuit. Explain Domino and NORA CMOS logic circuits with suitable examples.

Ans. Static logic circuits allow implementation of logic function based on static, or
steady-state behaviour of simple n MOS or CMOS structure. In high-density, high-
performance digital implementations where reduction of circuit delay and silicon area
is a major objective dynamic circuits offer several advantages over static.
High-Performance Dynamic CMOS circuits: High-performance dynamic
CMOS circuits are variants of the basic dynamic CMOS logic gate structure. The ultimate
goal is to achieve reliable high-speed, compact circuits using the least complicated clicking
scheme possible.
Domino CMOS logic: A domino logic module consists of an n-type dynamic logic
block followed by a static inverter. The generalized circuit diagram of a domine CMOS
logic gate shown in fig. The addition of the inverter allows us to operate a number of
such structures in cascade, as explained.
• When CK = 0 (pre-charge phase), the output node of the dynamic CMOS stage is pre
charged to a high logic level, and the output of the CMOS inverter (buffer) becomes low.
When the clock signal rises at the beginning of the evaluation phase (CK = 1),
there are two possibilities: The output node of the dynamic CMOS stage is either
discharged to a low level through the nMOS circuitry (1 to 0 transitions), or it remain
high. So, the inverter output voltage can also make at most one transition during the
evaluation phase, from 0 to 1.

Domino CMOS has the following properties:

• Since each dynamic gate has a static inverter logic can be implemented.
Very high speeds can be achieved.
. Allow a significant reduction in the number of transistors required to realize any
complex boolean function.
NORA CMOS Logic (NP-Domino Logic)
An alternative approach to cascading dynamic logic is provided by NP-CMOS. NP-
CMOS uses two flavors (n-tree and p-tree) of domino logic and avoids an extra static
inverter in the critical path that comes with domino logic. The nMOS transistors acting
as pull-down networks, while the pMOS transistor are used to build a pull-up network
as shown in fig. The precharge-and-evaluate timing of nMOS logic stages is accomplished
by the clock signal CK, whereas the pMOS logic stages are controlled by the inverted
clock signal, CK.

Operation of NORA CMOS logic

• When the clock -signal (CK) is low, the output nodes of nMOS logic blocks precharged
toV DD through the pMOSW pre charge transistors, whereas the output nodes of pMOS
logic blocks are pre-discharged to 0 V through the nMOS discharge transistors, driven
by CK
• When the clock signal (CK) makes a low-to-high transition, all cascaded nMOS
and PMOS logic stages evaluate one after the other, much like the domino CMOS
examined earlier.
Advantage of NORA CMOS logic
• NORA CMOS logic is that a static CMOS inverter is not required at the output of
every dynamic logic stage.
NORA CMOS logic is that it allows pipelined system architecture.

Q. 7. (b) Draw and explain TSPC-based negative edge triggered DFF.

Ans. Single-Phase Systems for a Flip-Flop
• The clocking discipline for systems built from flip-flops is simplest. A flip-flop
system looks very much like that of the generic sequential system with a single rank of
memory elements.
• Here, we define the conditions that the clock and data signals much satisfy which
are conservative but safe. A flip-flop system has one type of clock signal CLK as shown
in Fig. The figure assumes that the flip-flop read their inputs on the positive (0 - 1)
clock edge. The data inputs much have reached stable values at the flip-flop inputs on
the rising clock edge, which gives this requirement on the primary inputs.
Q8. (a) Discuss the hierarchy of various semiconductor technologies with Moorey’s
Law and VLSI design flow (y chart).
Ans. Moore’s Law
In 1965, G. Moore, one of the early integrated circuit pioneers, according to his
prediction, the number of transistors on a chip doubled about every two years. Each year
computer chips become more powerful yet cheaper than the year before, Gordon Moore once
said, “If the auto industry advanced as rapidly as the semiconductor industry, a Rolls Royce
would get a half a million per gallon and it would be cheaper to throw it away than to park it”.

The revolutionary nature of this development is indicated by the way in which the number of the
transistors integrated in circuits on a single chip has grown as shown in the figure below.
The most important factor in achieving such complexity is the continued reduction of the
minimum device dimension. Since 1960, the annual rate of reduction has been 13% at the rate;
the minimum feature length will shrink from its present length of 1 micrometer to 0.01
micrometer in the year 2000.

VLSI Design Flow: The design process, at various levels, is usually evolutionary in nature. The
design description for an integrated circuit may be described in terms of three domains namely:
behavioral, structural and physical domains. In each of these domains there are a number of
design options that may be selected to solve a particular problem. Initially all the designs are
developed and tested against the requirements: All the three domains may be hierarchically
divided into levels of design abstraction. Classically, these include the following:

Architectural or functional level

.
• Register Transfer Level (RTL)
• Logic level
• Circuit level

Thi Y-chart (first introduced by D. Gajski) shown in figure below illustrates the relationship
between description domains and levels of design abstraction. In this diagram, the three radial
lines represent the three description domains, namely, behavioral, structure and physical domain.
The design flow starts from the algorithm that describes the behavior of the target chip. First we
define the corresponding architecture of the processor. It is mapped on the chip surface by
floorplanning. The behavioral design domain defines finite state machines (FSMs) which are
structurally implemented with functional modules and arithmetic logic units (ALU's). These
modules are used for automatic module placement followed by routing, with a goal of
minimizing the interconnected area and signal delays using CAD tools. The third design domain
starts with a behavioral module description. This module is then implemented with leaf cells
(logic gates). At this stage the chip is described in terms of logic gates, which can be placed and
interconnected by using a cell placement and routing program.

The concentric circles around the centre of Y-chart indicate the various levels of abstraction that
are common in electronic design. The particular abstraction levels and design objects may differ
slightly, depending on the design method. The simplest flow (view) of the VLSI design is shown
in Fig. This flow consists of various representations, abstraction of design and mask layout. The
role of verification of design is important at every step during the process.
(b) Explain the following circuits.

(i) Variable threshold CMOS circuit

(ii) Multi threshold CMOS

Ans. (i) Variable threshold CMOS circuit

Variable Threshold CMOS (VTCMOS) devices are one solution to this problem. One of the
efficient methods to reduce power consumption is to use low supply voltage and low threshold
voltage without losing speed performance. But increase in the lower threshold voltage devices
leads to increased sub-threshold leakage and hence more standby power consumption. VTCMOS
technique threshold voltage of the low threshold devices are varied by applying variable
substrate bias voltage from a control circuitry.VTCMOS technique is a very effective technique
to reduce the power consumption with some drawbacks related to manufacturing of these
devices. VTCMOS requires either twin well or triple well technology to achieve different
substrate bias voltage levels at different parts of the IC. The area overhead of the substrate bias
control circuitry is negligible.

(ii)Multi-threshold CMOS (MTCMOS) is a variation of CMOS chip technology which has

transistors with multiple threshold voltages (Ven) in order to optimize delay or power. The Vth of
a MOSFET is the gate voltage where an inversion layer forms at the interface between the
insulating layer (oxide) and the substrate (body) of the transistor. Low Vth devices switch faster,
and are therefore useful on critical delay paths to minimize clock period. The penalty is that low
Vth devices have substantially higher static leakage power. High Vth devices are used on non-
critical paths to reduce static leakage power without încurring a delay penalty. Typical high Vth
devices reduce static leakage by 10 times compared with low Vth devices. One method of creating
devices with multiple threshold voltages is to apply different bias voltages (Vb) to the base or
bulk terminal of the transistors. Other methods involve adjusting the gate oxide thickness, gate
oxide dielectric constant (material type), or dopant concentration in the channel region beneath
the gate oxide. A common method of fabricating multi-threshold CMOS involves simply adding
additional photolithography and ion implantation steps. For a given fabrication process, the Vth is
adjusted by altering the concentration of dopant atoms in the channel region beneath the gate
oxide.