INDEX

EXP.N
NAME OF THE EXPERIMENT
O
1. Study of 8085 Microprocessor trainer kit
Arithmetic Operations with
a. 8-bit numbers (Addition, Subtraction, Multiplication,
2 Division)
b. 16- bit numbers (Addition, Subtraction, Multiplication,
Division)
Block Operations
a. Block Initialization
b. Block Move
c. Block Copy
d. Block Compare
3
e. Block Interchange
f. Block Insert
g. Block Delete
h. Block Search

Code Conversion
a. BCD to Binary
4 b. Binary to BCD
c. Binary to ASCII
d. ASCII to Binary

5 Largest and Smallest number in an Array

6 Sorting of N Numbers in Ascending and descending order

7 Searching an Given Number

8 Digital Clock Simulation

9 Printer Interfacing
10 Stepper Motor Interfacing
Serial Communication
11 a. Within a kit
b. Kit to kit

12 Music Synthesizer

13 Traffic Light Controller

Exp. No: 01 STUDY OF 8085 MICROPROCESSOR KIT

AIM:

To study the entire structure, parts and architecture of 8085 microprocessor trainer
kit.

APPARATUS REQUIRED:

8085 microprocessor kit.

BASIC FEATURES:

 24 TTL Lines
 Hardware single stepping
 RS 232-C compatible serial port
 Bus Expansion for interfacing VBMB series of add-on cards and 24-TTL input-
output lines.

SPECIFICATIONS:

HARDWARE SPECIFICATIONS:

1. Processor, Clock Frequency:

Intel 8085A at 6.144 MHz clock.

2. Memory:

Monitor EPROM : 0000 - 1FFF

EPROM ~ Expansion : 2000 - 3FFF & C000- FFFF
System RAM : 4000 - 5FFF
Monitor Data Area : 4000 - 40FF(Reserved)
User RAM area : 4100 - 5FFF
Ram ~ Expansion : 6000 – BFFF

3. Input/Output:

Parallel:
48 TTL I/O lines using two members of 8255
(only 24 I/O lines available in micro-85 EB1)

Serial:
One number of RS232C compatible serial interfaces using 8251A
USART.
 Timer:

Three channel 16-bit programmable time using 8253.

Channel 0 is used as baud rate clock generator for 8251A USART.

Channel 1 is used for in single stepping user programs.
Channel 2 is used for hardware single stepping user programs.

4. Display:
6 digit, 0.3”, 7 segment red LED display with filter.
4 digits for address display and 2 digits for data display.

5. Keyboard:

21 keys (soft keyboard including command keys and hexadecimal keys).

6. Battery backup:

Onboard battery backup facility is provided for the available RAM.

7. Hardware single step:

This facility allows the user to execute programs at machine cycle level
using a separate switch.

SOFTWARE SPECIFICATION:
1. Monitor program – 8 K

HEX KEY FUNCTION

1. Hex Key.
2. Register Key.
3. Command key.

21 KEYS:
16-KEYS – HEX, COMMAND, REGISTER KEYS remaining are stand alone
keys.

KEYS:
1. Hex Keys ‘0’, ‘1’, ‘2’, ‘3’,…………., ‘F’
2. Command Keys
3. Register Key ‘E’, ‘D’, ‘C’, ‘B’, ‘F’, ‘A’, ‘L’, ‘H’, ‘I’, ‘PL’, ‘PH’, ‘SL’, ‘SH’

KEY FUNCTION SUMMARY:

RES – This key allows you to terminate any present activity and to return to an initialized
state.

INT – Maskable Interrupt connected to CPU’s RST 7.5 interrupt.

DEC – Decrement the address by one and display it contents or Display the prvious
contents.

EXEC – Execute a particular program after selecting the address through GO command.

NEXT – Increment address by one and display its content or Display the next register
content.

SUB – Substituting the memory Contents.

When ‘NEXT’ key is pressed, immediately press after this key it takes the user to
the start address for entering user programs. (user RAM 4100)

REG – Examine the 8085A Registers and Modify the same.

TW – Writes data from memory on to the audio tape TR – Retries data from an audio
tape to memory.

BLOC – Block search for a byte.

FILL – Fill a block of RAM memory with desired data.

SER – Transmit/receive data to/from the serial port.

F2 – Function Key.

GO – Start running a particular program.

SNG – Single step a program instruction by instruction.

PL – Register key PCL

PH – Register Key PCH

PC – Program Counter

H – High

L – Low

F3 – Function key

F[0] – Input a byte from a port.

F[1] – Output a byte from aport.

F[3] with SNG – For hardware Single Stepping

SL – register Key SPL

SH – Register Key SPH

BC – Check a particular block for blank.

SP – Stack Pointer

MOV – Move a block of memory to another block

CMP – Compare 2 memory blocks

INS – Insert a byte with memory

DEL – Delete a byte with memory

INPUT OUTPUT ALLOCATION TABLE:

USER DEVELOPMENT

II PARALLEL PORT (8255)

I PARALLEL PORT (8235)

PROGRAMMABLE INTERVAL
TIMER (8253)

USART (8251)

HARDWARE SINGLE STEP

CONTROL
KEYBOARD/DISPLAY
CONTROLLER (8279)

JUMPER KEYS:

J3 AND J4 – RAM
J5 – EPROM

J3 J4 J5

8K RAM 16K RAM 32K RAM

KEY FUNCTIONS:

1. SUBSTITUTE MEMORY COMMAND:

Used To Examine The Contents Of Selected Memory Location And

Modify Its Content If Desired

RESET - SUB - Add - NEXT - data - ….. INT

Press INT to terminate the sub command.

Pressing the NEXT after entry of desired data will put the entered data to
memory location desired them.

2. REGISTER COMMAND:
To examine the register content.

RESET - SUB - b – 45 - NEXT - ……- INT

3. GO AND EXECUTE COMMAND:

GO – Used To Run Aprogram. This Command Transfer To Control Of
8085 MPU, from keypad monitor to user program.
GO - address - EXEC

4. GO AND EXECUTE COMMAND WITH BREAK POINT:

This command executes a block of program whose start address are
specified. It is equivalent to pressing INTR key while the program is being
executed.

GO - starting address - NEXT - break point address - EXEC

Content will be displayed – reg –b (or) – content will be displayed

5. SINGLE STEP:
This command helps the user to execute programs in steps (i.e .,)
Instruction by instruction
Useful while debugging
SNG - address - NEXT
 6. FILL COMMAND:
This command moves permits a block of Ram memory to be filled with
desired data type.
GO NEXT EXEC

7. BLOCK MOVE COMMAND:

This command compares the contents of two blocks of memory to another
block of memory whose starting address is specified.
MOV -starting add- NEXT -ending add- NEXT NEXT
- destination end INT
add

8. COMPARE COMMAND:
This command compares the contents of two blocks of memory locations
and display address whose contents are not identical.

CMP -starting add- NEXT - ending add- NEXT - destination end

NEXT INT
Address

9. INSERT COMMAND:
This command inserts the specified bytes in desired memory location

INS - ending add- NEXT - insert add -NEXT - data –NEXT

10. DELETE COMMAND:

This command deletes byte from memory.

DEL - block start address- NEXT - block end address - NEXT - program end NEXT
Address
The block starting from (block and address +1) to the program end address will be
moved to the block starting address from block start address.

11. INPUT COMMAND:

This command inputs data from desired port

F3 -0- port add - NEXT - data - NEXT - INT

12. OUPUT COMMAND:

This command inputs data from desired port

F3 -1- port add - NEXT - data - NEXT - INT

 13. BLOCK SEARCH COMMAND:
This command searches a block of memory for a particular byte.

BLOC - starting add- NEXT - ending add - NEXT - byte - NEXT - INT

14. BLOCK CHECK COMMAND:

To check a block of memory for location on that do not contain FF.

BC - - Starting address - NEXT - ending address - NEXT

ARCHITECTURE OF 8085:

The 8085 is an 8-bit general-purpose microprocessor capable of addressing

64K of memory. The device has forty pins, requires a +5v single power supply, and can
operate with a 3MHz single phase clock.

It consists of various functional blocks as listed below:

i. Registers
ii. Arithmetic and logic unit
iii. Instruction decoder and machine cycle encoder
iv. Address buffer
v. Address/Data buffer
vi. Incrementer/Decrementer address latch
vii. Interrupt control
viii. Serial I/O control
ix. Timing and control circuitry

(i) REGISTERS:
It has 8 addressable 8-bit registers A, B, C, D, E, H, L, F and two 16 bit
register PC and SP.
These registers can be classified as:
1. General purpose registers.
2. Temporary registers
a. Temporary data register
b. W and Z registers
3. Special purpose registers
a. Accumulator
b. Flag registers
c. Instruction register
4. Sixteen bit registers
a. Program Counter (PC)
b. Stack Pointer (SP)
1. General purpose registers:

B, C, D, E, H and L are 8-bit general purpose registers can be used as a Separate 8-

bit registers or as 16-bit register pairs BC, DE and HL. When used in register pair mode,
the higher order byte resides in the first register and lower order byte in the second. HL
pair also functions as a data pointer or memory pointer. These are also called Scratchpad
registers.

a. Temporary data register:

The ALU has two inputs. One input is supplied by the Accumulator
and other from temporary data register. The programmer cannot access this
temporary data register. However, it is internally used for execution of most
of the arithmetic and logical instructions.

For E.g.: ADD B

This instruction adds the contents if register A and register B and stores
the result in A.

b. W and Z Registers:

W and Z registers are temporary registers. These registers are used to

hold 8-bit data during execution of some instructions. XCHG instruction
exchanges the contents of H with D and L with E. At the time of exchange W
and Z registers are used for temporary storage of data.

2. Special purpose register

a. Register A (ACCUMULATOR)

It is a tri-state eight bit register. It is extensively used in

arithmetic, logic, load and store operations, as well as in I/O operations.
Most of the times the result of arithmetic and logical operations is stored
in the register A. Hence, it is also identified as accumulator.

b. Flag Registers:

It is an eight bit register, in which five of the bits carry

significant Information in the form of flags.

i. S-Sign flag:

After the execution of arithmetic or logical operations, if bit

D7 of the result is 1, the sign flag is set. In a given byte if D7 is 1, the
number will be viewed as Negative number. If D7 is 0, the number will
be considered as positive number.
 ii. Z-Zero flag:

The zero flag sets if the result of operation in ALU is zero and
flag resets if result is non-zero. The zero flag is also set if a certain
register content becomes zero following an increment or decrement
operation of that register.

iii. AC-Auxiliary carry flag:

This flag is set if there is an overflow out of bit 3 i.e. carry from
lower nibble to higher nibble(D3 to D7 bit) and it is not available for the
programmer.

iv. P-Parity flag:

Parity is defined by the number of ones present in the accumulator.

After an arithmetic or logical operation if the result has an even number of
ones, i.e. even parity, the flag is set. If the parity is odd, flag is reset.

v. CY-Carry flag:

This flag is set if there is an overflow out of bit7. The carry flag
also serves as a borrow flag for subtraction.

(c) Instruction Register:

In a typical processor operation, the processor first fetches the

opcode of instruction from memory. The CPU stores this opcode in a
register called the instruction register. This opcode is further sent to the
instruction decoder to select one of the 256 alternatives.

1. Sixteen bit registers:

(a) Program Counter(PC)

Program is a sequence of instructions. As mentioned earlier, the

Microprocessor fetches these instructions from the memory and executes
them sequentially. The program counter is a special purpose register
which, at a give time, stores the address of the next instruction to be
fetched. Program counter acts as a pointer to the next instruction. How
processor increments program counter depends on the nature
of the instruction; for one byte instruction it increments program counter
by one, for two byte instruction it increments program counter by two and
for three byte instruction it increments program counter by three such that
program counter always points of the address of the next instruction.
 (b) In case of JUMP and CALL instructions, address followed by
JUMP and CALL instructions is placed in the program counter. The
processor then fetches the next instruction from the new address specified
by JUMP or CALL instruction. In conditional JUMP and conditional
CALL instructions, if the condition is not satisfied, the processor
increments program counter by three so that it points the instruction
followed by conditional JUMP or CALL instruction; otherwise processor
fetches the next instruction from the new address specified by JUMP or
CALL instruction. Stack Pointer

The stack is an reserved area of the memory in the RAM where

temporary the information may be stored. A 16-bit stack pointer is used
to hold the address of most recent stack entry.

(ii) ARITHMETIC LOGIC UNIT (ALU)

The 8085’s ALU performs arithmetic and logical functions on

eight bit variables. The arithmetic unit performs bitwise fundamental
arithmetic operations such as addition and subtraction. The logic unit
performs logical operations such as complement, AND, OR and EX-OR,
as well as rotate and clear. The ALU also looks after the branching
decisions

(iii) INSTRUCTION DECODER

We know that, the processor first fetches the opcode of instruction

from memory and stores this opcode in the instruction register. It is then
sent to the instruction decoder. The instruction decoder decodes it and
accordingly gives the timing and control signals which control the register,
the data buffers, ALU and external peripheral signals depending on the
nature of the instruction.

The 8085 executes seven different types of machine

cycles. It gives the information about which machine cycle is currently
executing in the encoded form on the S0, S1 and IO/M. This task is done
by machine cycle encoder.

(iv) ADDRESS BUFFER

This is an 8-bit unidirectional buffer. It is used to drive external

higher order address bus (A15-A8). It is also used to tri-state the high
order address bus under certain conditions such as reset, hold, halt, and
when address lines are not in use.

(v) ADDRESS/DATA BUFFER:

This is an 8-bit bi-directional buffer. It is used to drive

multiplexed address/data bus i.e. low order address bus (D7-D0). It is also
 used to tri-state the multiplexed address/data bus under certain conditions
such as reset, hold, and halt and when the bus is not in use. The address
and data buffers are used to drive external address and data buses
respectively. Due to these buffers the address and data buses can be tri-
stated when they are not in use.

(vi) INCREMENTER/DECREMENTER ADDRESS LATCH

This 16-bit register is used to increment of decrement the contents

of the program counter of stack pointer as a part of execution of
instructions related to them.

(vii) INTERRUPT CONTROL

The processor fetches, decodes and executes instructions in a

sequence. Sometimes it is necessary to have the processor the
automatically execute one of a collection of special routines.

Whenever special condition exists within a program or the

microcomputer system. The most important thing is that, after execution
of the special routine, the program control must be transferred to the
program which processor was executing before the occurrence of the
special condition. The occurrence of this special condition is referred as
interrupt. The interrupt inputs RST5.5, RST 6.5, RST 7.5, TRAP and
INTR and one acknowledge signal INTA.

(viii) SERIAL I/O CONTROL

In situations like, data transmission over long distance and

communication with cassette tapes or a CRT terminal, it is necessary to
transmits data bit by bit to reduce the cost of cabling. In serial
communication one bit is transferred at a time over a single time. The
8085’s serial I/O control provides two lines, SOD and SID for serial
communication. The serial output data (SOD) line is used to send data
serially and SID is used to receive data serially.

(ix) TIMING AND CONTROL CIRCUITRY

The control circuitry in the processor 8085 is responsible for all

the operations. The control circuitry and hence the operations in 8085 are
synchronized with the help of clock signal. Along with the control of
fetching and decoding operations and generating appropriate signals for
instruction execution, control circuitry also generates signals required to
interface external devices to the processor 8085.
 8085 MICROPROCESSOR PIN DIAGRAM
                                                             
                    _________    _________                   
                 _|         \__/         |_                 
          --> X1 |_|1                   40|_| Vcc (+5V)      
                  _|                      |_                 
          --> X2 |_|2                   39|_| HOLD <--       
                  _|                      |_                 
   <-- RESET OUT |_|3                   38|_| HLDA -->       
                  _|                      |_                 
         <-- SOD |_|4                   37|_| CLK (OUT) -->  
                  _|                      |_  ________       
         --> SID |_|5                   36|_| RESET IN <--   
                  _|                      |_                 
        --> TRAP |_|6                   35|_| READY <--      
                  _|                      |_     _           
     --> RST 7.5 |_|7                   34|_| IO/M -->       
                  _|                      |_                 
     --> RST 6.5 |_|8                   33|_| S1 -->         
                  _|                      |_  __             
     --> RST 5.5 |_|9                   32|_| RD -->         
                  _|                      |_  __             
        --> INTR |_|10      8085A       31|_| WR -->         
            ____  _|                      |_                 
       <-- INTA |_|11                  30|_| ALE -->        
                  _|                      |_                 
        <--> AD0 |_|12                  29|_| S0 -->         
                  _|                      |_                 
        <--> AD1 |_|13                  28|_| A15 -->        
                  _|                      |_                 
        <--> AD2 |_|14                  27|_| A14 -->        
                   _|                      |_                  
        <--> AD3 |_|15                  26|_| A13 -->        
                  _|                      |_                 
        <--> AD4 |_|16                  25|_| A12 -->        
                   _|                      |_                  
        <--> AD5 |_|17                  24|_| A11 -->        
                  _|                      |_                 
        <--> AD6 |_|18                  23|_| A10 -->        
                   _|                      |_                  
        <--> AD7 |_|19                  22|_| A9 -->         
                  _|                      |_                 
       (Gnd) Vss |_|20                  21|_| A8 -->         
                    |______________________|                   
 8085 MICROPROCESSOR ARCHITECTURAL BLOCK DIAGRAM

RST5.5
____ INTA RST7.5
INTR SID SOD
TRAP
RST5.5

INTERRUPT CONTROL SERIAL I/O CONTROL

8-BIT INTERNAL DATA BUS

ACCUMULATOR TEMP. REGISTER INSTRUCTION DECODER

MULTIPLEXER

TEMP. REG W TEMP. REG Z

B REGISTER C REGISTER
FLAG (5)
FLIP FLOPS
INSTRUCTION DECODER AND MACHINE CYCLE ENCODING D REGISTER E REGISTER

H REGISTER L REGISTER

ALU
STACK POINTER

PROGRAM COUNTER
INC/DEC ADDRESS LATCH

+5V
POWER SUPPLY

GND

CLKTIMING AND CONTROL

GEN ADDRESS BUFFER DATA / ADD. BUFFER
CONTROL STATUS DMA RESET

___ ___ __
RD WR IO/M
CLKOUT READY ALE S0 S1 HOLD ________
RESETIN

HLDA RESETOUT
RESULT:
Thus, the entire structure of 8085 has been studied.
 Exp. No: 02 ARITHMETIC OPERATIONS

AIM:

To perform arithmetic operations such as addition, subtraction, multiplication, division

operations on two 8-bit and 16-bit numbers.

2 (A). 8 BIT DATA ADDITION

AIM:

To add two 8 bit numbers stored at consecutive memory locations.

ALGORITHM:

1. Initialize memory pointer to data location.

2. Get the first number from memory in accumulator.
3. Get the second number and add it to the accumulator.
4. Store the answer at another memory location.

RESULT:

Thus the 8 bit numbers stored at 4500 &4501 are added and the result stored at 4502 & 4503.
PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

4100 START MVI C, 00
Clear C reg.
4101
4102 LXI H, 4500
Initialize HL reg. to
4103
4500
4104
Transfer first data to
4105 MOV A, M
accumulator

Increment HL reg. to point

4106 INX H
next memory Location.

Add first number to acc.

4107 ADD M
Content.
4108 JNC L1
4109 Jump to location if result does
not yield carry.
410A
410B INR C Increment C reg.
Increment HL reg. to point
410C L1 INX H
next memory Location.

Transfer the result from acc.

410D MOV M, A
to memory.

Increment HL reg. to point

410E INX H
next memory Location.
410F MOV M, C Move carry to memory
4110 HLT Stop the program

SAMPLE INPUT AND OUTPUT:

INPUT OUTPUT
4500 21 4502 23
4501 02 4503 00
4500 FE 4502 02
4501 04 4503 01

OBSERVATION:
 INPUT OUTPUT
4500 4502
4501 4503
2 (B). 8 BIT DATA SUBTRACTION
AIM:

To subtract two 8 bit numbers stored at consecutive memory locations.

ALGORITHM:

1. Initialize memory pointer to data location.

2. Get the first number from memory in accumulator.
3. Get the second number and subtract from the accumulator.
4. If the result yields a borrow, the content of the acc. is complemented and 01H is added
to it (2’s complement). A register is cleared and the content of that reg. is incremented
in case there is a borrow. If there is no borrow the content of the acc. is directly taken as
the result.
5. Store the answer at next memory location.

RESULT:

Thus the 8 bit numbers stored at 4500 &4501 are subtracted and the result stored at

4502 & 4503.

 PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT

4100 START MVI C, 00
Clear C reg.
4101
4102 LXI H, 4500
Initialize HL reg. to
4103
4500
4104
Transfer first data to
4105 MOV A, M
accumulator
Increment HL reg. to point next
4106 INX H
memory location.
Subtract first number from acc.
4107 SUB M
Content.
4108 JNC L1
Jump to location if result does
4109
not yield borrow.
410A
410B INR C Increment C reg.
410C CMA Complement the Acc. content
410D ADI 01H
Add 01H to content of acc.
410E
Increment HL reg. to point next
410F L1 INX H
memory location.
Transfer the result from acc. to
4110 MOV M, A
memory.
Increment HL reg. to point next
4111 INX H
memory location.
4112 MOV M, C Move carry to memory.
4113 HLT Stop the program

SAMPLE INPUT AND OUTPUT:

INPUT OUTPUT
4500 37 4502 F7
4501 40 4503 01
4500 23 4502 21
4501 02 4503 00

OBSERVATION:

INPUT OUTPUT
4500 4502
4501 4503
 2 (C). 8 BIT DATA MULTIPLICATION
AIM:

To multiply two 8 bit numbers stored at consecutive memory locations and store the

result in memory.

ALGORITHM:

LOGIC: Multiplication can be done by repeated addition.

1. Initialize memory pointer to data location.

2. Move multiplicand to a register.
3. Move the multiplier to another register.
4. Clear the accumulator.
5. Add multiplicand to accumulator
6. Decrement multiplier
7. Repeat step 5 till multiplier comes to zero.
8. The result, which is in the accumulator, is stored in a memory location.

RESULT:

Thus the 8-bit multiplication was done in 8085p using repeated addition method.
PROGRAM:
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT
4100 START LXI H, 4500 Initialize HL reg. to
4101 4500
4102
Transfer first data to
4103 MOV B, M
reg. B
Increment HL reg. to
4104 INX H point next mem
ocation.
4105 MVI A, 00H Clear the acc.
4106
4107 MVI C, 00H Clear C reg for carry
4108
Add multiplicand
4109 L1 ADD M
multiplier times.
410A JNC NEXT
Jump to NEXT if there
410B
is no carry
410C
410D INR C Increment C reg
410E NEXT DCR B Decrement B reg
410F JNZ L1
Jump to L1 if B is not
4110
zero.
4111
Increment HL reg. to
4112 INX H point next mem.
Location.
Transfer the result from
4113 MOV M, A
acc. to memory.
Increment HL reg. to
4114 INX H point next mem.
Location.
Transfer the result from
4115 MOV M, C
C reg. to memory.
4116 HLT Stop the program
SAMPLE INPUT AND OUTPUT:
INPUT OUTPUT
4500 20 4502 40
4501 02 4503 00

OBSERVATION:
 INPUT OUTPUT
4500 4502
4501 4503
2 (D). 8 BIT DIVISION

AIM:

To divide two 8-bit numbers and store the result in memory.

ALGORITHM:

LOGIC: Division is done using the method Repeated subtraction.

1. Load Divisor and Dividend

2. Subtract divisor from dividend
3. Count the number of times of subtraction which equals the quotient
4. Stop subtraction when the dividend is less than the divisor .The dividend now becomes
the remainder. Otherwise go to step 2.
5. stop the program execution.

RESULT:

Thus an ALP was written for 8-bit division using repeated subtraction method and

executed using 8085 p kits

PROGRAM:

MNEMO OPERA
ADDRESS OPCODE LABEL COMMENTS
NICS ND
4100 MVI B,00
Clear B reg for quotient
4101
4102 LXI H,4500
Initialize HL reg. to
4103
4500H
4104
4105 MOV A,M Transfer dividend to acc.
4106 INX H Increment HL reg. to point
next mem. Location.
4107 LOOP SUB M Subtract divisor from dividend
4108 INR B Increment B reg
4109 JNC LOOP
Jump to LOOP if result does
410A
not yield borrow
410B
410C ADD M Add divisor to acc.
410D DCR B Decrement B reg
410E INX H Increment HL reg. to point
next mem. Location.
410F MOV M,A Transfer the remainder from
acc. to memory.
4110 INX H Increment HL reg. to point
next mem. Location.
4111 MOV M,B Transfer the quotient from B
reg. to memory.
4112 HLT Stop the program

SAMPLE INPUT AND OUPTUT:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
4500 03 4502 05
4501 15 4503 00

OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
4500 4502
4501 4503
 2 (E). 16 BIT DATA ADDITION

AIM:

To add two 16-bit numbers stored at consecutive memory locations.

ALGORITHM:

1. Initialize memory pointer to data location.

2. Get the first number from memory and store in Register pair.
3. Get the second number in memory and add it to the Register pair.
4. Store the sum & carry in separate memory locations.

RESULT:

Thus an ALP program for 16-bit addition was written and executed in 8085p using

special instructions.
PROGRAM:
ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENT
8000 START LHLD 8050H
8001 Load the augend in DE
8002 pair through HL pair.
8003 XCHG
8004 LHLD 8052H
Load the addend in HL
8005
pair.
8006
8007 MVI A, 00H Initialize reg. A for
8008 carry
Add the contents of HL
8009 DAD D Pair with that of DE
pair.
800A JNC LOOP If there is no carry, go
800B to the instruction
800C labeled LOOP.
Otherwise increment
800D INR A
reg. A
800E LOOP SHLD 8054H Store the content of HL
800F Pair in 8054H(LSB of
8010 sum)
8011 STA 8056H Store the carry in
8012 8056H through Acc.
8013 (MSB of sum).
8014 HLT Stop the program.

SAMPLE INPUT AND OUTPUT:

INPUT OUTPUT
ADDRES DATA ADDRESS DATA
S
8050H A1 8054H 56
8051H 78 8055H 1E
8052H B5 8056H 01
8053H A5

OBSERVATION:

INPUT OUTPUT
ADDRES DATA ADDRESS DATA
S
8050H 8054H
8051H 8055H
8052H 8056H
 8053H

2 (F). 16 BIT DATA SUBTRACTION

AIM:

To subtract two 16-bit numbers stored at consecutive memory locations.

ALGORITHM:

1. Initialize memory pointer to data location.

2. Get the subtrahend from memory and transfer it to register pair.
3. Get the minuend from memory and store it in another register pair.
4. Subtract subtrahend from minuend.
5. Store the difference and borrow in different memory locations.

RESULT:

Thus an ALP program for subtracting two 16-bit numbers was written and executed.
PROGRAM:
MNEMO OPER
ADDRESS OPCODE LABEL COMMENTS
NICS AND
8000 START MVI C, 00
Initialize C reg.
8001
8002 LHLD 8050H
8003 Load the subtrahend in DE reg.
8004 Pair through HL reg. pair.
8005 XCHG
8006 LHLD 8052H
Load the minuend in HL reg.
8007
Pair.
8008
Move the content of reg. L to
8009 MOV A, L
Acc.
Subtract the content of reg. E
800A SUB E
from that of acc.
Move the content of Acc. to
800B MOV L, A
reg. L
Move the content of reg. H to
800C MOV A, H
Acc.
Subtract content of reg. D with
800D SBB D
that of Acc.
Transfer content of acc. to reg.
800E MOV H, A
H
800F SHLD 8054H
Store the content of HL pair in
8010
memory location 8504H.
8011
8012 JNC NEXT
If there is borrow, go to the
8013
instruction labeled NEXT.
8014
8015 INR C Increment reg. C
NEXT Transfer the content of reg. C to
8016 MOV A, C
Acc.
8017 STA 8056H
Store the content of acc. to the
8018
memory location 8506H
8019
801A HLT Stop the program execution.

OBSERVATION:
INPUT OUTPUT
ADDRES DATA ADDRESS DATA
S
8050H 43 8054H C1
 8051H 87 8055H 03
8052H 82 8056H 00
8053H 83

2 (G). 16 BIT MULTIPLICATION

AIM:

To multiply two 16 bit numbers and store the result in memory.

ALGORITHM:

1. Get the multiplier and multiplicand.

2. Initialize a register to store partial product.
3. Add multiplicand, multiplier times.
4. Store the result in consecutive memory locations.

RESULT:

Thus the 16-bit multiplication was done in 8085p using repeated addition method.
PROGRAM:

ADDRESS OPCODE LABEL MNEMONICS OPERAND COMMENTS

8000 START LHLD 8050
Load the first No. in
8001
stack pointer through
8002
HL reg. pair
8003 SPHL
8004 LHLD 8052 Load the second No. in
8005 HL reg. pair
8006 & Exchange with DE
8007 XCHG reg. pair.
8008 LXI H, 0000H
8009
800A
800B LXI B, 0000H Clear HL & DE reg.
800C pairs.
800D
800E LOOP DAD SP Add SP with HL pair.
800F JNC NEXT If there is no carry, go
8010 to the instruction
8011 labeled NEXT
8012 INX B Increment BC reg. pair
Decrement DE reg.
8013 NEXT DCX D
pair.
Move the content of
8014 MOV A,E
reg. E to Acc.
8015 ORA D OR Acc. with D reg.
8016 JNZ LOOP If there is no zero, go to
8017 instruction labeled
8018 LOOP
8019 SHLD 8054 Store the content of HL
801A pair in memory
801B locations 8054 & 8055.
Move the content of
801C MOV A, C
reg. C to Acc.
801D STA 8056 Store the content of
801E Acc. in memory
801F location 8056.
Move the content of
8020 MOV A, B
reg. B to Acc.
8021 STA 8057 Store the content of
 8022 Acc. in memory
8023 location 8056.
Stop program
8024 HLT
execution

SAMPLE INPUT AND OUTPUT:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8050 A1 8054 56
8051 78 8055 1E
8052 B5 8056 01
8053 A5 8057 00

OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8050 8054
8051 8055
8052 8056
8053 8057
 2(H). 16- BIT DIVISION

AIM:

To divide two 16-bit numbers and store the result in memory using 8085 mnemonics.

ALGORITHM:

1. Get the dividend and divisor.

2. Initialize the register for quotient.
3. Repeatedly subtract divisor from dividend till dividend becomes less than divisor.
4. Count the number of subtraction which equals the quotient.
5. Store the result in memory.

RESULT:

Thus the 16-bit Division was done in 8085p using repeated subtraction method.
PROGRAM:
MNEM OPERA
ADDRESS OPCODE LABEL COMMENTS
ONICS ND
8000 START LHLD 8052
8001 Load the first No. in stack pointer
8002
through HL reg. pair
8003 XCHG
8004 LHLD 8050
8005 Load the second No. in HL reg.
pair
8006
& Exchange with DE reg. pair.
8007 LXI B, 0000H
8008
8009 Clear BC reg. pair.
800A LOOP MOV A, L Move the content of reg. L to Acc.
800B SUB E Subtract reg. E from that of Acc.
800C MOV L, A Move the content of Acc to L.
800D MOV A, H Move the content of reg. H Acc.
800E SBB D Subtract reg. D from that of Acc.
800F MOV H, A Move the content of Acc to H.
8010 INX B Increment reg. Pair BC
8011 JNC LOOP
If there is no carry, go to the location
8012
labeled LOOP.
8013
8014 DCX B Decrement BC reg. pair.
8015 DAD D Add content of HL and DE reg. pairs.
8016 SHLD 8054
Store the content of HL pair in 8054 &
8017
8055.
8018
8019 MOV A, C Move the content of reg. C to Acc.
801A STA 8056
Store the content of Acc. in memory
801B
8056
801C
801D MOV A, B Move the content of reg. B to Acc.
801E STA 8057
Store the content of Acc. in memory
801F
8057.
8020
 8021 HLT Stop the program execution.
SAMPLE INPUT AND OUTPUT:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8050 02 8054 01
8051 00 8055 00
8052 01 8056 80
8053 01 8057 00

OBSERVATION:
INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8050 8054
8051 8055
8052 8056
8053 8057
 Exp. No: 03 BLOCK OPERATIONS

AIM:

To perform various types of block operations.

3(A). BLOCK INITIALIZATION

AIM:

To initialize a block of memory to 00.

ALGORITHM:

1.Load Accumulator with counter value

2.If counter value is zero, no initialization
3.Load the starting memory locations of block in HL pair
4.Increment the HL register pair value and initialize tom zero until counter decrement to
zero.
RESULT:

Thus the block of memory has been initialized.

PROGRAM:

MNEM OPERA COMMENTS

ADDRESS OPCODE LABEL
ONICS ND
8200 LXI H,8000
Load the HL Register
8201
pair
8202
Moving the content of
8203 MOV B,M
HL register pair to B
Increment the HL register
8204 INX H
pair
8205 MVI M,00 Loading the content of
8206 HL register pair to zero
8207 DCR B Decrementing B register
8208 JNZ 8204
8209 If there is no zero
820A
820B HLT STOP

SAMPLE INPUT AND OUTPUT:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8000 05 (no of inputs) 8000 00
8001 11 8001 00
8002 22 8002 00
8003 EE 8003 00
8004 FF 8004 00
8005 DD 8005 00

OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8000 (no of inputs) 8000 -
8001 8001
8002 8002
8003 8003
8004 8004
 8005 8005

3 (B). BLOCK MOVE

AIM:

To move the contents of one block to another.

ALGORITHM:

1. Initialize B register with no of data’s

2. Load the HL and DE register pair with the data’s.
3. Move the HL register pair content to accumulator and store it in DE register apir.
4. Move Zero’s to the empty memory location of HL register pair.
5. Decrement B register.
6. Repeat the above last three steps till B becomes Zero.
7. Store the result and program.

RESULT:

Thus the contents of a block of memory have been moved to another place.
PROGRAM:

ADDR MNEMO COMMENTS

OPCODE LABEL OPERAND
ESS NICS
8100 LXI H, 8000
8101 Load the HL Register pair
8102
Load the B register with
8103 MOV B, M
number of data
8104 LXI D, 8500
8105 Load the DE register pair
8106
8107 LI INX H Increment the HL register pair
8108 INX D Increment the DE register pair
Move the content of HL
8109 MOV A, M
register pair to register pair
Moving zero to HL register
810A MVI M, 00
pair
Storing A content in DE
810C STAX D
register pair
810D DCR B Decrement B register
810E JNZ 8107 (L1)
If B is Zero, go to next step
810F
else go to 8107
8110
8111 HLT Stop

SAMPLE INPUT AND OUTPUT:

INPUTS OUTPUTS

ADDRE ADDRE ADDRE ADDRE

DATA DATA DATA DATA
SS SS SS SS
8000 05 8500 05

8001 11 8501 66 8001 00 8501 11

8002 22 8502 77 8002 00 8502 22

8003 33 8503 88 8003 00 8503 33

8004 44 8504 99 8004 00 8504 44

8005 FF 8505 AA 8005 00 8505 FF

OBSERVATION:

INPUTS OUTPUTS

ADDRE ADDRE ADDRE ADDRE

DATA DATA DATA DATA
SS SS SS SS
8000 8500

8001 8501 8001 8501

8002 8502 8002 8502

8003 8503 8003 8503

8004 8504 8004 8504

8005 8505 8005 8505

 3 (C). BLOCK COPY

AIM:

To copy the contents of one block to another.

ALGORITHM:

1. Get the no of data’s and first set of data’s in HL register pair.

2. Move the number of data’s to B register.
3. Get another set of data’s in DE register pair.
4. Move the Hl register pair content to A.
5. Move the A content to DE register pair and store it.
6. Repeat the above process till B register becomes Zero.

RESULT:

Thus the contents of block of memory have been copied to another place.
PROGRAM:

ADDR OPC MNEMO

LABEL OPERAND COMMENTS
ESS ODE NICS
8500 LXI H, 9000
8501 Load the no of data
8502
8503 MOV B, M Move that to B register
8504 LXI D, 8600
Load the data’s in DE register
8505
pair
8506
8507 INX H Get the data
Get one location DE register
8508 INX D
pair
Move the HL register pair
8509 MOV A, M
content to A register
850A STAX D Store that in DE register pair
850B DCR B Decrement B register
850C JNZ 8507
If B is Zero, go to next else goto
850D
8507
850E
850F HLT Stop

SAMPLE INPUT AND OUTPUT:

INPUTS OUTPUTS
ADDRES ADDRES ADDRES ADDRES
DATA DATA DATA DATA
S S S S
9000 05 8060 05
9001 1A 8061 A1 9001 1A 8061 1A
9002 2A 8062 A2 9002 2A 8062 2A
9003 3A 8063 A3 9003 3A 8063 3A
9004 4A 8064 A4 9004 4A 8064 4A
9005 5A 8064 A5 9005 5A 8065 5A
 OBSERVATION:

INPUTS OUTPUTS
ADDRES ADDRES ADDRES ADDRES
DATA DATA DATA DATA
S S S S
9000 8060
9001 8061 9001 8061
9002 8062 9002 8062
9003 8063 9003 8063
9004 8064 9004 8064
9005 8064 9005 8065
 3 (C). BLOCK COMPARE

AIM:

To compare the contents of one block with another.

ALGORITHM:

1. Load the B register with number of data’s.

2. Load the HL and DE register pair with the data.
3. Compare the HL and De register pair content. If they are equal make that location as
zero, else make the location as FF.
4. Repeat it till B becomes Zero.

RESULT:

Thus the contents of two blocks of memory have been compared.

PROGRAM:
ADDR MNEMO OPERAND
OPCODE LABEL COMMENTS
ESS NICS
8400 LXI H, 8000
8401 Loading the HL register pair
8402
Load B register with no of
8403 MOV B, M
Data
8404 LXI D, 8200
8405 Loading DE register pair
8406
Increment HL and get the
8407 INX H
data
Increment DE and get the
8408 INX D
data
8409 LDAX D Moving DE content to A
Comparing A with HL
840A CMP M
content.
840B JNZ 8413
If it is not zero, goto 8413
840C
else goto next step
840D
840E MVI M, 00 If it is Zero, move zero to HL
840F register pair
8410 JMP 8415
8411 Go to 8415 Step
8412
8413 MVI M, FF If it is not zero, move FF to
8414 HL
8415 DCR B Decrement B register
8416 JNZ 8407
8417 If B is zero, goto next step
8418
8419 HLT Stop

SAMPLE INPUT AND OUTPUT:

INPUTS OUTPUTS
ADDRESS DATA ADDRESS DATA ADDRESS DATA
8000 05 8200 05 8001 -
8001 AA 8201 AA 8002 00
8002 1A 8202 12 8003 FF
8003 BB 8203 BB 8004 00
8004 C2 8204 C2 8005 00
8005 2C 8205 35 8006 FF
OBSERVATION:

INPUTS OUTPUTS
ADDRESS DATA ADDRESS DATA ADDRESS DATA
8000 8200 8001 -
8001 8201 8002
8002 8202 8003
8003 8203 8004
8004 8204 8005
8005 8205 8006
 3 (D). BLOCK INTERCHANGE

AIM:

To exchange the data between two memory blocks.

ALGORITHM:

1. Load the number of data’s in ‘B’ register.

2. Load the Hl and DE register pair with data.
3. Move the HL register pair content to DE register pair
4. Before moving the Hl register pair content to DE move DE content to A
5. After moving HL content to DE move A to HL.
6. Decrement B and repeat the above process till B is Zero

RESULT:

Thus the contents of two blocks of memory have been exchanged.

PROGRAM:

ADDR MNEMO OPERAND

OPCODE LABEL COMMENTS
ESS NICS
8300 LXI H, 8000
8301 Load the HL register apir
8302
8303 MOV B, M Move the no of data’s to B
8304 LXI D, 8500
8305 Load the DE register pair
8306
Increment HL register pair
8307 INX H
and get the data
Increment DE register pair
8308 INX D
and get the data
Loading the DE register
8309 LDAX D
content to A
830A MOV C, M Moving HL content C
830B MOV M, A Moving A to HL
To make HL as DE and HL
830C XCHG
as DE
830D MOV M, C Moving C to Hl register pair
Making HL as DE and DE as
830E XCHG
HL
830F DCR B Decrement B register
8310 JNZ 8307
If B is Zero, goto next step
8311
else goto 8307
8312
8313 HLT Stop

SAMPLE INPUT AND OUTPUT:

INPUTS OUTPUTS
ADDRES ADDRES ADDRES ADDRES
DATA DATA DATA DATA
S S S S
8000 05 8500 05
8001 1A 8501 A1 8001 A1 8501 1A
8002 2A 8502 A2 8002 A2 8502 2A
8003 3A 8503 A3 8003 A3 8503 3A
8004 4A 8504 A4 8004 A4 8504 4A
8005 5A 8505 A5 8005 A5 8505 5A
 OBSERVATION:

INPUTS OUTPUTS
ADDRES ADDRES ADDRES ADDRES
DATA DATA DATA DATA
S S S S
8000 8500
8001 8501 8001 8501
8002 8502 8002 8502
8003 8503 8003 8503
8004 8504 8004 8504
8005 8505 8005 8505
 3 (D). BLOCK INSERT

AIM:

To perform insert a data in memory block.

ALGORITHM:

1. Load the HL and DE register pair

2. Move DE content to A register pair
3. Subtract that from L and adding 01 to A and moving that to B.
4. Get the position to be inserted and the elements to be inserted.
5. Move the elements in that position downwards and insert the elements
6. Store the results.

RESULT:

Thus the contents of two blocks of memory have been compared.

PROGRAM:

ADDR MNEMO OPERAND

OPCODE LABEL COMMENTS
ESS NICS
8100 LXI H, 9500 Load the HL register pair
8101
8102
8103 XCHG Copy HL to DE
Load the size of block to be
8104 LDAX D
inserted
8105 SUB L Subtract L from A
8106 ADI 01 Add 01 to A
8107
8108 MOV B, A Move result to B
8109 STA 9700 Starting that in 9700
810A
810B
810C LXI D, 9700 Making this as temp
810D
810E
810F XCHG Exchanging DE and HL
8110 MOV M, A Moving that to HL
Incrementing DE register
8111 INX D
pair
8112 DCR B Decrement B register
8114 JNZ 8112
8115
8116
8117 LHLD 9500
8118
8119
811A

SAMPLE INPUT AND OUTPUT:

 INPUTS OUTPUTS
ADDRES ADDRES ADDRES ADDRES
DATA DATA DATA DATA
S S S S
8000 05 8500 05
8001 1A 8501 A1 8001 A1 8501 1A
8002 2A 8502 A2 8002 A2 8502 2A
8003 3A 8503 A3 8003 A3 8503 3A
8004 4A 8504 A4 8004 A4 8504 4A
8005 5A 8505 A5 8005 A5 8505 5A

OBSERVATION:

INPUTS OUTPUTS
ADDRES ADDRES ADDRES ADDRES
DATA DATA DATA DATA
S S S S
8000 8500
8001 8501 8001 8501
8002 8502 8002 8502
8003 8503 8003 8503
8004 8504 8004 8504
8005 8505 8005 8505
 6(A). LARGEST ELEMENT IN AN ARRAY

AIM:
To find the largest element in an array.

ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next
element).
7. If the accumulator content is smaller, then move the memory content
(largest element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.

RESULT:
Thus the largest number in the given array is found out.
PROGRAM:

ADDRE OPCO LABEL MNEM OPER COMMENTS

SS DE ONICS AND
8001 LXI H,8100 Initialize HL reg. to
8002 8100H
8003
8004 MVI B,04 Initialize B reg with no. of
8005 comparisons(n-1)
8006 MOV A,M Transfer first data to acc.
8007 LOOP1 INX H Increment HL reg. to point
next memory location
8008 CMP M Compare M & A
8009 JNC LOOP If A is greater than M then go
800A to loop
800B
800C MOV A,M Transfer data from M to A reg
800D LOOP DCR B Decrement B reg
800E JNZ LOOP1 If B is not Zero go to loop1
800F
8010
8011 STA 8105 Store the result in a memory
8012 location.
8013
8014 HLT Stop the program

OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8100 8105
8101
8102
8103
8104
 6(B). SMALLEST ELEMENT IN AN ARRAY

AIM:
To find the smallest element in an array.

ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next
element).
7. If the accumulator content is smaller, then move the memory content
(largest element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.

RESULT:
Thus the smallest number in the given array is found out.
PROGRAM:

ADDRE OPCO LABEL MNEM OPER COMMENTS

SS DE ONICS AND
8001 LXI H,8100 Initialize HL reg. to
8002 8100H
8003
8004 MVI B,04 Initialize B reg with no. of
8005 comparisons(n-1)
8006 MOV A,M Transfer first data to acc.
8007 LOOP1 INX H Increment HL reg. to point
next memory location
8008 CMP M Compare M & A
8009 JC LOOP If A is lesser than M then go
800A to loop
 800B
800C MOV A,M Transfer data from M to A reg
800D LOOP DCR B Decrement B reg
800E JNZ LOOP1 If B is not Zero go to loop1
800F
8010
8011 STA 8105 Store the result in a memory
8012 location.
8013
8014 HLT Stop the program

OBSERVATION:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8100 8105
8101
8102
8103
8104
 7(A).ASCENDING ORDER

AIM:
To sort the given number in the ascending order using 8085 microprocessor.

ALGORITHM:

1. Get the numbers to be sorted from the memory locations.

2. Compare the first two numbers and if the first number is larger than second then I
interchange the number.
3. If the first number is smaller, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order

RESULT:

Thus the ascending order program is executed and thus the numbers are arranged in
ascending order.
PROGRAM:

ADDR OPCO LABEL MNEM OPER COMMENTS

E DE ONICS AND
SS
8000 MVI B,04 Initialize B reg with number
8001 of comparisons (n-1)
8002 LOOP 3 LXI H,8100 Initialize HL reg. to
8003 8100H
8004
8005 MVI C,04 Initialize C reg with no. of
8006 comparisons(n-1)
8007 LOOP2 MOV A,M Transfer first data to acc.
8008 INX H Increment HL reg. to point
next memory location
8009 CMP M Compare M & A
800A JC LOOP1 If A is less than M then go to
800B loop1
800C
800D MOV D,M Transfer data from M to D reg
800E MOV M,A Transfer data from acc to M
800F DCX H Decrement HL pair
8010 MOV M,D Transfer data from D to M
8011 INX H Increment HL pair
8012 LOOP1 DCR C Decrement C reg
8013 JNZ LOOP2 If C is not zero go to loop2
8014
 8015
8016 DCR B Decrement B reg
8017 JNZ LOOP3 If B is not Zero go to loop3
8018
8019
801A HLT Stop the program

OBSERVATION:

INPUT OUTPUT
MEMORY DATA MEMORY DATA
LOCATION LOCATION
8100 8100
8101 8101
8102 8102
8103 8103
8104 8104
 7(B). DESCENDING ORDER

AIM:
To sort the given number in the descending order using 8085 microprocessor.

ALGORITHM:

1. Get the numbers to be sorted from the memory locations.

2. Compare the first two numbers and if the first number is smaller than second then I
interchange the number.
3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order

RESULT:

Thus the descending order program is executed and thus the numbers are arranged in
descending order.
PROGRAM:

ADDR OPCO LABEL MNEM OPER COMMENTS

E DE ONICS AND
SS
8000 MVI B,04 Initialize B reg with number
8001 of comparisons (n-1)
8002 LOOP 3 LXI H,8100 Initialize HL reg. to
8003 8100H
8004
8005 MVI C,04 Initialize C reg with no. of
8006 comparisons(n-1)
8007 LOOP2 MOV A,M Transfer first data to acc.
8008 INX H Increment HL reg. to point
next memory location
8009 CMP M Compare M & A
800A JNC LOOP1 If A is greater than M then go
800B to loop1
800C
800D MOV D,M Transfer data from M to D reg
800E MOV M,A Transfer data from acc to M
800F DCX H Decrement HL pair
8010 MOV M,D Transfer data from D to M
8011 INX H Increment HL pair
8012 LOOP1 DCR C Decrement C reg
8013 JNZ LOOP2 If C is not zero go to loop2
8014
 8015
8016 DCR B Decrement B reg
8017 JNZ LOOP3 If B is not Zero go to loop3
8018
8019
801A HLT Stop the program

OBSERVATION:

INPUT OUTPUT
MEMORY DATA MEMORY DATA
LOCATION LOCATION
8100 8100
8101 8101
8102 8102
8103 8103
8104 8104
 8(A). CODE CONVERSION –DECIMAL TO HEX

AIM:

To convert a given decimal number to hexadecimal.

ALGORITHM:

1. Initialize the memory location to the data pointer.

2. Increment B register.
3. Increment accumulator by 1 and adjust it to decimal every time.
4. Compare the given decimal number with accumulator value.
5. When both matches, the equivalent hexadecimal value is in B register.
6. Store the resultant in memory location.

RESULT:

Thus an ALP program for conversion of decimal to hexadecimal was written and

executed.

PROGRAM:

ADDRE OPCO LABEL MNEM OPER COMMENTS

SS DE ONICS AND
8000 LXI H,8100 Initialize HL reg. to
8001 8100H
8002
8003 MVI A,00 Initialize A register.
8004
 8005 MVI B,00 Initialize B register..
8006
8007 LOOP INR B Increment B reg.
8008 ADI 01 Increment A reg
8009
800A DAA Decimal Adjust Accumulator
800B CMP M Compare M & A
800C JNZ LOOP If acc and given number are
800D not equal, then go to LOOP
800E
800F MOV A,B Transfer B reg to acc.
8010 STA 8101 Store the result in a memory
8011 location.
8012
8013 HLT Stop the program

RESULT:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8100 8101
 8(B). CODE CONVERSION –HEXADECIMAL TO DECIMAL

AIM:

To convert a given hexadecimal number to decimal.

ALGORITHM:

1. Initialize the memory location to the data pointer.

2. Increment B register.
3. Increment accumulator by 1 and adjust it to decimal every time.
4. Compare the given hexadecimal number with B register value.
5. When both match, the equivalent decimal value is in A register.
6. Store the resultant in memory location.

RESULT:
 Thus an ALP program for conversion of hexadecimal to decimal was written and

executed.

PROGRAM:

ADDRE OPCO LABEL MNEM OPER COMMENTS

SS DE ONICS AND
8000 LXI H,8100 Initialize HL reg. to
8001 8100H
8002
8003 MVI A,00 Initialize A register.
8004
8005 MVI B,00 Initialize B register.
8006
8007 MVI C,00 Initialize C register for carry.
8008
8009 LOOP INR B Increment B reg.
800A ADI 01 Increment A reg
800B
800C DAA Decimal Adjust Accumulator
800D JNC NEXT If there is no carry go to
800E NEXT.
800F
8010 INR C Increment c register.
8011 NEXT MOV D,A Transfer A to D
8012 MOV A,B Transfer B to A
8013 CMP M Compare M & A
8014 MOV A,D Transfer D to A
8015 JNZ LOOP If acc and given number are
8016 not equal, then go to LOOP
8017
8018 STA 8101 Store the result in a memory
8019 location.
801A
801B MOV A,C Transfer C to A
801C STA 8102 Store the carry in another
801D memory location.
801E
801F HLT Stop the program
RESULT:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
8100 8101
8102

STUDY OF 8279 PROGRAMMABLE

KEYBOARD/DISPLAY INTERFACE
AIM:

To study the entire structure of 8279 Programmable Keyboard/Display Interface.

INTRODUCTION:

The 8279 is a hardware approach to interfacing a matrix keyboard and a multiplexed

display. The 8279 is a 40 pin device with two major segments: Keyboard and Display.

The keyboard segment can be connected to a 64-contact key matrix. Keyboard entries are
debounced and stored in the internal FIFO memory; an interrupt signal is generated with each
entry.

The display segment can be provide a sixteen character scanned display interface with
such device as LED’s. This segment has 16/8 R/W memory (RAM), which can be used to
read/write information for display purposes. The display can be set up in either right-entry of
left-entry format.

BLOCK DIAGRAM OF 8279:

The block diagrams about 4 major routine of the 8279.

 Keyboard
 Scan
 Display
 Microprocessor Interface

KEYBOARD SECTION:

This section has 8 lines (RL0-RL7) that can be connected to eight columns of a keyboard,
plus two additional lines: Shift and CNTL/STB (Control/Strobe). The keys are automatically
debounced and the keyboard can operate in 2 modes: Two Key Lockout or N-key rollover.

In the two-key lockout mode, if two keys are pressed almost simultaneously, only the
first key is recognized. In the N-key roll-over mode, simultaneous keys are recognized and
their codes are stored in the internal buffer; it can also be set up so that no key is recognized
until only one key remains pressed.

The keyboard section also includes an 8*8 FIFO RAM. The FIFO RAM consists of eight
registers that can store and keyboard entries; each is then read in the order of entries. The
status logic keeps track of the number of entries and provides an IRQ signal when the FIFO is
not empty.

SCAN SECTION:
Page No:
DISPLAY SECTION:

The display section has 8 output lines divide into 2 groups.

 A0-A3
 B0-B3

These lines can be used, either as a group of eight lines or as two groups of four, in
conjunction with the scan lines for a multiplexed display. The display can be blanked by using
the BD line. This section includes 16*8 displays RAM. The microprocessor can read from or
write into any of these registers.

MICROPROCESSOR INTERFACE SECTION:

This section includes 8-bit directional data lines (DB0-DB7), one interrupt request line
(IRQ), and 6 lines for interfacing, including the buffer address line (A0). When A0 is high,
signals are interrupted as data. The IRQ line goes high whenever data entries are stored in the
FIFO. This signal is used to interrupt the microprocessor to indicate the availability of data.

KEYBOARD:

The keyboard in this design is an input port with keys assigned in the matrix format.
When a key is pressed, the keyboard routine should provide a binary equivalent of the key.
This can be accomplished in obvious ways.

 One of the software approaches, where by a key closer is sensed, debound and identified and
the key code is obtained by using the software.
 The other is the hardware approach, whereby all these key functions are performed through a
programmable keyboard encoder.
 8279 is the keyboard interface controller. Location is 010. The keys are divided into 2 groups.

ARCHITECTURE AND SIGNAL DESCRIPTIONS OF 8279

The keyboard display controller chip 8279 provides:

a) a set of four scan lines and eight return lines for interfacing keyboards
b) A set of eight output lines for interfacing display.

 I/O Control and Data Buffers :

The I/O control section controls the flow of data to/from the 8279. The data buffers
interface the external bus of the system with internal bus of 8279. Architecture and Signal
Descriptions of 8279
The I/O section is enabled only if CS is low. The pins A0, RD and WR select the
command, status or data read/write operations carried out by the CPU with 8279.

 Control and Timing Register and Timing Control :

Page No:
  Scan Counter :

The scan counter has two modes to scan the key matrix and refresh the display. In the
encoded mode, the counter provides binary count that is to be externally decoded to provide
the scan lines for keyboard and display (Four externally decoded scan lines may drive upto 16
displays). In the decode scan mode, the counter internally decodes the least significant 2 bits
and provides a decoded 1 out of 4 scan on SL0-SL3( Four internally decoded scan lines may
drive upto 4 displays). The keyboard and display both are in the same mode at a time.

 Return Buffers and Keyboard Debounce and Control:

This section for a key closure row wise. If a key closer is detected, the keyboard
debounce unit debounces the key entry (i.e. wait for 10 ms). After the debounce period, if the
key continues to be detected. The code of key is directly transferred to the sensor RAM along
with SHIFT and CONTROL key status.

 FIFO/Sensor RAM and Status Logic:

In keyboard or strobed input mode, this block acts as 8-byte first-in-firstout (FIFO)
RAM. Each key code of the pressed key is entered in the order of the entry and in the mean
time read by the CPU, till the RAM become empty. The status logic generates an interrupt
after each FIFO read operation till the FIFO is empty. In scanned sensor matrix mode, this unit
acts as sensor RAM. Each row of the sensor RAM is loaded with the status of the
corresponding row of sensors in the matrix. If a sensor changes its state, the IRQ line goes
high to interrupt the CPU.

 Display Address Registers and Display RAM :

The display address register holds the address of the word currently being written or
read by the CPU to or from the display RAM. The contents of the registers are automatically
updated by 8279 to accept the next data entry by CPU.

SIGNALS:

The signal discription of each of the pins of 8279 as follows :

 DB0-DB7 :

These are bidirectional data bus lines. The data and command words to and from the
CPU are transferred on these lines.

 CLK :

This is a clock input used to generate internal timing required by 8279.

 RESET :

This pin is used to reset 8279. A high on this line reset 8279. After resetting 8279, its in
sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The clock prescaler is set
to 31.

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 CS : Chip Select

A low on this line enables 8279 for normal read or write operations. Otherwise, this pin
should remain high.

 A0 :

A high on this line indicates the transfer of a command or status information. A low on
this line indicates the transfer of data. This is used to select one of the internal registers of
8279.

 RD, WR :

These input pins enable the data buffers to receive or send data over the data bus.

 IRQ :

This interrupt output lines goes high when there is a data in the FIFO sensor RAM.
The interrupt lines goes low with each FIFO RAM read operation but if the FIFO RAM
further contains any key-code entry to be read by the CPU, this pin again goes high to
generate an interrupt to the CPU.

 Vss, Vcc :

These are the ground and power supply lines for the circuit.

 SL0-SL3-Scan Lines :

These lines are used to scan the key board matrix and display digits. These lines can
be programmed as encoded or decoded, using the mode control register.

 RL0 - RL7 - Return Lines :

These are the input lines which are connected to one terminal of keys, while the other
terminal of the keys are connected to the decoded scan lines. These are normally high, but
pulled low when a key is pressed.

 SHIFT :

The status of the shift input lines is stored along with each key code in FIFO, in
scanned keyboard mode. It is pulled up internally to keep it high, till it is pulled low with a key
closure.

 BD – Blank Display :

This output pin is used to blank the display during digit switching or by a blanking
 Page No:

two 4-bit ports may also as one 8-bit port.

 CNTL/STB- CONTROL/STROBED I/P Mode :

In keyboard mode, this lines is used as a control input and stored in FIFO on a key
closure. The line is a strobed lines that enters the data into FIFO RAM, in strobed input mode.
It has an interrupt pull up. The lines is pulled down with a key closer.

KEYS:

I. RES : The RES key allows you to terminate any present activity and to
return your “Micro-85EB” to an initiated state. When pressed the µ85 sign-
on message operates in the display for few seconds and monitors will display
command promt “_” in the left most digit.

II. INT : Maskable interrupt connected to CPU’s RST 7.5, RST 6.5, RST 5.5.

III. DEC : Decrement the address by one and display its content ordisplay the previous
register content.

IV. EXEC : Execute particular program after selecting the address through GO command.

V. NEXT : Increment address by one and display its content or display the next register
contents.

VI. SUB : Substitute memory content SUB key used for starting address to the program.

VII. REG : Examine contents of register.

VIII. TW : Read/data available.

IX. TR : Read/Retrive data from memory through addition tab.

X. BLOCK : Search for byte.

XI. FILL : Block of RAM fills the data.

XII. SEA : Transmit/Receive serial port.

XIII. F2 : Function Key.

XIV. GO : Start/RUN the program

XV. SNG : Single step.

 XVI. BC : Check

XVII. MOV : Move one block to another

XVIII. CMP : Compare 2 memory blocks.

XIX. CNS : Insert byte into memory.

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XX. DEL : Delete byte from memory.

There are totally 21 keys on keyboard. !6 keys are Hex keys and 5 function keys.

PROGRAMMING THE 8279:

The 8279 is a complex device that can accept, 8 different commands to perform
various functions. The initialization commands can specify:

I. Left or right entry and key rollover.

II. Clock frequency p
III. Starting address and incrementing mode of the FIFO RAM.
IV. RAM address to read and write data and incrementing mode.
V. Blanking format.
RESULT:

Thus the various parts of 8279 Programmable Keyboard/Display Interface has been studied.
 Page No:

STUDY OF 8251A PROGRAMMABLE COMMUNICATION

INTERFACE

AIM:

To study the entire structure of programmable communication interface (8251 A).

INTRODUCTION:

The 8251 is a programmable chip designed for synchronous and asynchronous serial
data communication packaged in a 28 pin DIP ( Dual Inline Package).

The 8251 is the enhanced version of its predecesion, the 8051 and its compatible with
the 8251. The block diagram of 8251 A includes Read/Write control logic. Transmitter,
Receiver, Database buffer and MODEM control.

The control logic interfaces the chip with the microprocessor. Determines the
functions of the chip according to the control word in its register and monitors the data flow.
The transmitter section converts a parallel word received from the microprocessor into serial
bits and transmits them over the Txp line to a peripheral.

The receiver sections receive serial bits from a peripheral converts them into a parallel
word and transfers the word to the microprocessor. The modern control is used to establish
data communication through modems over telephone lines.

The 8251 is a complete device, capable of performing various functions. The

asynchronous mode is often used for data communication between the microprocessor and
serial peripherals such as terminals and floppy disks.

READ/WRITE CONTROL LOGIC AND REGISTER

This section includes R/W control logic, six input signal control logic and three
buffer registers: data register, control register and status register, The input signals to the
control logic are as follows.

INPUT SIGNALS:
___
CS – Chip Select:
 When the signal goes low, the 8251 A is selected by the microprocessor for
communication. This is usually connected to a decoded address bus.
_
C/D – Control / Data:

___ When this signal is high, the control register and the status register are differentiated by
WR and RD signals, respectively.
___
WR – WRITE:

When this signal goes low, the microprocessor either writes in the control register or
sends output to the data buffer. This is connected to IOW or MEMW.

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___
RD _ READ:

When this signal goes low, the microprocessor either reads a status from the status
register can accept (inputs) data from the data buffer. This is connected to either IOR or
MEMB.

RESET – Reset:

A high on this input reset the 8251 A and forces it into the idle node.

CLK – Clock:

This is the clock input, usually connected to the system clock. This clock does not
control either the transmission on the reception rate - the clock is necessary for communication
with microprocessor.

CONTROL REGISTER:

This is 16 bit register for a control word consists of two independent bytes. The first
byte called the “mode instruction” (word) and the second byte is called “command
instruction”. This register can be accessed as an output port when the C/D pin is high.

STATUS REGISTER:

This input register checks the ready status of a peripheral. This register is addressed as
an input part. When the C/D pin is high. It has same part address as the control registers.

DATA BUS BUFFER:

This 3-state bidirectional, 8-bit buffer is used to interface the 8251A to the system data
bus. Data is transmitted or received by the buffer upon execution of input or output
 instructions of the CPU. Control works, command words and status information are also
transferred through the data bus buffer. The command status, Data-in and data-out registers
are separate, 8-bit registers communicating with the system bus through the Data Bus Buffer.

This functional block accepts inputs from the system Control bus and generates control
signals for overall device operation. It contains the Control Word Register and Command
Word Register that store the various control formats for the device functional definition.

MODEM CONTROL:

The 8251A has a set of control inputs and outputs that can be used to simplify the
interface to almost any modem. The modem control signals are general purpose in nature and
can be used for functions other than modem control if necessary.
____
DSR (Data Set Ready):
____
The DSR input signal is a general-purpose, 1-bit inverting input port. Its condition can
be tested by the CPU using a Status Read operation. The DSR input is normally used to test
modem conditions such as Data Set Ready.

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____
DTR (Data Terminal Ready) :
___
The DTR output signal is a general-purpose, 1-bit inverting output port. I t can be set
“low” by programming the appropriate bit in the Command Instruction word. The DTR output
signal is normally used for modem control such as Data Terminal Ready.
___
RTS (Request to Send) :

The RTS output signal is a general-purpose, 1-bit inverting output port. It can be set
“low” by programming the appropriate bit in the Command Instruction word. The RTS output
signal is normally used for modem control such as Request To Send..
____
CTS (Clear to Send) :

A “low” on this input enables the 8251A to transmit serial data if the Tx Enable bit n
the command byte is set to a “one”. If either a Tx Enable off or CTS off condition occurs
while the Tx is in operation, the Tx will transmit all the data in the Usart, written prior to Tx
Disable command before shutting down.

TRANSMITTER SECTION
 The transmitter accepts parallel data from the microprocessor and converts them into
serial data. It has two registers a buffer to hold eight bits and a output register to convert eight
bits into a stream of serial bit.
The microprocessor writes a bytes in the buffer registers. This section transmits data on
the TxD with the approvable froming bits (start and stop). Three output signals and one input
signal are associated with the transmitter section.

TxD- TRANSMITTER DATA:

Serial bits are transmitted on this line.

___
TxC- TRANSMITTER CLOCK:

This input signal controls the rate at which bits are transmitted by the USART. The
clock frequency can be 16 or 64 times the board.

TxRDY- TRANSMITTER READY:

This is an output signal, it is high, it indicates that buffer registers is empty and the
USART is ready to accept a byte. It can be used either to interrupt the microprocessor or to
indicate the status. This signal is reset when a data byte is loaded into the buffer.

TxE- TRANSMITTER EMPTY:

This is an output signal. On this line indicates that the output registers is empty. This
signal is reset when a byte is transferred from the buffer to the output register.

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RECEIVER SECTION:

The receiver accepts the serial data on the RxD line from a peripheral and converts
them into parallel data. This section has two registers and the buffer registers.

When the RxD lines goes low, the control logic assumes it is a start bit, waits for half a
bit time and samples the line again. If the line is still low, the input register accepts the
following bits, forms a character and loads it into the buffer register.

Subsequently, the parallel byte is transferred to the microprocessor when requested. In

the asynchronous mode, the input signals and output signals are necessary.

RxD- RECEIVER DATA:

 Bits are received serially on this line and converted into a parallel byte in the input
register.
____
RxC – RECEIVER CLOCK:

This is a clock signal that controls the rate of which bits are received by the USART. In
the asynchronous mode, the clock can be set to 1, 16 or 64 times are based.

RxRDY – RECEIVER READY:

This is an output signal. It goes high when the USART has a character in the buffer
register and is ready to the microprocessor. This line can be used either to indicate the status or
the interrupt in the microprocessor.

INITIALISING THE 8251A

To implement serial communication, the MPU must inform the 8251A of all details, such
as mode, baud, Stop bits, parity, etc. Therefore, prior to data transfer, a set of control words
must be loaded into the 16-bit control register of the 8251A. In addition, the MPU must check
the readiness of a peripheral by reading the status register. The control words are divided into
two formats: mode words and command words. The mode word specifies the general
characteristics of operation, the command word enables data transmission and/or reception, and
the status word provides the information concerning register status and transmission errors.

To initialize the 8251A in the asynchronous mode, a certain sequence of control words
must be followed. After a Reset operation, a mode word must be written in the control register
followed by a command word. Any control word written into the control register immediately
after a mode word will be interpreted as a command word; that means a command word can be
changed anytime during the operation. However, the 8251A should be reset prior to writing a
new mode word, and it can be reset by using the Internal Reset bit (D6) in the command word.

Page No:
RESULT:

Thus the entire structure of 8251A- Programmable Communication Interface has been studied.
 PIN DIAGRAM

D2 D1

D3 D0

RxD Vcc

GND RxC

D4
I DTR
C
D5 RTS
8
D6 DSR
2
D7 5 RESET
1
TxC CLK
A
WR TxD

CS Tx EMPTY

CD CTS

RD SYDET/BD

RxRDy TxRDY
Page No:
STUDY OF 8253 PROGRAMMABLE INTERVAL TIMER
AIM:

To study the entire structure of programmable interval timer (8253).

INTRODUCTION:

The 8253 programmable interval timer/counter is functionally similar to the software

designed counters and timers. It generates accurate time delays and can be used for
applications such as a real-time clock, an event counter, a digital one shot, a square-wave
generator, and a complex waveform generator.

The 8253 includes three identical 16-bit counter that can be operate independently in
any one of the six modes. It is packaged in a 24-pin DIP and required a single +5V power
supply. To operate a counter, a 16-bit count is loaded in its register and, on command, begins
to decrement the count until it reaches 0. At the end of the count, it generates a pulse that can
be used to interrupt the MPU. The counter can count either in binary or BCD. In addition, a
count can be read by the MPU while the counter is decrementing.

PIN DESCRIPTION:

D7 – D0 :
Bi-directional three state data bus lines, connected to system data bus.

CLK 0 :
Clock input of Counter 0

OUT 0 :
Output of Counter 0.

GATE 0:
Gate input of Counter 0.

GND :
Power supply connection.

VCC :
A 5V power supply connection.
___
WR :
This input is low during CPU write operations.
___
RD :
This input is low during CPU read operations.
__
CS : __ ___
 Page No:

A1, A0 :
Used to select one of the three Counters or the Control Word Register for read
or write operations. Normally connected to the system address bus.

A1 A0 Selects
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register

CLK 2 :
Clock input of Counter 2.

OUT 2 :
Output of Counter 2.

GATE 2 :
Gate input of Counter 2.

CLK 1 :
Clock input of Counter 1.

GATE 1 :
Gate input of Counter 1.

OUT 1:
Output of Counter 1.

ARCHITECTURE OF 8253:

 DATA BUS BUFFER:

This 3-state, bi-directional, 8-bit buffer is used to interface the 8253 to the system bus,
Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions.

 READ/WRITE LOGIC :

The Read/Write Logic accepts inputs from the system bus and generates control signals
for the other functional blocks of the 8253. A1 and A0 select one of the three counters or the
Control Word Register to be read from/written into.

A ``low'' on the RD input tells the 8253 that the CPU is reading one of the counters.
 A ``low'' on the WR input tells the 8253 that the CPU is writing either a Control Word
or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored
unless the 8253 has been selected by holding CS low.

 CONTROL WORD REGISTER :

The Control Word Register is selected by the Read/Write Logic when

A1,A0 = 11. If the CPU then does a write operation to the 8253, the data is stored in the
Page No:

Control Word Register and is interpreted as a Control Word used to define the operation of
the Counters. The Control Word Register can only be written to; status information is
available with the Read-Back Command.

 COUNTER 0, COUNTER 1, COUNTER 2 :

The Counters are fully independent. Each Counter may operate in a different Mode.
The Control Word Register is shown in the figure; it is not part of the Counter itself, but
its contents determine how the Counter operates.The status register, contains the current
contents of the Control Word Register and status of the output and null count flag.

The actual counter is labelled CE. It is a 16-bit presettable synchronous down

counter. OLM and OLL are two 8-bit latches. OL stands for ``Output Latch''; the subscripts M
and L stand for ``Most significant byte'' and ``Least significant byte'‘ respectively.

Both are normally referred to as one unit and called just OL. These latches normally
``follow'‘ the CE, but if a suitable Counter Latch Command is sent to the 8253, the latches
``latch'' the present count until read by the CPU and then return to ``following'' the CE.

One latch at a time is enabled by the counter's Control Logic to drive the internal bus.
This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE
itself cannot be read; whenever you read the count, it is the OL that is being read.

Similarly, there are two 8-bit registers called CRM and CRL (for ``Count Register'').
Both are normally referred to as one unit and called just CR.

When a new count is written to the Counter, the count is stored in the CR and later
transferred to the CE. The Control Logic allows one register at a time to be loaded from the
internal bus. Both bytes are transferred to the CE simultaneously.

CRM and CRL are cleared when the Counter is programmed. In this way, if the
Counter has been programmed for one byte counts (either most significant byte only or least
significant byte only) the other byte will be zero.

Note that the CE cannot be written into, whenever a count is written, it is written into
 the CR.

PROGRAMMING THE 8253 :

Counters are programmed by writing a Control Word and then an initial count.
The Control Words are written into the Control Word Register, which is selected when
A1,A0 = 11. The Control Word itself specifies which Counter is being programmed.

 Control Word Format:

A1,A0 = 11, CS = 0, RD = 1, WR = 0.
By contrast, initial counts are written into the Counters, not the Control Word Register. The
A1,A0 inputs are used to select the Counter to be written into. The format of the initial count
is determined by the Control Word used.

Page No:

 Write Operations:

The programming procedure for the 8253 is very flexible. Only two conventions
need to be remembered:
1) For each Counter, the Control Word must be written before the initial count is written.
2) The initial count must follow the count format specified in the Control Word (least
significant byte only, most significant byte only, or least significant byte and then
most significant byte).

Since the Control Word Register and the three Counters have separate addresses
(selected by the A1,A0 inputs), and each Control Word specifies the Counter it applies to
(SC0,SC1 bits), no special instruction sequence is required.

A new initial count may be written to a Counter at any time without affecting the
Counter's programmed Mode in any way. Counting will be affected as described in the
Mode definitions. The new count must follow the programmed count format.

If a Counter is programmed to read/write two-byte counts, the following precaution

applies: A program must not transfer control between writing the first and second byte
to another routine which also writes into that same Counter. Otherwise, the Counter will be
loaded with an incorrect count.

 Read Operations:

It is often desirable to read the value of a Counter without disturbing the count in
progress. This is easily done in the 8253.
 • There are three possible methods for reading the counters:
a simple read operation, the Counter Latch Command, and the Read-Back Command.

• Each is explained below. The first method is to perform a simple read operation. To
read the Counter, which is selected with the A1, A0 inputs, the CLK input of the
selected Counter must be inhibited by using either the GATE input or external logic.

• Otherwise, the count may be in the process of changing when it is read, giving an
undefined result.

• The second method uses the ``Counter Latch Command''. Like a Control Word, this
command is written to the Control Word Register, which is selected when A1,A0 =
11. Also like a Control Word, the SC0, SC1 bits select one of the three Counters, but
two other bits, D5 and D4, distinguish this command from a Control Word.

• The selected Counter's output latch (OL) latches the count at the time the Counter Latch
Command is received. This count is held in the latch until it is read by the CPU (or
until the Counter is reprogrammed).

• The count is then unlatched automatically and the OL returns to ``following'' the
counting element (CE).

• This allows reading the contents of the Counters ``on the fly'' without affecting counting
in progress.

• Multiple Counter Latch Commands may be used to latch more than one Counter. Each
Page No:

latched Counter's OL holds its count until it is read.

• Counter Latch Commands do not affect the programmed Mode of the Counter in any
way.

• If a Counter is latched and then, some time later, latched again before the count is read,
the second Counter Latch Command is ignored. The count read will be the count at
the time the first Counter Latch Command was issued.

• With either method, the count must be read according to the programmed format;
specifically, if the Counter is programmed for two byte counts, two bytes must be read.
The two bytes do not have to be read one right after the other, read or write or
programming operations of other Counters may be inserted between them.

• Another feature of the 8253 is that reads and writes of the same Counter may be
interleaved.
• Read-back command: The third method uses the Read-Back Command. This command
allows the user to check the count value, programmed Mode, and current states of the
OUT pin and Null Count flag of the selected counter (s).

• The command is written into the Control Word Register. The command applies to the
counters selected by setting their corresponding bits D3, D2, D1 = 1.

• The read-back command may be used to latch multiple counter output latches (OL) by
setting the COUNT bit D5 = 0 and selecting the desired counter (s). This single
command is functionally equivalent to several counter latch commands, one for each
counter latched.

• Each counter's latched count is held until it is read (or the counter is reprogrammed).

• The counter is automatically unlatched when read, but other counters remain latched until
they are read. If multiple count read-back commands are issued to the same counter
without reading the count, all but the first are ignored; i.e., the count which will be read
is the count at the time the first read-back command was issued.

• The read-back command may also be used to latch status information of selected counter
(s) by setting STATUS bit D4 = 0. Status must be latched to be read; status of a counter
is accessed by a read from that counter.

• Bits D5 through D0 contain the counter's programmed Mode exactly as written in the last
Mode Control Word. OUTPUT bit D7 contains the current state of the OUT pin.

• This allows the user to monitor the counter's output via software, possibly eliminating
some hardware from a system. NULL COUNT bit D6 indicates when the last count
written to the counter register (CR) has been loaded into the counting element (CE).

• The exact time this happens depends on the Mode of the counter and is described in the
Mode Definitions, but until the count is loaded into the counting element (CE), it can't
be read from the counter.
AIM:
To write a program to perform the operation of a stepper motor using interface.

EQUIPMENTS REQUIRED:
1. 8085 microprocessor kit
2. Stepper motor interfacing.

ALGORITHM:
(i) Load HL pair and move 20 to C register.
(ii) Call the subroutine rotate.
(iii) Decrement the C register, check if C is zero. If it is not go to the loop.
(iv) Call the subroutine for stop.
(v) Step 1-4 is forward motion and repeat the step 1-4 for reverse rotation.
(vi) Jump to step1.

Subroutine for ROTATE:

(i) Move 04 to B register and M to A.
(ii) Output the data from the port C0.
(iii) Load DE pair as 0303.
(iv) Decrement the DE pair, move E to A and move E to A register.
(v) OR A with D and check for zero go to loop.
(vi) Decrement B and check for zero go to loop.
(vii) Return to main program.

Subroutine for STOP

(i) Load DE pair as FFFF.
(ii) Decrement the DE pair.
(iii) Move E to A and OR A with D.
(iv) Jump on no zero and continue the loop.
(v) Return to main program.
 Page No:

ADDRESS LABEL MNEMONICS OPCODE COMMENTS

4100 Start: MVI C,20 0E,20 Move 20 to C register

4102 Forw: LXI H ,FOR 21,3F,41 Load the HL pair
4105 CALL ROT CD,21,41 Call the subroutine
4108 DCR C 00 Decrement the C register
4109 JNZ FORW C2,02,41 If Z ≠ 0 then goto loop
410C CALL STOP CD,35,41 Call the subroutine
410F MVI C,20 0E,20 Move 20 to C register
4111 REV: LXI H,REV 21,43,41 Load the HL pair
4114 CALL ROT CD,21,41 Call the subroutine
4117 DCR C 0D Decrement the C register
4118 JNZ RE C2,11,41 If Z≠0 then goto loop
411B CALL STOP CD,35,41 Call the subroutines
411E JMP START C3,00,41 Jump to start
4121 ROT: MVI B,04 06,04 Move 04 to B register
4123 L1: MOV A,M 7E Move M to accumulator
4124 OUT C0 D3,C0 Output the data at C0
4126 LXI D 03,03 71,03,03 Load DE as 0303 H
4129 L2: DCX D 1B Decrement the DE pair
412A MOV A,E 7B Move E to A
412B OR A,D B2 OR with A & D
412C JNZ L2 C2,29,47 If Z≠0 then goto loop
412F INX H 23 Increment the pair HL
4130 DCR B 05 Decrement B register
4131 JNZ L1 C2,23,41 Jump if no zero
4134 RET C9 Return
4135 STOP: LXI D FF FF 11,FF,F Load the DE pair
4138 X: DCX D 1B Decrement the DE pair
4139 MOV A,E 7B Move E to A register
413A ORA D B2 OR A with D
413B JNZ X C9 If Z≠0 then goto X
413E RET C9 Return to main
FOR: 09,05,06,0A Look up table

STEPPER MOTOR
RESULT:

Thus the stepper motor was rotated in forward and reverse direction.