Unit: FABRICAION OF MOSFET

Integrated Circuits (IC) Technology:

An integrated circuit is a miniaturized low-cost electronic circuit consisting of

active and passive components fabricated together on a substrate.
Why we need this integrated circuit?

 miniaturization,
 Batch Processing Results in cost reduction
 Improved system reliability due to avoid of soldering
 Better functional density
 Matched devices
 Increased operation speed
 Significant reduction in the power consumption

Basically integrated circuits can be divided into two classes:

 Linear integrated circuits: IP/OP characteristics are linear Eg. OP-

Amp

 Digital integrated circuits: The circuit is either in ON state or

OFF state and not in between the 2; that means that either it can be 1 or
it can be 0.

 Hybrid or Multi chip Integrated Circuit:

Monolithic integrated circuits

“Mono” meaning a single one and “lithic” comes from the Lithos meaning
stone. Monolithic comes from the Greek words one is mono and second is
lithos; that means, single and stone; that means, that if you carve a single stone
to a sculpture, it is monolithic.

The monolithic ICs refer to a single stone or a single crystal: ingle crystal in
this monolithic integrated circuit is nothing but a silicon chip as a
semiconductor material and on top of this semiconductor material, we are
using all the passive and active components which are interconnected.

Monolithic ICs are treated as best mode of manufacturing:

 It can be made identical

 Higher reliability
 Low cost
 Manufactured in bulk
Limitations:

 Low power rating

 Isolation on IC is poor
 Inductor can’t be fabricated
 Passive components within IC will have lower values and external
connection is required from the IC PIN to acquire higher values

Thin and thick film integrated circuits:

Thin film technology refers fabrication by depositing thin films of conducting

or semiconducting materials on the surface of glass or ceramic base.

 Larger than monolithic ICs but smaller than discrete circuits.

 It can be used in higher power applications.
 It cannot be integrated with diodes and transistors
 But resistors and capacitors can be integrated.

Processes Flow:

 Oxidation
 Thermal oxidation (physical vapour deposition)
 Plasma Enhanced chemical vapour deposition.
 Deposition
 PVD
 Thermal
 E beam evaporation
 Sputtering
 CVD
 LPCVD
 PECVD
 Photolithography
 Diffusion/Ion Implantation
 Ion Implantation
 Diffusion
Credit Rajesh Kumar Sharma
CMOS Processes Flow:

1.

2. Oxidation

Grow SiO2 on top of Si wafer

– 900℃ - 1200℃ with H2O or O2 in an oxidation furnace

3. Photoresist

Spin on photoresist

– Photoresist is a light-sensitive organic polymer

– Softens where exposed to light

4. Lithography

Expose photoresist through n-well mask Strip off exposed photoresist

5. Etch
Etch oxide with hydrofluoric acid (HF)
Only attacks oxide where resist has been exposed

6. Strip Photoresist Strip off remaining photoresist

– Old days we used a mixture of nitric and sulphuric acids called

piranha etch

– Now we use a plasma etch which is much safer (and greener).

Necessary so resist doesn’t melt in the next step
7. n-Well
n-Well formed with diffusion or ion implant Diffusion

– Place wafer in furnace with Arsine (AsH3) gas

– Heat until As atoms diffuse into exposed Si

8. Ion Implantation

–Blast wafer with beam of As ions

– Ions blocked by SiO2, only enter exposed Si

9. Strip Oxide
- Strip off the remaining oxide using HF Back to bare wafer with n-
well Subsequent steps involve similar series of steps
10. Polysilicon
-Grow/deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of Si
layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

11. Polysilicon Cont…

- Patterning
Use same lithography process to pattern polysilicon
12. Self-Aligned Process
- Use oxide and masking to expose where n+ dopants should be
diffused or implanted
- N-diffusion forms nMOS source, drain, and n-well contact

13. N-diffusion
- Pattern oxide and form n+ regions
- Self-aligned process - gate blocks diffusion
- Polysilicon is better than metal for self-aligned gates because it
doesn’t melt during later processing
 14. Strip off oxide to complete patterning step

15. P-Diffusion
- Similar set of steps form p+ diffusion regions for pMOS source
and drain and substrate contact

Contacts….
- Now we need to wire together the devices Cover chip with thick field
oxide
- Etch oxide where contact cuts are needed
 16. Metallization
- Sputter on Aluminium over whole wafer
- Pattern to remove excess metal, leaving wires

Layout design Rule:

Motivation:

In VLSI design, as processes become more and more complex, need for the
designer to understand the intricacies of the fabrication process and interpret
the relations between the different photo masks. Therefore, a set of layout
rules, also called design rules, has been defined. They act as an interface or
communication link between the circuit designer and the process engineer
during the manufacturing phase.

Objective:

The objective associated with layout rules is to obtain a circuit with optimum
yield (functional circuits versus non-functional circuits) in as small as area
possible without compromising reliability of the circuit. Generally, they are a
compromise between yield and performance without compromising reliability
of the circuit.

So the need of design rules arises due to manufacturing problems like

  Photo resist shrinkage, tearing.
 Variations in material deposition, temperature and oxide thickness.
 Impurities.
 Variations across a wafer.

Layout design rules describe how small features can be engraved and how
closely they can be put together without sacrificing reliably in a particular
manufacturing process,

The design rules primary address two issues:

1. The geometrical reproduction of features that can be reproduced by the

mask making and lithographical process, and

2. The interaction between different layers.

Types of Design Rules

1. Scalable Design Rules (e.g. SCMOS, λ-based design rules)

2. Absolute Design Rules (e.g. μ-based design rules ) : Micron rules, in
which the layout constraints such as minimum feature sizes and
minimum allowable feature separations are stated in terms of absolute
dimensions in micrometers,

1.Scalable Design Rules (e.g. SCMOS, λ-based design rules)

Mead and Conway [Mead80] popularized scalable design rules based on a

single parameter, λ that characterizes the resolution of the process.

λ is generally half of the minimum drawn transistor channel length (feature

size).

This length (feature size) is the distance between the source and drain of a
transistor and is set by the minimum width of a polysilicon wire.

Drawback:

 Lambda-based rules are necessarily conservative because they round up

dimensions to an integer multiple of λ
 Most of the submicron CMOS process design rules do not lend
themselves to straightforward linear scaling. The use of λ-based design
rules must therefore be handled with caution in sub-micron geometries
Advantage:

 However, they make scaling layout trivial

 The same layout can be moved to a new process simply by specifying a
new value of Q

The MOSIS (MOS Implementation System) service is a low-cost prototyping

service has developed a set of scalable lambda-based design rules that covers a
wide range of manufacturing processes. The rules describe the minimum width
to avoid breaks in a line, minimum spacing to avoid shorts between lines, and
minimum overlap to ensure that two layers completely overlap.