Data Flow Modelling

Data Flow Modelling

Module 3

Amacdalino2020 SY 2020- 2021 CompEng 314 – Introduction to HDL

 Data Flow Modelling

Table of Contents
Introduction ............................................................................................................................................... 1
Learning Outcome ................................................................................................................................... 1
Learning Content...................................................................................................................................... 1
Data Flow Modelling ............................................................................................................................. 2
A. Continuous Assignments .......................................................................................................... 2
Implicit Continuous Assignment.................................................................................................... 2
B. Delays ......................................................................................................................................... 3
Regular Assignment Delay ............................................................................................................ 3
Implicit Continuous Assignment Delay ........................................................................................ 4
Net Declaration Delay................................................................................................................... 5
C. Expressions, Operators, and Operands .................................................................................. 6
Expressions ...................................................................................................................................... 6
Operands ........................................................................................................................................ 7
Operators ........................................................................................................................................ 7
D. Example ..................................................................................................................................... 8
Dataflow 4-to-1 Multiplexer (Using Logic Equations) .................................................................. 8
Teaching and Learning Activities.......................................................................................................... 10
Recommended Learning Materials and Resources ........................................................................... 10
Assessment Task ...................................................................................................................................... 10

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 Data Flow Modelling

Module 3 - Data Flow Modelling

Introduction
This module introduces VHDL programming using the Data Flow Model. It presents
continuous assignments including different types of delays, expressions, operators and
operands. Examples are also provided.

Learning Outcome
At the end of the lesson, you are expected to:

• Describe the continuous assignment (assign) statement, restrictions on the assign

statement, and the implicit continuous assignment statement.
• Explain assignment delay, implicit assignment delay, and net declaration delay for
continuous assignment statements.
• Define expressions, operators, and operands.
• List operator types for all possible operations-arithmetic, logical, relational, equality,
bitwise, reduction, shift, concatenation, and conditional.
• Use dataflow constructs to model practical digital circuits in Verilog.

Learning Content

Data Flow Modelling

A. Continuous Assignments
Implicit Continuous Assignment

B. Delays
Regular Assignment Delay
Implicit Continuous Assignment Delay
Net Declaration Delay

C. Expressions, Operators, and Operands

Expressions
Operands
Operators

D. Example
Dataflow 4-to-1 Multiplexer (Using Logic Equations) 8

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 Data Flow Modelling

Data Flow Modelling

• provides the means of describing combinational circuits by their function rather than
by their gate structure
• describes hardware in terms of the flow of data from input to output
• provides a powerful way to implement a design
• uses a number of operators that act on operands to produce the desired results
• Example description of AND gate using dataflow:
module and_gate(a,b,out);
input a,b;
output out;

assign out = a&b;

endmodule
• In the above code, we executed the functionality of the AND gate with the help of
the AND (&) operator. That is what dataflow modeling is about. It utilizes operators
that act on operands and gives the desired relationship between output and input.

A. Continuous Assignments
• the most basic statement in dataflow modeling, used to drive a value onto a net
• replaces gates in the description of the circuit and describes the circuit at a higher
level of abstraction.
• A continuous assignment statement starts with the keyword assign.

//Syntax of assign statement in the simplest form

< continuous_assign >

: : = assign < drive_strength > ? < delay > ? < list_of_assignments > ;

Example of Continuous Assignment

Continuous assign out is a
net. i1 and i2 are nets. assign out = i1 & i2 ;

Concatenation. Left-hand side

assign { c_out , sum[ 3 : 0 ] } = a [ 3 : 0 ] + b [ 3 :
is a concatenation of a scalar net
0 ] + c_in ;
and a vector net

Implicit Continuous Assignment

Instead of declaring a net and then writing a continuous assignment on the net.
Verilog provides a shortcut by which a continuous assignment can be placed on a
net when it is declared. There can be only one implicit declaration assignment per
net because a net is declared only once.

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 Data Flow Modelling

Example of Implicit Continuous Assignment

Regular continuous
assignment wire out ;

assign out = in1 & in2 ;

Same effect is achieved by an

Implicit continuous assignment
wire out = in1 & in2 ;

B. Delays
Delay value control the time between the change in a right-hand-side operand and
when the new value is assigned to the left-hand-side.

Regular Assignment Delay

The first method is to assign a delay value in a continuous assignment statement.
The delay value is specified after the keyword assign.

Ex1. Regular Assignment Delay program

1. This example shows inertial delay. The waveform is generated by simulating

the assign statement. It shows the delay on signal out. Note the following
changes. When signal in1 and in2 go high at time 20, out goes to a high
10-time units later (time = 30).
2. When in1 goes to low at 60, out changes to low at 70.
3. However, in1 changes to high at 100, but it goes down to low before10
time units have elapsed.
4. Hence, at the time of recompilation, 10 units after time 100, in1 is 0. Thus,
out gets the value 0. A pulse of width less than the specified assignment
delay is not propagated to the output.
i. Verilog Code

Declaration
module regular_delay (out, in1, in2);
I/O port
output out;
input in1, in2;

Delay in a continuous
assign #10 out = in1 & in2;
endmodule

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 Data Flow Modelling

ii. Test Stimulus Code module stimulus;

wire OUT;
reg IN1, IN2;

initial
begin
Input test value IN1 = 0; IN2= 0;
#20 IN1=1; IN2= 1;
#40 IN1 = 0;
#40 IN1 = 1;
#5 IN1 = 0;
#150 $stop;
end

initial
Shown the result $monitor("out", OUT, "in1", IN1, "in2",
IN2);

Call regular_delay module regular_delay rd1(OUT, IN1, IN2);

endmodule

iii. Simulation Waveform

Implicit Continuous Assignment Delay

An equivalent method is using an implicit continuous assignment to specify
both a delay and an assignment on the net.

Ex2. Implicit Continuous Assignment

i. Verilog Code
module implicit_delay (out, in1, in2);

output out;
Delay in a continuous assign
input in1, in2;

wire #10 out = in1 & in2;

endmodule

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 Data Flow Modelling

ii. Test Stimulus Code

module stimulus;

wire OUT;
reg IN1, IN2;

Input test value initial

begin
IN1 = 0; IN2= 0;
#20 IN1=1; IN2= 1;
#40 IN1 = 0;
#40 IN1 = 1;
#5 IN1 = 0;
#150 $stop;
end
Shown the result
initial
$monitor("out", OUT, "in1", IN1, "in2",
IN2);
Call regular_delay module

implicit_delay rd1(OUT, IN1, IN2);

endmodule
iii. Simulation Waveform

Net Declaration Delay

A delay can be specified on a net when it is declared without putting a continuous
assignment on the net. If a delay is specified on a net out, then any value change
applied to the net out is delayed accordingly. Net declaration delays can also be
used in gate-level modeling.
Ex3. Net Declaration Delay Program

i. Verilog Code module implicit_delay (out, in1, in2);

output out;

input in1, in2;

No Delay in a assign out = in1 & in2;

continuous
assignment endmodule

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ii. Test Stimulus Code

Declare the delay module stimulus;

on the net.
wire #10 OUT;
reg IN1, IN2;

initial
Input test value begin
IN1 = 0; IN2= 0;
#20 IN1=1; IN2= 1;
#40 IN1 = 0;
#40 IN1 = 1;
#5 IN1 = 0;
#150 $stop;
end

Shown the result initial

$monitor("out", OUT, "in1", IN1, "in2",
IN2);
Call net_declare module
net_delare rd1(OUT, IN1, IN2);

endmodule

iii. Simulation Waveform

C. Expressions, Operators, and Operands

Dataflow modeling describes the design in terms of expressions instead of primitive
gates. expressions, operators, and operands form the basis of dataflow modeling.

Expressions
Expressions are constructs that combine operators and operands to produce a result.

//Examples of expressions . Combine operators and operands a ^ b

addr1[20:17] + addr2[20:17]

in1 | in2

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Operands
Operands can be any one of the data types. Some constructs will take only certain
types of operands.

integer count , final_count ;

count is an
integer operand final_count = count + 1 ;

a and b are real a , b , c ;

real operands
c=a–b;

Operators
The operator act on the operands to produce desired results. Verilog provides
various types of operators.

Operator Operator Operation Number of

Type Symbol Performed Operands
Arithmetic * Multiply Two
/ Divide Two
+ Add Two
- Subtract Two
% Modulus Two
Logical ! Logical Negation One
&& Logical AND Two
|| Logical OR Two
Relational > Greater Than Two
< Less Than Two
>= Greater Than or Equal Two
<= Less Than or Equal Two
Equality == Equality Two
!= Inequality Two
=== Case Equality Two
!== Case Inequality Two
Bitwise ~ Bitwise Negation One
& Bitwise AND Two
| Bitwise OR Two
^ Bitwise XOR Two
^~ or ~^ Bitwise XNOR Two
Reduction & Reduction AND One
~& Reduction NAND One
| Reduction OR One
~| Reduction NOR One
^ Reduction XOR One
^~ or ~^ Reduction XNOR One
Shift >> Right Shift Two
<< Left Shift Two
Concatenation { } Concatenation Any Number
Replication {{}} Replication Any Number
Conditional ?: Condition Three

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 Data Flow Modelling

D. Example

Dataflow 4-to-1 Multiplexer (Using Logic Equations)

i. Verilog Code
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

Port declarations from the

output out;
I/O diagram
input i0, i1, i2, i3;

input s1, s0;

Set assignment function

assign out = (~s1 & ~s0 & i0) |

(~s1 & s0 & i1) |

(s1 & ~s0 & i2) |

(s1 & s0 & i3) ;

endmodule

ii. Test Stimulus Code

Define the stimulus module module stimulus;

(no ports)
reg IN0, IN1, IN2, IN3;
Declare variables to be reg S1, S0;
Connected to the inputs
wire OUTPUT;
Declare the output wire
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1,
Instantiated the S0);
multiplexer
initial
begin
Stimulate the inputs
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b,
Set input lines IN3= %b\n",IN0,IN1,IN2,IN3);

S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT =
Choose IN0 %b \n", S1, S0, OUTPUT);

S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT =
Choose IN1
%b \n", S1, S0, OUTPUT);

S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n",
S1, S0, OUTPUT); 8
 Data Flow Modelling

Choose IN2 S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT =
%b \n", S1, S0, OUTPUT);

Choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT =
%b \n", S1, S0, OUTPUT);

end

endmodule

iii. Simulation Waveform

iv. Simulation Result

Other examples will be uploaded.

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 Data Flow Modelling

Teaching and Learning Activities

• What is data flow modelling?

• What are continuous assignments?
• Define the different types of delays.
• Define expressions, operators, and operands.
• What are the nine types of operators? Differentiate each.

Recommended Learning Materials and Resources

• Digital Design with An Introduction to the Verilog HDL Fifth Edition by M. Morris Mano
and Michael D. Ciletti
• http://content.inflibnet.ac.in/data-server/eacharya-
documents/53e0c6cbe413016f23443704_INFIEP_33/5/LM/33-5-LM-V1-
S1__dataflowmodelingchep4.pdf
• https://technobyte.org/dataflow-modeling-verilog/

Assessment Task
***To be uploaded separately.

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