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Wallace Tree Encoder

The document discusses implementing an analog comparator digitally by cross-coupling two 3-input NAND gates. It then provides code and testbenches for a NAND gate, comparator, Wallace tree encoder, XOR gate, and XOR encoder. The next steps mentioned are to compare parameters like propagation delay and power consumption of the Wallace tree and XOR encoders to determine the better performance encoder for use in flash analog-to-digital converter designs.

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120 views13 pages

Wallace Tree Encoder

The document discusses implementing an analog comparator digitally by cross-coupling two 3-input NAND gates. It then provides code and testbenches for a NAND gate, comparator, Wallace tree encoder, XOR gate, and XOR encoder. The next steps mentioned are to compare parameters like propagation delay and power consumption of the Wallace tree and XOR encoders to determine the better performance encoder for use in flash analog-to-digital converter designs.

Uploaded by

jestinmary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digitally synthesized comparator

Analog comparator can be implemented by cross-coupling two 3-input NAND gates.

First step-3input NAND gate

Code

Testbench for NAND

Output waveform of NAND-3


Analog comparator

Code for comparator

Testbench for comparator


Output waveform of comparator
Wallace tree encoder

Implementation using verilog

 First step-Full adder


 Full adder testbench
Full adder output

Second step-Code for Wallace tree encoder


Testbench for Wallace tree
Wallace tree output(priority encoder output)

xor encoder
First step-xor gate

Testbench
Output waveform of xor

Code for xor-encoder


Testbench for xor encoder
Output of xor encoder
Encoder speed is a constraint in flash adc design,through our project we aim at finding fast encoder
circuit to be used in flash adc design. So as next step we have to compare both encoder parameters
like propagation delay,power consumption etc to find out better performance encoder.

At present we are studying Xilinx software that includes the provision for calculating different
parameters that are not supported in modelsim.

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