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Datasheet
Features
Order code VDS RDS(on) max. ID PTOT
( s )25 W
•
•
Outstanding dv/dt capability
Gate charge minimized
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• Very low intrinsic capacitances
TO-220FP • Very low RDS(on)
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• Extremely low trr
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Applications
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• Switching applications
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Description
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This device is N-channel Power MOSFET developed using UltraFASTmesh™
technology, which combines the advantages of reduced on resistance, Zener gate
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protection and very high dv/dt capability with an enhanced fast body-drain recovery
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STF5N52U
Product summary
1 Electrical ratings
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IDM (1) Drain current (pulsed) 17.6 A
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PTOT Total power dissipation at TC = 25 °C 25 W
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dv/dt (2) Peak diode recovery voltage slope 20 V/ns
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Insulation withstand voltage (RMS) from all three leads to external heat sink
VISO 2.5 kV
(t=1 s; TC=25 °C)
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2. ISD ≤ 4.4 A, di/dt ≤ 400 A/µs, VDS peak < V(BR)DSS, VDD = 80% V(BR)DSS
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Symbol Parameter Value Unit
Rthj-amb r o
Thermal resistance junction-ambient 62.5
°C/W
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Symbol Parameter Value Unit
IAR Avalanche current, repetitive or non-repetitive (pulse width limited by Tjmax) 4.4 A
EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 170 mJ
2 Electrical characteristics
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IDSS Zero gate voltage drain current VGS = 0 V, VDS = 525 V,
500 µA
TC = 125 °C(1)
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VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA 3 3.75 4.5 V
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Table 5. Dynamic
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Symbol Parameter Test conditions Min. Typ. Max. Unit
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Ciss Input capacitance - 529 - pF
Crss
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Reverse transfer capacitance - 13.4 - pF
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RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6 - Ω
let
Qg Total gate charge VDD = 416 V, ID = 4.4 A, - 16.9 - nC
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1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS
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inductive load switching and diode
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recovery times)
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1. Pulse width is limited by safe operating area
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%
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Table 8. Source drain diode
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Symbol
V(BR)GSO
Parameter
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Gate-source breakdown voltage
Test conditions
IGS = ± 1mA, ID = 0 V
Min.
30
Typ.
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Max.
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Unit
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The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In
this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the
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device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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Single pulse
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10-5 10-4 10-3 10
-2
10 -1 tp(s)
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Figure 3. Output characteristics
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(BR)
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Figure 9. Normalized gate threshold voltage vs
temperature
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Figure 10. Normalized on-resistance vs temperature
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Figure 11. Source-drain diode forward characteristics Figure 12. Maximum avalanche energy vs temperature
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3 Test circuits
Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior
VDD
12 V 47 kΩ
1 kΩ
100 nF
RL
2200
)
3.3
+ μF μF VDD
RG
VD
VGS
+
IG= CONST
100 Ω
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pulse width
VGS D.U.T. 2.7 kΩ
2200 VG
pulse width μF
47 kΩ
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1 kΩ
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AM01468v1 AM01469v1
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Figure 15. Test circuit for inductive load switching and
diode recovery times s o
Figure 16. Unclamped inductive load test circuit
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A A A L
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D VD
fast 100 µH
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G D.U.T. diode 2200 3.3
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S B 3.3 1000 µF VDD
B B
µF + µF VDD
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25 Ω D ID
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G D.U.T.
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RG S
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pulse width
D.U.T.
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AM01470v1
90% 90%
IDM
0 10%
AM01472v1
AM01473v1
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
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7012510_Rev_12_B
mm
Dim.
Min. Typ. Max.
A 4.4 4.6
B 2.5 2.7
D 2.5 2.75
E 0.45 0.7
F 0.75 1
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F1 1.15 1.70
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F2 1.15 1.70
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G 4.95 5.2
Pr
G1 2.4 2.7
H 10 10.4
L2
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L3 28.6
o le 30.6
L4
L5
9.8
2.9 b s 10.6
3.6
L6
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15.9 O 16.4
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9 9.3
Dia
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Revision history
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Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
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Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
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TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
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© 2019 STMicroelectronics – All rights reserved P
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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