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116 views13 pages

Obsolete Product(s) - Obsolete Product(s)

Uploaded by

Najeeb Ullah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 13

STF5N52U

Datasheet

N-channel 525 V, 1.25 Ω typ., 4.4 A, UltraFASTmesh™


Power MOSFET in a TO-220FP package

Features
Order code VDS RDS(on) max. ID PTOT

STF5N52U 525 V 1.50 Ω 4.4 A

( s )25 W



Outstanding dv/dt capability
Gate charge minimized
c t
u
3
2

d
1
• Very low intrinsic capacitances
TO-220FP • Very low RDS(on)
r o
D(2)
• Extremely low trr

e P
Applications
o l et
G(1)
• Switching applications

b s
Description
- O
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This device is N-channel Power MOSFET developed using UltraFASTmesh™
technology, which combines the advantages of reduced on resistance, Zener gate
S(3) AM15572v1_no_tab

c
diode. t(
protection and very high dv/dt capability with an enhanced fast body-drain recovery

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O b Product status link

STF5N52U

Product summary

Order code STF5N52U


Marking 5N52U
Package TO-220FP
Packing Tube

DS12943 - Rev 1 - March 2019 www.st.com


For further information contact your local STMicroelectronics sales office.
STF5N52U
Electrical ratings

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VGS Gate- source voltage ±30 V

ID Drain current (continuous) at TC = 25 °C 4.4


A
ID Drain current (continuous) at TC= 100 °C 2.8

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t(
IDM (1) Drain current (pulsed) 17.6 A

uc
PTOT Total power dissipation at TC = 25 °C 25 W

od
dv/dt (2) Peak diode recovery voltage slope 20 V/ns

Pr
Insulation withstand voltage (RMS) from all three leads to external heat sink
VISO 2.5 kV
(t=1 s; TC=25 °C)

Tstg Storage temperature range


t e -55 to 150 °C
Tj Operating junction temperature range

o le
ESD

1. Pulse width limited by safe operating area.


b s
Gate-source human body model (R = 1.5 kΩ, C = 100 pF) 2.8 kV

O
2. ISD ≤ 4.4 A, di/dt ≤ 400 A/µs, VDS peak < V(BR)DSS, VDD = 80% V(BR)DSS

-
( s )
c t Table 2. Thermal data

du
Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case 5

Rthj-amb r o
Thermal resistance junction-ambient 62.5
°C/W

e P
le t Table 3. Avalanche characteristics

so
Ob
Symbol Parameter Value Unit

IAR Avalanche current, repetitive or non-repetitive (pulse width limited by Tjmax) 4.4 A

EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 170 mJ

DS12943 - Rev 1 page 2/13


STF5N52U
Electrical characteristics

2 Electrical characteristics

(TC = 25 °C unless otherwise specified).

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 525 V

VGS = 0 V, VDS = 525 V


s )
t(
10 µA

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IDSS Zero gate voltage drain current VGS = 0 V, VDS = 525 V,
500 µA
TC = 125 °C(1)

IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V


o d ±10 µA

r
eP
VGS(th) Gate threshold voltage VDS = VGS, ID = 50 µA 3 3.75 4.5 V

RDS(on) Static drain-source on-resistance

1. Defined by design, not subject to production test.


l e t
VGS = 10 V, ID = 2.2 A 1.25 1.50 Ω

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b
Table 5. Dynamic

O
)-
Symbol Parameter Test conditions Min. Typ. Max. Unit

t(s
Ciss Input capacitance - 529 - pF

Coss Output capacitance VDS= 25 V, f = 1 MHz, VGS = 0 V - 71 - pF

Crss

d uc
Reverse transfer capacitance - 13.4 - pF

Coss eq. (1)


r o
Equivalent output capacitance VDS = 0 V to 420 V, VGS = 0 V - 11 - pF

eP
RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6 - Ω

let
Qg Total gate charge VDD = 416 V, ID = 4.4 A, - 16.9 - nC

Qgs Gate-source charge VGS = 0 to 10 V - 4.2 - nC

s o Qgd Gate-drain charge


(see Figure 14. Test circuit for gate
- 8.4 - nC

O b charge behavior)

1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 260 V, ID = 2.2 A, - 11.4 -

tr Rise time RG = 4.7 Ω, VGS = 10 V - 13.6 -

td(off) (see Figure 13. Test circuit for ns


Turn-off delay time - 23.1 -
resistive load switching times and
Figure 18. Switching time
tf Fall time - 15 -
waveform)

DS12943 - Rev 1 page 3/13


STF5N52U
Electrical characteristics

Table 7. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD Source-drain current - 4.4 A

ISDM(1) Source-drain current (pulsed) - 17.6 A

VSD Forward on voltage VGS = 0 V, ISD = 4.4 A - 1.6 V

trr Reverse recovery time ISD = 4.4 A, di/dt = 100 A/µs, - 55 ns

Qrr Reverse recovery charge VDD = 60 V - 95 nC


(see Figure 15. Test circuit for
inductive load switching and diode
s )
t(
IRRM Reverse recovery current - 3.5 A
recovery times)
trr Reverse recovery time ISD = 4.4 A, di/dt = 100 A/µs,
u-c 120 ns

Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C


od - 266 nC

IRRM Reverse recovery current


(see Figure 15. Test circuit for

P
inductive load switching and diode
r - 4.5 A
recovery times)

t e
1. Pulse width is limited by safe operating area
2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%
o le
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Table 8. Source drain diode

-
Symbol

V(BR)GSO
Parameter

( s )
Gate-source breakdown voltage
Test conditions

IGS = ± 1mA, ID = 0 V
Min.

30
Typ.

-
Max.

-
Unit

c t
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The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In
this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the
P
device's integrity. These integrated Zener diodes thus avoid the usage of external components.

e
l e t
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DS12943 - Rev 1 page 4/13


STF5N52U
Electrical characteristics (curves)

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance


GC20540_ZTH
K
δ=0.5

δ=0.2

s )
t(
0.1

10 -1
0.02
0.05

u c
o
0.01
d
r
Single pulse

P
10
-2

t e
le
10-5 10-4 10-3 10
-2
10 -1 tp(s)

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Figure 3. Output characteristics
Ob Figure 4. Transfer characteristics

) -
t ( s
u c
o d
P r
e t e
o l
b s
O Figure 5. Normalized V(BR)DSS vs temperature Figure 6. Static drain-source on-resistance

(BR)

DS12943 - Rev 1 page 5/13


STF5N52U
Electrical characteristics (curves)

Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations

s )
c t(
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Figure 9. Normalized gate threshold voltage vs
temperature
P
Figure 10. Normalized on-resistance vs temperature
e
le t
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) -
t ( s
u c
o d
0.6

P r
e te
o l
Figure 11. Source-drain diode forward characteristics Figure 12. Maximum avalanche energy vs temperature

b s
O

DS12943 - Rev 1 page 6/13


STF5N52U
Test circuits

3 Test circuits

Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior

VDD

12 V 47 kΩ
1 kΩ
100 nF
RL
2200

)
3.3
+ μF μF VDD

RG
VD
VGS

+
IG= CONST
100 Ω

t( s
D.U.T.

uc
pulse width
VGS D.U.T. 2.7 kΩ
2200 VG
pulse width μF
47 kΩ

o d
1 kΩ

r
eP
AM01468v1 AM01469v1

l e t
Figure 15. Test circuit for inductive load switching and
diode recovery times s o
Figure 16. Unclamped inductive load test circuit

O b
) -
(s
A A A L

t
D VD
fast 100 µH

c
G D.U.T. diode 2200 3.3

u + µF
S B 3.3 1000 µF VDD
B B
µF + µF VDD

d
25 Ω D ID

o
G D.U.T.

P
+

_
RG S

r Vi
pulse width
D.U.T.

et e
o l AM01471v1

s
AM01470v1

Ob Figure 17. Unclamped inductive waveform


Figure 18. Switching time waveform
ton toff
V(BR)DSS
td(on) tr td(off) tf
VD

90% 90%
IDM

10% VDS 10%


ID 0

VDD VDD VGS 90%

0 10%
AM01472v1
AM01473v1

DS12943 - Rev 1 page 7/13


STF5N52U
Package information

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.

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DS12943 - Rev 1 page 8/13


STF5N52U
TO-220FP package information

4.1 TO-220FP package information

Figure 19. TO-220FP package outline

s )
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t ( s
u c
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P r
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7012510_Rev_12_B

DS12943 - Rev 1 page 9/13


STF5N52U
TO-220FP package information

Table 9. TO-220FP package mechanical data

mm
Dim.
Min. Typ. Max.

A 4.4 4.6
B 2.5 2.7
D 2.5 2.75
E 0.45 0.7
F 0.75 1

s )
t(
F1 1.15 1.70

uc
F2 1.15 1.70

od
G 4.95 5.2

Pr
G1 2.4 2.7
H 10 10.4
L2
t e
16
L3 28.6

o le 30.6
L4
L5
9.8
2.9 b s 10.6
3.6
L6
-
15.9 O 16.4
L7

( s )
9 9.3
Dia

c t 3 3.2

d u
r o
e P
l e t
s o
O b

DS12943 - Rev 1 page 10/13


STF5N52U

Revision history

Table 10. Document revision history

Date Version Changes

05-Mar-2019 1 First release. Part number previously included in datasheet DocID15684.

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DS12943 - Rev 1 page 11/13


STF5N52U
Contents

Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
)
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
s
4.1 t(
TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
c
d u
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
r o
e P
le t
s o
O b
) -
t ( s
u c
o d
P r
e t e
o l
b s
O

DS12943 - Rev 1 page 12/13


STF5N52U

IMPORTANT NOTICE – PLEASE READ CAREFULLY


STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

s )
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
c t(
d u
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

r o
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

e
© 2019 STMicroelectronics – All rights reserved P
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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t ( s
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P r
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DS12943 - Rev 1 page 13/13

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