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Digital Integated Circuits Assignment 3: Name: Arpit Sharma Roll No: 32118222 Branch: VLSI Design, 1

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Abhinav Sahu
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15 views7 pages

Digital Integated Circuits Assignment 3: Name: Arpit Sharma Roll No: 32118222 Branch: VLSI Design, 1

Uploaded by

Abhinav Sahu
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© © All Rights Reserved
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DIGITAL INTEGATED CIRCUITS

Assignment 3

Name : ARPIT SHARMA

Roll no : 32118222

Branch : VLSI Design, 1st year M.Tech


Spice model level 2:

.MODEL NMOSL2 NMOS( level=2 vto=1 nsub=1e16 tox=8.5e-8 uo=750 + cgso=4e-10


cgdo=4e-10 cgbo=2e-10 uexp=0.14 ucrit=5e4 utra=0 vmax=5e4 rsh=15 + cj=4e-4 mj=2 pb=0.7
cjsw=8e-10 mjsw=2 js=1e-6 xj=1u ld=0.7u ) *

.MODEL PMOSL2 PMOS( level=2 vto=-1 nsub=2e15 tox=8.5e-8 uo=250 + cgso=4e-10


cgdo=4e-10 cgbo=2e-10 uexp=0.03 ucrit=1e4 utra=0 vmax=3e4 rsh=75 + cj=1.8e-4 mj=2
pb=0.7 cjsw=6e-10 mjsw=2 js=1e-6 xj=0.9u ld=0.6u ) *

Length and widths of N-MOS are 2um and 5um


Length and widths of p-MOS are 2um and 15um

Layout of CMOS Inverter:


Parasatic capacitances:

Calculations of Propagation delay of CMOS inverter :

Fig.1 : CMOS inverter circuit diagram


Fig.2 Output for tplh

Fig.4 Output for tphl


CALCULATIONS:

tphl=2.0292208ns

tplh=1.2738095ns

tp = (tphl +tplh)/2

= (2.02+ 1.273)/2

Propogation delay(tp)=1.645ns

NOISE MARGIN:

Fig:VOUT and Vin


Calculation of Noise Margin:
VOL=2.4114441V
VIL=3.57234V
VIH=3.0980926V
VOH=4.3274859V

NMH=VOH-VIH=1.238
NML=VIL-VOL=1.1612
Fan-out:

Calculations:
IIH=60.879621µA
IIL=-38.086943µA
IOH=247.78044µA
IOL=-176.90877µA
Fan out=min{|Ioh/Iih| , |Iol/Iil|}
=4

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