Unit-3 Combinational Circuit Adders Subtractor Decoder-Encoder Multiplexers-Demultiplexers Comparator Parity IC Family
Unit-3 Combinational Circuit Adders Subtractor Decoder-Encoder Multiplexers-Demultiplexers Comparator Parity IC Family
Unit-3 Combinational Circuit Adders Subtractor Decoder-Encoder Multiplexers-Demultiplexers Comparator Parity IC Family
Adders
Subtractor
Decoder-Encoder
Multiplexers-Demultiplexers
Comparator
Parity
IC Family
Combinational Circuits
• output depends only on the present input
• The combinational circuit do not use any memory.
• The previous state of input does not have any effect on the present state of the circuit.
Half Adder
A combinational logic circuit with two inputs and two outputs.
The half adder circuit add two single bit Cary number
This circuit has two outputs carry and sum.
S(A, B) = ∑m (1, 2)
CY(A, B) = ∑m (3)
Full Adder (1-bit Adder)
A combinational logic circuit with 3 inputs and 2 outputs.
The Full adder circuit add 3 single bit Cary number
This circuit has two outputs carry and sum.
Cout=AB+BC+AC
Full Adder using Half Adder
FA
Sum= A⊕B⊕C
Carry=AB+(A⊕B)C
HA
Sum= A⊕B
Carry=AB
Half Subtractor
Combinational circuit perform binary Subtraction
Accepts 2 input and Two output Difference and Borrow
D(A, B) = ∑m (1, 2)
Br(A, B) = ∑m (1)
Full Subtractor
Performs subtraction of 3 bits
This circuit has three inputs and two outputs.
The three inputs A, B and C, denote the minuend, subtrahend, and previous borrow, respectively.
The two outputs, D and Bout
Sum(A, B,C) = ∑m (1, 2, 4, 7)
Bout(A, B,C) = ∑m (1,2,3,7)
Bout = A’B’C + A’BC’ + A’BC + ABC
= C(AB + A’B’) + A’B(C + C’)
= C( A XNOR B) + A’B
= C (A XOR B)’ + A’B
Full Subtractor using Half Subtractor
FS
Sum= A⊕B⊕C
Carry=A’B+(A⊕B)’C
HS
Sum= A⊕B
Carry=A’B
Design a 3 input digital circuit produces high output for two or more binary input high
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Design a 3 input digital circuit produces high output for ODD decimal equivalent
A B C Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1-BIT Magnitude Comparator
GT
A 1-Bit
Magnitude EQ
B Comparator LT
EQ
GT LT
GT=AB’
EQ=A’B’+AB
LT=A’B
2-BIT Magnitude Comparator
Multiplexer
➢ A combinational circuit has maximum of 2n data inputs, ‘n’ selection lines and single output line.
➢ One of these data inputs will be connected to the output based on the values of selection lines
➢ It is a data selector device
➢ Size of multiplexer is 2𝑛 :1
I0 0
Y =S’I0 + SI1
2:1 Multiplexer
I1 1
S
4:1 Multiplexer
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Expression implementation with Multiplexer
Y(A, B,C) = ∑m (1, 3, 5, 6) implement with 4:1 multiplexer Y(A, B,C) = ∑m (1, 2, 4, 5) implement with 4:1 multiplexer
Any 2 input (AB/BC/AC) select line Any 2 input (AB/BC/AC) select line
0 C
1 C’
A 1
A’ 0
Rearrange equation with selection line Rearrange equation with selection line
I0 I1 I2 I3 I0 I1 I2 I3
Logic Gate implementation with 2:1 Multiplexer
AND GATE OR GATE
NOR GATE
NAND GATE
Logic Gate implementation with 2:1 Multiplexer
XOR GATE XNOR GATE
NOT GATE
Full Adder implementation with 4:1 Multiplexer
S(A, B, Cin) = ∑(1, 2, 4, 7)
= m1 + m2 + m4 +m7
= A’B’Cin + A’BC’in + AB’C’in + ABCin
= A.(B’C’in) + A’.(B’Cin) + A’.(BC’in) + A.(B’C’in)
(1)
I0 = A, I1 = A’, I2 = A’, I3 = A.
A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Full Adder using 3:8 Decoder Full Subtractor using 3:8 Decoder
Y
3:8 decoder using 2:4 decoder
Decoder with Enable
One of outputs will be ‘1’ when enable, E is ‘1’
A2 A1 A0 HIGH OUTPUT
0 0 0 Y0
0 0 1 Y1
0 1 0 Y2
0 1 1 Y3
1 0 0 Y4
1 0 1 Y5
1 1 0 Y6
1 1 1 Y7
4:16 decoder
A3 A2 A1 A0 HIGH OUTPUT
0 0 0 0 Y0
0 0 0 1 Y1
Y0
0 0 1 0 Y2
0 0 1 1 Y3 A3
0 1 0 0 Y4
0 1 0 1 Y5 A2
0 1 1 0 Y6
0
1
1
0
1
0
1
0
Y7
Y8
A1
4:16 Decoder
1 0 0 1 Y9
A0
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13 Y15
1 1 1 0 Y14
EN
1 1 1 1 Y15
4:16 decoder using 3:8 decoder
A3 A2 A1 A0 HIGH OUTPUT
0 0 0 0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7
1 0 0 0 Y8
1 0 0 1 Y9
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13
1 1 1 0 Y14
1 1 1 1 Y15
4:16 decoder using 2:4 decoder
A3 A2 A1 A0 HIGH OUTPUT
0 0 0 0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7
1 0 0 0 Y8
1 0 0 1 Y9
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13
1 1 1 0 Y14
1 1 1 1 Y15
4:2 Encoder
4-bit Ripple Carry Adder
4-bit Adder cum Subtractor capable of both addition and subtraction of
binary numbers in one circuit
K=0 Addition
K=1 Subtraction
•Diode Logic (DL) logic is implemented with the use of resistors and diodes.
•Resistor-Transistor Logic (RTL) logic is implemented with the use of transistors and resistors
•Diode-Transistor Logic (DTL) logic is implemented with the use of diodes and transistors.
•Transistor-Transistor Logic (TTL) logic are implemented with transistors
•Emitter Coupled Logic (ECL) logic are implemented with transistors
•Complementary Metal Oxide Semiconductor Logic (CMOS) logic are implemented with MOSFET
Fan out: It specifies the number of standard loads that the output of the gate can drive without affecting its normal operation.
Fan in: This is the number of inputs of a logic gate.
Power Dissipation: This is the power supplied required to operate the gate.
Propagation delay Time delay between the occurrence of change in the logical level at the input and before it is reflected at
the output
Noise margin: This is the maximum noise voltage added to the input signal of digital circuit that does not cause an undesirable
change in the circuit output