AN233855

Support for SEMPER™ Quad SPI flash in Linux

from Xilinx
Scope and purpose
This application note explains how to support SEMPER™ quad SPI NOR flash memory on the memory
technology device (MTD) layer of Linux operating systems and how each die can be accessed. The patch file has
several dependencies on update status and source code revision. In many cases, simply applying the patch may
cause errors and failures. Therefore, you may need to migrate the source code on the patch file manually. This
application note also tries to explain how to do that.

Intended audience
This application note is intended for users who use Linux with UltraScale+ MPSoC devices from Xilinx and
Infineon SEMPER™ NOR flash memory.

Table of contents
Table of contents ............................................................................................................................ 1
1 Introduction .......................................................................................................................... 2
2 Set up the environment .......................................................................................................... 3
2.1 Mount SEMPER™ NOR flash memory on UltraScale+ MPSoC board from Xilinx ................................... 3
2.2 Set up toolchains from Xilinx .................................................................................................................. 5
2.3 Download the Linux source code ........................................................................................................... 5
3 Apply the Linux patch file ........................................................................................................ 7
4 Merge the Linux patch file manually ......................................................................................... 8
4.1 Modify drivers/mtd/spi-nor/core.c........................................................................................................... 8
4.1.1 Set 4-byte addressing mode .............................................................................................................. 8
4.1.2 Modify the function to find the best erase type ................................................................................ 8
4.1.3 Modify the function to initialize erase command list ....................................................................... 8
4.1.4 Create Any Register Read/Write functions ........................................................................................ 8
4.1.5 Set QSPI mode using the volatile register ......................................................................................... 8
4.1.6 Fix and manage parameter sectors to erase ..................................................................................... 9
4.1.7 Modify the source code ...................................................................................................................... 9
4.2 Modify drivers/mtd/spi-nor/core.h ........................................................................................................ 15
4.3 Modify drivers/mtd/ spi-nor/sfdp.c ........................................................................................................ 15
4.3.1 Set the overlay bit when the region is overlaid ............................................................................... 15
4.3.2 Moify the initialization of the non-uniform erase map ................................................................... 16
4.3.3 Modify the source code .................................................................................................................... 16
4.4 Modify drivers/mtd/spi-nor/spansion.c ................................................................................................. 17
4.4.1 Add SPI NOR fixups structure and create fixup functions .............................................................. 18
4.4.2 Add SEMPER™ flash memory devices .............................................................................................. 18
4.4.3 Modify the source code .................................................................................................................... 18
4.5 Modify include/linux/mtd/spi-nor.h ....................................................................................................... 20
5 Conclusion ........................................................................................................................... 21
Revision history............................................................................................................................. 22

Application Note Please read the Important Notice and Warnings at the end of this document 002-33855 Rev.**
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Support for SEMPER™ Quad SPI flash in Linux from Xilinx

Introduction

1 Introduction
Open source-based projects are frequently improved and expanded by several contributors. Linux is also
periodically changed by many contributors in this way. This changing project is managed based on tags by the
maintainer; platform designers or system designers download the project and perform porting work according
to their platform design.
Even though you can develop your own flash driver source code according to the SEMPER™ flash datasheet to
use Linux with SEMPER™ flash devices, it is easier to use a patch file for the project from the device
manufacturer while downloading the open source-based project.
Infineon also provides patch files for open source-based projects. However, open source-based projects are
frequently changed; this may make the patch file incompatible with your target platform. When this happens,
you have to break up the patch file and apply it manually one by one. This application note explains how to use
a Linux patch file from Infineon to enable SEMPER™ flash memory.

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Support for SEMPER™ Quad SPI flash in Linux from Xilinx

Set up the environment

2 Set up the environment

2.1 Mount SEMPER™ NOR flash memory on UltraScale+ MPSoC board from
Xilinx
I/O peripherals (IOP) from Xilinx have two Quad-SPI controllers with different functional features and I/O
interfacing capabilities. They share the same advanced peripheral bus (APB) slave interface and I/O signals to
the multiplexed I/O (MIO) pins. Only one controller can be enabled at a time. The legacy Quad-SPI controller
(LQSPI) provides a linear addressable memory space on the Quad-SPI advanced extensible interface (AXI) slave
interface, and supports execute-in-place (XIP) for booting and application software for some configurations.
The generic Quad-SPI controller (GQSPI) provides I/O, DMA, and SPI mode interfacing. Boot and XIP are not
supported in GQSPI.

Table 1 QSPI flash memory I/O type configuration

I/O type Device count Slave selects Data signals Controller Boot (GQSPI) XiP (LQSPI)
type

Single CS# 1 1 4 LQSPI, GQSPI Yes1 Yes

Dual CS# 2 2 4 LQSPI, GQSPI Yes Yes

stacked

Dual CS# 2 2 8 LQSPI, GQSPI Yes No

parallel

1
Only LQSPI provides a linear address space which XiP requires. However, based on the data provided in the spec sheet from Xilinx,
GQSPI can provide limited support for XiP when the configuration security unit (CSU) boot ROM uses the GQSPI controller for system
boot.
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Support for SEMPER™ Quad SPI flash in Linux from Xilinx

Set up the environment

Figure 1 UltraScale+ MPSoC evaluation board from Xilinx

This application note shows how to use two Infineon SEMPER™ QSPI NOR flash memory devices by applying
dual CS# parallel mode. For this, the existing NOR flash memory devices of UltraScale+ MPSoC board from
Xilinx are removed and two SEMPER™ 1.8-V QSPI 1-Gbit (S25HS01GT) flash memory devices are attached as
follows. In Figure 2, a small socket is attached and the flash memory is installed for the subsequent flash
memory test.
This test uses two 1-Gbit devices, but 2-Gbit or 4-Gbit devices also can be used; the sf command will be
changed to support these devices.

Figure 2 Mount two SEMPER™ QSPI NOR flash devices

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Support for SEMPER™ Quad SPI flash in Linux from Xilinx

Set up the environment

2.2 Set up toolchains from Xilinx

1. Check the latest user guide on the Xilinx website to learn about installing toolchains from Xilinx as they
continue to be updated.
2. Create an account on the Xilinx web site to download the toolchain.
3. Install the following items:
− Visual Studio Code
− Windows Subsystem for Linux (WSL)
− Xilinx SDK 2019.1 or later
− Git application on WSL

Note: You don't need to download the entire Vivado or Vitis software from Xilinx to set up a build
environment for the Linux driver code; you can use the Xilinx SDK for that. Also, you do not need to
install the GUI tool because you will be using the command-line options. See the “Batch Mode
Installation Flow” section in the ug973-vivado-release-notes-install-license.pdf document.

2.3 Download the Linux source code

1. Create a folder (for example: myproject) in your local machine and download the Linux project from Xilinx
on GitHub (https://github.com/Xilinx/linux-xlnx.git) using the git application:
$ mkdir myproject
$ cd myproject
myproject$ git clone https://github.com/Xilinx/linux-xlnx.git
Cloning into 'linux-xlnx'...
remote: Enumerating objects: 8370495, done.
remote: Counting objects: 100% (390/390), done.
remote: Compressing objects: 100% (210/210), done.
remote: Total 8370495 (delta 237), reused 250 (delta 180), pack-reused 8370105
Receiving objects: 100% (8370495/8370495), 2.18 GiB | 8.70 MiB/s, done.
Resolving deltas: 100% (7063658/7063658), done.
Updating files: 100% (70999/70999), done.
warning: the following paths have collided (e.g. case-sensitive paths
on a case-insensitive filesystem) and only one from the same
colliding group is in the working tree:
...
myproject$ cd linux-xlnx

2. Set environment variables for build:

linux-xlnx$ source /tools/Xilinx/SDK/2019.1/settings64.sh
linux-xlnx$ export CROSS_COMPILE=aarch64-linux-gnu-
linux-xlnx$ export ARCH=arm64

The build starts using the default configuration. This process may take several hours. When the build is
completed without errors, verify that Image* files are created in the arch/arm64/boot/ folder.
linux-xlnx$ make distclean
linux-xlnx$ make xilinx_zynqmp_defconfig
linux-xlnx$ make menuconfig

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Support for SEMPER™ Quad SPI flash in Linux from Xilinx

Set up the environment

linux-xlnx$ make
...

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Support for SEMPER™ Quad SPI flash in Linux from Xilinx

Apply the Linux patch file

3 Apply the Linux patch file

Do the following after getting the patch file (0001-arm64-zynqmp-spi-nor-mtd-driver-This-patch-contains-.patch)
that enables Linux from Xilinx to support the SEMPER™ NOR flash memory:
1. Copy the patch to the parent folder of the linux-xlnx folder.
Even though you can place the patch anywhere, you should ideally separate it from the Linux source code
already present.
2. Enter the following patch command to apply the patch to appropriate files:
linux-xlnx$ patch -p1 < ../0001-arm64-zynqmp-spi-nor-mtd-driver-This-patch-contains-.patch

The following message ensures that the patch was successful:

patching file drivers/mtd/spi-nor/core.c
patching file drivers/mtd/spi-nor/core.h
patching file drivers/mtd/spi-nor/sfdp.c
patching file drivers/mtd/spi-nor/spansion.c
patching file include/linux/mtd/spi-nor.h

3. If there are no errors, build again to generate Image* files to which the patch was applied:
linux-xlnx$ make
...

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Merge the Linux patch file manually

4 Merge the Linux patch file manually

Even though a patch file makes source code update convenient, errors may occur in the patch process when
targeting frequently updated source code. This will require that you disassemble the given patch file and apply
it directly to the source code.
Code snippets to be added to each file are provided in this document. See the code listed in the first few lines of
each Code Listing to identify where to add the code snippet. Just as the source code is updated, the patch file is
also continuously updated. Thus, note that there may be changes in the code snippets, and more parts
may need updates than provided in this document. You should check and compare the patch file
provided with the code snippets provided in this document.

4.1 Modify drivers/mtd/spi-nor/core.c

The major patches are made in core.c. It mainly consists of the following elements:

4.1.1 Set 4-byte addressing mode

The SEMPER™ NOR flash memory supports both 3-byte (24 bits) and 4-byte (32 bits) addressing modes like the
previous-generation memory devices. After a reset or power-on reset, the memory is set to 3-byte addressing
mode (the default setting), unless you set the non-volatile configuration register for 4-byte addressing mode.
This setting can be stored in the non-volatile configuration register or temporarily set in the volatile
configuration register at system startup. In the latter case, the setting can be directly written to the volatile
configuration register, but it can also be set using the EN4BA command.

4.1.2 Modify the function to find the best erase type

The patch contains a function to find the best erase type for the given offset in the serial flash memory and the
number of bytes to erase. Modify this function to return to its caller immediately with a pointer to a structure of
spi_nor_erase_type when it finds that the sector has overlaid region property.

4.1.3 Modify the function to initialize erase command list

The patch contains a function to build the list of best-fitted erase commands and to verify if the erase can be
performed. This function adds one erase size comparison condition where the result of the conditional
statement can be true. This allows to call the function which can initialize the erase command.

4.1.4 Create Any Register Read/Write functions

As the features of the SEMPER™ NOR flash memory increases, user options also have increased. This eventually
led to an increase in the internal registers. Because there is a limit to the method of adding new commands to
control these internal registers, new commands such as Any Register Read and Any Register Write that use the
register address were added. These are vendor-specific functions; these are not yet included in the Linux source
code from Xilinx and must be implemented by users themselves.

4.1.5 Set QSPI mode using the volatile register

The SEMPER™ NOR flash memory supports QSPI mode, but by default, the memory is set not to use QSPI mode,
unless you set the configuration register to have QSPI mode. This setting can be stored in the non-volatile
configuration register or temporarily set in the volatile configuration register at system startup. This patch
shows how to enable QSPI mode using the volatile configuration register.

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4.1.6 Fix and manage parameter sectors to erase

Many NOR flash memories have been designed to have parameter sectors of 4 KB or 8 KB. These parameter
sectors can be configured at the bottom address or top address according to the setting of the configuration
register; the number can be different for each NOR flash memory family. In the case of SEMPER™ NOR flash
memory, thirty-two 4-KB parameter sectors can be allocated to a part of Sector 0 or a part of the last sector.
You should add a function for erasing this parameter sector.

4.1.7 Modify the source code

1. Set the SEMPER™ NOR flash memory to use 4-byte addressing mode. Use the existing
spansion_set_4byte_addr_mode function, and modify the SPI_MEM_OP macro to use the EN4BA
(0xB7) and EX4BA (0xB8) commands.

Code Listing 1 Set 4-byte addressing mode

001 int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool
enable)
002 {
003 int ret;
004
005 nor->bouncebuf[0] = enable << 7;
006
007 if (nor->spimem) {
008 struct spi_mem_op op =
009 SPI_MEM_OP(SPI_MEM_OP_CMD(enable ?
010 SPINOR_OP_EN4BA :
011 SPINOR_OP_EX4BA,
012 1),
013 SPI_MEM_OP_NO_ADDR,
014 SPI_MEM_OP_NO_DUMMY,
015 SPI_MEM_OP_NO_DATA);
016
017 ret = spi_mem_exec_op(nor->spimem, &op);
018 } else {
019 ret = nor->controller_ops->write_reg(nor, enable
?
020 SPINOR_OP_EN4BA :
SPINOR_OP_EX4BA, NULL, 0);
021 }
022
023 if (ret)
024 dev_dbg(nor->dev, "error %d setting 4-byte
mode\n", ret);
025
026 return ret;
027 }

2. Modify the function to return to its caller with a pointer to a structure of spi_nor_erase_type when the
function finds that the sector has overlaid region. In the following source code, note that the return order of
the corresponding part in the loop is different from the source code provided by Xilinx.

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Code Listing 2 Modify the function to find the best erase type
001 static const struct spi_nor_erase_type *
002 spi_nor_find_best_erase_type(const struct spi_nor_erase_map
*map,
003 const struct spi_nor_erase_region
*region,
004 u64 addr, u32 len)
005 {
006 const struct spi_nor_erase_type *erase;
007 u32 rem;
008 int i;
009 u8 erase_mask = region->offset & SNOR_ERASE_TYPE_MASK;
010
011 /*
012 * Erase types are ordered by size, with the smallest
erase type at
013 * index 0.
014 */
015 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
016 /* Does the erase region support the tested erase
type? */
017 if (!(erase_mask & BIT(i)))
018 continue;
019
020 erase = &map->erase_type[i];
021
022 /* Alignment is not mandatory for overlaid
regions */
023 if (region->offset & SNOR_OVERLAID_REGION &&
024 region->size <= len)
025 return erase;
026
027 /* Don't erase more than what the user has asked
for. */
028 if (erase->size > len)
029 continue;
030
031 spi_nor_div_by_erase_size(erase, addr, &rem);
032 if (rem)
033 continue;
034 else
035 return erase;
036 }
037
038 return NULL;
039 }

3. Find the spi_nor_init_erase_cmd_list function, and then add one erase size comparison condition
where the result of the conditional statement can be true to call the spi_nor_init_erase_cmd
function.

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Code Listing 3 Modify the function to initialize the erase command list
001 if (prev_erase != erase ||
002 erase->size != cmd->size ||
003 region->offset & SNOR_OVERLAID_REGION) {
004 cmd = spi_nor_init_erase_cmd(region,
erase);
005 if (IS_ERR(cmd)) {
006 ret = PTR_ERR(cmd);
007 goto destroy_erase_cmd_list;
008 }
009
010 list_add_tail(&cmd->list, erase_list);
011 } else {
012 cmd->count++;
013 }

4. Add spansion_read_any_reg and spansion_write_any_reg functions for Any Register access.

Because these functions receive the address of Any Registers as an argument, a register can be accessed
individually by selecting the lower die or upper die of the MCP.
Code Listing 4 Add Any Register access functions
001 int spansion_read_any_reg(struct spi_nor *nor, u32 reg_addr,
002 u8 reg_dummy, u8 *reg_val)
003 {
004 u8 read_opcode, read_dummy, dummy_rem;
005 enum spi_nor_protocol read_proto;
006 size_t len;
007 ssize_t ret;
008
009 read_opcode = nor->read_opcode;
010 read_dummy = nor->read_dummy;
011 read_proto = nor->read_proto;
012
013 nor->read_opcode = SPINOR_OP_RD_ANY_REG;
014 nor->read_dummy = reg_dummy & ~7;
015 nor->read_proto = SNOR_PROTO_1_1_1;
016
017 dummy_rem = reg_dummy - nor->read_dummy;
018 len = dummy_rem ? 2 : 1;
019
020 ret = spi_nor_read_data(nor, reg_addr, len, nor-
>bouncebuf);
021
022 nor->read_opcode = read_opcode;
023 nor->read_dummy = read_dummy;
024 nor->read_proto = read_proto;
025
026 if (ret == len) {
027 if (dummy_rem)
028 *reg_val = (nor->bouncebuf[0] << dummy_rem)
|

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029 (nor->bouncebuf[1] >> (8 -

dummy_rem));
030 else
031 *reg_val = nor->bouncebuf[0];
032
033 return 0;
034 }
035
036 return ret < 0 ? ret : -EIO;
037 }
038
039 static int spansion_write_any_reg(struct spi_nor *nor, u32
reg_addr, u8 reg_val)
040 {
041 u8 program_opcode;
042 enum spi_nor_protocol write_proto;
043 ssize_t ret;
044
045 ret = spi_nor_write_enable(nor);
046 if (ret)
047 return ret;
048
049 program_opcode = nor->program_opcode;
050 write_proto = nor->write_proto;
051
052 nor->program_opcode = SPINOR_OP_WR_ANY_REG;
053 nor->write_proto = SNOR_PROTO_1_1_1;
054
055 nor->bouncebuf[0] = reg_val;
056 ret = spi_nor_write_data(nor, reg_addr, 1, nor-
>bouncebuf);
057
058 nor->program_opcode = program_opcode;
059 nor->write_proto = write_proto;
060
061 return ret == 1 ? 0 : (ret < 0 ? ret : -EIO);
062 }

5. Create the spansion_quad_enable_volatile function. This function sets the SEMPER™ NOR flash
memory that is not set as Quad interface to have a Quad interface temporarily by setting a volatile register.
Because the function receives the address of Any Registers as an argument, the register can be accessed
individually by selecting the lower die or upper die of the MCP.
Code Listing 5 Enable the Quad interface by setting a volatile register
001 static int spansion_quad_enable_volatile(struct spi_nor *nor,
u32 reg_addr_base,
002 u8 reg_dummy)
003 {
004 u32 reg_addr = reg_addr_base + SPINOR_REG_CYPRESS_CFR1V;
005 u8 cfr1v, cfr1v_written;
006 int ret;
007
008 /* Check current Quad Enable bit value. */

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009 ret = spansion_read_any_reg(nor, reg_addr, reg_dummy,

&cfr1v);
010 if (ret)
011 return ret;
012 if (cfr1v & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
013 return 0;
014
015 /* Update the Quad Enable bit. */
016 cfr1v |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
017
018 ret = spansion_write_any_reg(nor, reg_addr, cfr1v);
019 if (ret)
020 return ret;
021
022 cfr1v_written = cfr1v;
023
024 /* Read back and check it. */
025 cfr1v = 0xFF;
026 ret = spansion_read_any_reg(nor, reg_addr, reg_dummy,
&cfr1v);
027 if (ret)
028 return ret;
029
030 if (cfr1v != cfr1v_written) {
031 dev_err(nor->dev, "CFR1: Read back test failed,
%02x\n", cfr1v);
032 return -EIO;
033 }
034
035 return 0;
036 }
037
038 int s25hx_t_quad_enable(struct spi_nor *nor)
039 {
040 return spansion_quad_enable_volatile(nor, 0, 0);
041 }

6. SEMPER™ NOR flash memory can be composed of several erasable sectors of different sizes, and a group of
sectors of the same size is called a region. These region settings are generally completed based on the
values specified in the SFDP, but it is necessary to directly specify them in the source code as follows and
modify them so that they can be used in the Linux MTD layer. Modify the information for each region
according to the SEMPER™ NOR flash memory that you use in your deign as follows:
Code Listing 6 Add a function to fix SEMPER™ flash erase map
001 void s25hx_t_fix_erase_map(struct spi_nor *nor)
002 {
003 struct spi_nor_erase_region *region = nor->params-
>erase_map.regions;
004 u8 erase_type_256k, erase_type_4k, erase_type_r0;
005
006 /*
007 * Uniform: Only one region is allocated. Unsupported
Map IDs are rolled
008 * back to the Uniform.
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009 * Bottom: Size of region 0 and 1 are same (128KB)

010 */
011 if (region[0].offset & SNOR_LAST_REGION ||
012 region[0].size == region[1].size)
013 {
014 region[2].size = SZ_256M - region[0].size -
region[1].size;
015 return;
016 }
017
018 /* Erase Types are sorted in ascending order */
019 erase_type_256k = BIT(SNOR_ERASE_TYPE_MAX - 1);
020 erase_type_4k = BIT(SNOR_ERASE_TYPE_MAX - 2);
021
022 /* Examine Erase Type of Region 0 */
023 erase_type_r0 = region[0].offset & SNOR_ERASE_TYPE_MASK;
024 if (erase_type_r0 == erase_type_256k) {
025 pr_info("Enter s25hx_t_fix_erase_map 1");
026 /*
027 * Erase Map is populated as Top and needs to be
fixed to Split.
028 * Re-allocate 5 regions then free existing 3
regions.
029 */
030 region = devm_kcalloc(nor->dev, 5,
sizeof(*region), GFP_KERNEL);
031 if (!region)
032 return;
033
034 region[0].size = SZ_64K;
035 region[1].size = SZ_256K - SZ_64K;
036 region[2].size = nor->params->size - SZ_512K;
037 region[3].size = SZ_256K - SZ_64K;
038 region[4].size = SZ_64K;
039
040 region[0].offset = 0;
041 region[1].offset = region[0].size;
042 region[2].offset = region[1].offset +
region[1].size;
043 region[3].offset = region[2].offset +
region[2].size;
044 region[4].offset = region[3].offset +
region[3].size;
045
046 region[0].offset |= erase_type_4k;
047 region[1].offset |= erase_type_256k |
SNOR_OVERLAID_REGION;
048 region[2].offset |= erase_type_256k;
049 region[3].offset |= erase_type_256k |
SNOR_OVERLAID_REGION;
050 region[4].offset |= erase_type_4k |
SNOR_LAST_REGION;
051
052 devm_kfree(nor->dev, nor->params-
>erase_map.regions);
053 nor->params->erase_map.regions = region;
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054
055 } else if (erase_type_r0 == erase_type_4k) {
056 pr_info("Enter s25hx_t_fix_erase_map 2");
057 /*
058 * Erase Map is populated as Split and needs to
be fixed to Top.
059 */
060 region[0].size = nor->params->size - SZ_256K;
061 region[1].size = SZ_128K;
062 region[2].size = SZ_128K;
063
064 region[0].offset = 0;
065 region[1].offset = region[0].size;
066 region[2].offset = region[1].offset +
region[1].size;
067
068 region[0].offset |= erase_type_256k;
069 region[1].offset |= erase_type_256k |
SNOR_OVERLAID_REGION;
070 region[2].offset |= erase_type_4k |
SNOR_LAST_REGION;
071 }
072 }

4.2 Modify drivers/mtd/spi-nor/core.h

Add the following four function prototypes to the core.h header file.

Code Listing 7 Add SEMPER™ flash memory devices

001 int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool
enable);
002 int spansion_read_any_reg(struct spi_nor *nor, u32 reg_addr,
003 u8 reg_dummy, u8 *reg_val);
004 int s25hx_t_quad_enable(struct spi_nor *nor);
005 void s25hx_t_fix_erase_map(struct spi_nor *nor);

4.3 Modify drivers/mtd/ spi-nor/sfdp.c

Working with this file may not be necessary in some cases. However, some parts have been modified for
reference.

4.3.1 Set the overlay bit when the region is overlaid

The example with a hybrid configuration in Figure 3 shows that the first 256-KB sector is divided into thirty-two
4-KB sectors and the remaining 128-KB sector. In this case, only the 128-KB sector region except for the region
consisting thirty-two of 4-KB sectors should have the overlaid attribute. If the overlaid attribute is also given to
the 4-KB sector region, only one erase operation is performed for the 4-KB sector region; in the end, only the
first 4-KB sector of thirty-two 4-KB sectors is erased. To prevent this, modify the conditional statement in the
loop.

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Figure 3 Bottom hybrid configuration

4.3.2 Modify the initialization of the non-uniform erase map

Change the call location of the function that adds the property pointing to the last region after the loop which
changes the erase property of each region.

4.3.3 Modify the source code

1. Change the conditional statement in the loop if (!(erase_type & BIT(i))) to if
(!(erase[i].size && erase_type & BIT(erase[i].idx))).

Code Listing 8 Modify the region overlay check function

001 static void
002 spi_nor_region_check_overlay(struct spi_nor_erase_region
*region,
003 const struct spi_nor_erase_type
*erase,
004 const u8 erase_type)
005 {
006 int i;
007
008 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
009 if (!(erase[i].size && erase_type &
BIT(erase[i].idx)))
010 continue;
011 if (region->size & erase[i].size_mask) {
012 spi_nor_region_mark_overlay(region);
013 return;
014 }
015 }
016 }

2. Change the call location of the spi_nor_region_mark_end function from the end of the
spi_nor_init_non_uniform_erase_map function to after the loop, which changes the erase
property of each region.

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Code Listing 9 Modify the initialization of the non-uniform erase map function
001 static int
002 spi_nor_init_non_uniform_erase_map(struct spi_nor *nor,
003 struct spi_nor_flash_parameter
*params,
004 const u32 *smpt)
005 {
006
007 ......
008
009 /* Populate regions. */
010 for (i = 0; i < region_count; i++) {
011 j = i + 1; /* index for the region dword */
012 region[i].size = SMPT_MAP_REGION_SIZE(smpt[j]);
013 erase_type = SMPT_MAP_REGION_ERASE_TYPE(smpt[j]);
014 region[i].offset = offset | erase_type;
015
016 spi_nor_region_check_overlay(&region[i], erase,
erase_type);
017
018 /*
019 * Save the erase types that are supported in all
regions and
020 * can erase the entire flash memory.
021 */
022 uniform_erase_type &= erase_type;
023
024 /*
025 * regions_erase_type mask will indicate all the
erase types
026 * supported in this configuration map.
027 */
028 regions_erase_type |= erase_type;
029
030 offset = (region[i].offset &
~SNOR_ERASE_FLAGS_MASK) +
031 region[i].size;
032 }
033 spi_nor_region_mark_end(&region[i - 1]);
034
035 ......
036
037 return 0;
038 }

4.4 Modify drivers/mtd/spi-nor/spansion.c

Currently, the ownership of the SEMPER™ NOR flash memory is Infineon, but in the Linux source code from
Xilinx, a part of the source code related to the Infineon-specific characteristics of NOR flash memory is still
included in spansion.c as a convention that has been used for a long time. It is expected that the file will be
changed to infineon.c in the future, but at this point it is entirely up to Xilinx, so you should add the necessary
contents to the current spansion.c file.

Application Note 17 of 23 002-33855 Rev.**

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4.4.1 Add SPI NOR fixups structure and create fixup functions
To correct the parsing result of the basic flash parameter table (BFPT) and serial flash discoverable parameter
(SFDP), create a fixups structure for this. The structure consists of three function pointers that provide places
for a correction of the page program buffer size, a correction of the sector size, and a masking of the commands
not supported by the SEMPER™ NOR flash memory. This must reflect the changes such as in configuration
registers.

4.4.2 Add SEMPER™ flash memory devices

The SEMPER™ NOR flash memory ID for each product must be registered. If the device used is a custom order
part or has a value different from the following, you can change it appropriately. Code Listing 13 shows an
example from the 256-Mbit to 4-Gbit device of 3 V and 1.8 V SEMPER™ QSPI NOR flash memory.

4.4.3 Modify the source code

1. Add the s25hx_t_post_bfpt_fixups function. This function modifies the result of parsing the basic
flash parameter table (BFPT).
Code Listing 10 Add the s25hx_t_post_bfpt_fixups function
001 static int s25hx_t_post_bfpt_fixups(struct spi_nor *nor,
002 const struct sfdp_parameter_header
*bfpt_header,
003 const struct sfdp_bfpt *bfpt,
004 struct spi_nor_flash_parameter *params)
005 {
006 u8 cfr3v;
007 int ret;
008
009 /* Address mode affects Read/Write Any Register
operations */
010 ret = spansion_set_4byte_addr_mode(nor, true);
011 if (ret)
012 return ret;
013 nor->addr_width = 4;
014
015 /* The page_size is set to 512B by BFPT but it depends
on CFR3V[4] */
016 ret = spansion_read_any_reg(nor,
SPINOR_REG_CYPRESS_CFR3V, 0, &cfr3v);
017 if (ret)
018 return ret;
019
020 if (!(cfr3v & SPINOR_REG_CYPRESS_CFR3V_PGSZ))
021 params->page_size = 256;
022
023 /* Replace Quad Enable with non-volatile version */
024 params->quad_enable = s25hx_t_quad_enable;
025
026 return 0;
027 }

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2. Add the s25hx_t_post_sfdp_fixups function. This function modifies the result of parsing the serial flash
discoverable parameter (SFDP).
Code Listing 11 Add the s25hx_t_post_sfdp_fixups function
001 void s25hx_t_post_sfdp_fixups(struct spi_nor *nor)
002 {
003 /* Fast Read 4B requires mode cycles */
004 nor->params->reads[SNOR_CMD_READ_FAST].num_mode_clocks =
8;
005
006 s25hx_t_fix_erase_map(nor);
007 }

3. Add a spi_nor_fixups structure variable named s25hx_t_fixups and initialize it by creating default,
BFPT, and SFDP hook functions.
Code Listing 12 Add the s25hx_t_post_sfdp_fixups function
001 static struct spi_nor_fixups s25hx_t_fixups = {
002 .post_bfpt = s25hx_t_post_bfpt_fixups,
003 .post_sfdp = s25hx_t_post_sfdp_fixups
004 };

4. Add the following SEMPER™ NOR flash memory ID and sector geometry information to a flash_info
structure variable named spansion_parts.
Code Listing 13 Add the s25hx_t_post_sfdp_fixups function
001 { "s25hl256t", INFO6(0x342a19, 0x0f0390, 256 * 1024,
128,
002 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
003 .fixups = &s25hx_t_fixups },
004 { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024,
256,
005 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
006 .fixups = &s25hx_t_fixups },
007 { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024,
512,
008 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
009 .fixups = &s25hx_t_fixups },
010 { "s25hl02gt", INFO6(0x342a1c, 0x0f0390, 256 * 1024,
1024,
011 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
012 .fixups = &s25hx_t_fixups },
013 { "s25hl04gt", INFO6(0x342a1d, 0x0f0390, 256 * 1024,
2048,
014 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
015 .fixups = &s25hx_t_fixups },

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016 { "s25hs256t", INFO6(0x342b19, 0x0f0390, 256 * 1024,

128,
017 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
018 .fixups = &s25hx_t_fixups },
019 { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024,
256,
020 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
021 .fixups = &s25hx_t_fixups },
022 { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024,
512,
023 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
024 .fixups = &s25hx_t_fixups },
025 { "s25hs02gt", INFO6(0x342b1c, 0x0f0390, 256 * 1024,
1024,
026 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
027 .fixups = &s25hx_t_fixups },
028 { "s25hs04gt", INFO6(0x342b1d, 0x0f0390, 256 * 1024,
2048,
029 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ
| USE_CLSR)
030 .fixups = &s25hx_t_fixups },

4.5 Modify include/linux/mtd/spi-nor.h

1. The SEMPER™ NOR flash memory has more registers than previous generations of the flash memory. Thus,
new commands and register addresses have been added to access each register. Add the following
definitions:
Code Listing 14 Add commands and addresses of Any Registers
001 #define SPINOR_OP_EN4BA 0xb7 /* Enter 4-byte mode */
002 #define SPINOR_OP_EX4BA 0xb8 /* Exit 4-byte mode */
003 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
004 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
005
006 #define SPINOR_REG_CYPRESS_CFR1V 0x00800002
007 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003
008 #define SPINOR_REG_CYPRESS_CFR3V 0x00800004
009 #define SPINOR_REG_CYPRESS_CFR4V 0x00800005
010 #define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN BIT(1) /* Quad
Enable */
011 #define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page
size. */

Application Note 20 of 23 002-33855 Rev.**

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Support for SEMPER™ Quad SPI flash in Linux from Xilinx

Conclusion

5 Conclusion
It may be difficult to patch files for updating the source code when the target source code is being frequently
updated. If the source code is not directly managed by Infineon, it is difficult to predict the time of the change,
and it is difficult to maintain consistency in the change due to the supported by many contributors from
externals.
With this approach, you can determine the scope of changes with each release and apply the appropriate patch
file for major releases of the Linux source code from Xilinx.

Application Note 21 of 23 002-33855 Rev.**

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Support for SEMPER™ Quad SPI flash in Linux from Xilinx

Revision history

Revision history
Document Date of release Description of changes
version
** 2021-09-16 New application note

Application Note 22 of 23 002-33855 Rev.**

2021-09-16
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