MR20H40 / MR25H40

MR20H40 - 50MHz/20ns tSCK (Industrial Temp Range) 4Mb SPI Interface MRAM
MR25H40 - 40MHz/25ns tSCK (Industrial, Extended and AEC-Q100 Grade 1 Temp Range) 4Mb SPI Interface MRAM
For more information on product options, see “Table 16 – Ordering Part Numbers” on page 25.

FEATURES
•  No write delays
•  Unlimited write endurance
•  Data retention greater than 20 years
•  Automatic data protection on power loss 8-DFN

•  Fast, simple SPI interface, up to 50 MHz clock rate with MR20H40.

•  3.0 to 3.6 Volt power supply range
•  Low-current sleep mode
•  Industrial (-40 to 85°C), Extended (-40 to 105°C), and AEC-Q100
8-DFN Small Flag
Grade 1 (-40 to 125°C) temperature range options.
•  Available in 8-pin DFN or 8-pin DFN Small Flag, RoHS-compliant
packages. RoHS
•  Direct replacement for serial EEPROM, Flash, and FeRAM
•  MSL Level 3

DESCRIPTION
MR2xH40 is a family of 4,194,304-bit magnetoresistive random access memory (MRAM) devices
organized as 524,288 words of 8 bits. They are the ideal memory solution for applications that must
store and retrieve data and programs quickly using a small number of I/O pins. They have serial EE-
PROM and serial Flash compatible read/write timing with no write delays and unlimited read/write
endurance. Unlike other serial memories, with the MR2xH40 family both reads and writes can occur
randomly in memory with no delay between writes.
The MR2xH40 family provides highly reliable data storage over a wide range of temperatures. The
MR20H40 (50MHz) is offered with Industrial (-40° to +85 °C) range. The MR25H40 (40MHz) is offered
with Industrial (-40° to +85 °C), Extended (-40 to 105°C), and AEC-Q100 Grade 1 (-40°C to +125 °C)
operating temperature range options.
Both are available in a 5 x 6mm, 8-pin DFN package. The pinout is compatible with serial SRAM,
EEPROM, Flash, and FeRAM products.

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TABLE OF CONTENTS

OVERVIEW.............................................................................................................................................5
Figure 1 – Block Diagram............................................................................................................................................ 5
System Configuration......................................................................................................................5
Figure 2 – System Configuration.............................................................................................................................. 5
Pin Functions....................................................................................................................................6
Figure 3 – DFN Package Pin Diagram (Top View)............................................................................................... 6
Table 1 – Pin Functions................................................................................................................................................ 6
SPI COMMUNICATIONS PROTOCOL....................................................................................................7
Command Codes...............................................................................................................................7
Table 2 – Command Codes........................................................................................................................................ 7
Status Register, Memory Protection and Block Write Protection.................................................8
Table 3 – Status Register Bit Assignments............................................................................................................ 8
Memory Protection Modes..............................................................................................................8
Table 4 – Memory Protection Modes..................................................................................................................... 8
Block Protection Modes...................................................................................................................9
Table 5 – Block Memory Write Protection............................................................................................................. 9
Read Status Register (RDSR)......................................................................................................... 10
Figure 4 – Read Status Register (RDSR) Timing.................................................................................................10
Write Enable (WREN)..................................................................................................................... 10
Figure 5 – Write Enable (WREN) Timing...............................................................................................................10
Write Disable (WRDI)..................................................................................................................... 11
Figure 6 – Write Disable (WRDI) Timing...............................................................................................................11
Write Status Register (WRSR)....................................................................................................... 11
Figure 7 – Write Status Register (WRSR) Timing...............................................................................................11
Read Data Bytes (READ)................................................................................................................ 12
Figure 8 – Read Data Bytes (READ) Timing.........................................................................................................12

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Table of Contents (Cont’d)
Write Data Bytes (WRITE).............................................................................................................. 12
Figure 9 – Write Data Bytes (WRITE) Timing.......................................................................................................13
Enter Sleep Mode (SLEEP)............................................................................................................. 13
Figure 10 – Enter Sleep Mode (SLEEP) Timing...................................................................................................13
Exit Sleep Mode (WAKE)................................................................................................................ 14
Figure 11 – Exit Sleep Mode (WAKE) Timing......................................................................................................14
ELECTRICAL SPECIFICATIONS.......................................................................................................... 15
Absolute Maximum Ratings......................................................................................................... 15
Table 6 – Absolute Maximum Ratings ...............................................................................................................15
Table 7 – Operating Conditions..............................................................................................................................16
Table 8 – DC Characteristics.....................................................................................................................................16
Table 9 – Power Supply Characteristics...............................................................................................................17
TIMING SPECIFICATIONS.................................................................................................................. 18
Capacitance.................................................................................................................................... 18
Table 10 – Capacitance..............................................................................................................................................18
AC Measurement Conditions........................................................................................................ 18
Table 11 – AC Measurement Conditions.............................................................................................................18
Figure 12 – Output Load for Impedance Parameter Measurements........................................................18
Figure 13 – Output Load for all Other Parameter Measurements..............................................................18
Power Up Timing........................................................................................................................... 19
Table 12 – Power-Up Timing....................................................................................................................................19
Figure 14 – Power-Up Timing.................................................................................................................................19
AC Timing Parameters................................................................................................................... 20
Table 13 – MR20H40 (fSCK = 50MHz) AC Timing Parameters......................................................................20
Table 14 – MR25H40 (fSCK = 40MHz) AC Timing Parameters......................................................................21

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Table of Contents (Cont’d)
Figure 15 – Synchronous Data Timing.................................................................................................................23
Figure 16 –  HOLD Timing.........................................................................................................................................23
PART NUMBERS AND ORDERING..................................................................................................... 24
Table 15 – Part Numbering System.......................................................................................................................24
Table 16 – Ordering Part Numbers........................................................................................................................25
PACKAGE OUTLINE DRAWINGS........................................................................................................ 26
Figure 17 –  DFN Package Outline.........................................................................................................................26
Figure 18 – DFN Small Flag Package.....................................................................................................................27
REVISION HISTORY............................................................................................................................ 28
HOW TO REACH US............................................................................................................................ 29

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OVERVIEW
The MR2xH40 family is an SPI interface MRAM family with a memory array logically organized as 512Kx8
using the four pin interface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the
serial peripheral interface (SPI) bus. The MRAM implements a subset of commands common to SPI EEPROM
and SPI Flash components. This allows the SPI MRAM to replace these components in the same socket
and interoperate on a shared SPI bus. The SPI MRAM offers superior write speed, unlimited endurance, low
standby & operating power, and simple, reliable data retention compared to other serial memory alterna-
tives.

Figure 1 – Block Diagram
WP Instruction Decode
CS Clock Generator
HOLD Control Logic
SCK Write Protect
512Kb x 8
MRAM ARRAY
Instruction Register

Address Register 19 8
Counter

SO
SI Data I/O Register

Nonvolatile Status
Register

System Configuration
Single or multiple devices can be connected to the bus as shown in Figure 2. Pins SCK, SO and SI are com-
mon among devices. Each device requires CS and HOLD pins to be driven separately.

Figure 2 – System Configuration
SCK

MOSI

MISO

SO SI SCK SO SI SCK
SPI EVERSPIN SPI MRAM 1 EVERSPIN SPI MRAM 2
Micro Controller
CS HOLD CS HOLD

CS1

HOLD 1

CS2

HOLD 2
MOSI = Master Out Slave In
MISO = Master In Slave Out

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Pin Functions

Figure 3 – DFN Package Pin Diagram (Top View)

CS 1 8 VDD

SO 2 7 HOLD

WP 3 6 SCK

VSS 4 5 SI

Table 1 – Pin Functions
Signal
Pin I/O Function Description
Name
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
CS 1 Input Chip Select
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
The data output pin is driven during a read operation and remains Hi-Z at
SO 2 Output Serial Output all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
A low on the write protect input prevents write operations to the Status
WP 3 Input Write Protect
Register.
Refer-
VSS 4 Ground Power supply ground pin.
ence
All data is input to the device through this pin. This pin is sampled on the
SI 5 Input Serial Input rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
Synchronizes the operation of the MRAM. The clock can operate up to 50
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
SCK 6 Input Serial Clock on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
HOLD 7 Input Hold
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.

VDD 8 Supply Power Supply Power supply voltage from +3.0 to +3.6 volts.

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SPI COMMUNICATIONS PROTOCOL
The MR2xH40 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1).
For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling
edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high.
The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when
CS falls.
All memory transactions start when CS is brought low to the memory. The first byte is a command code.
Depending upon the command, subsequent bytes of address are input. Data is either input or output.
There is only one command performed per CS active period. CS must go inactive before another command
can be accepted. To ensure proper part operation according to specifications, it is necessary to terminate
each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial
or aborted accesses.
Command Codes
Table 2 – Command Codes
Instruction Description Binary Code Hex Code Address Bytes Data Bytes
WREN Write Enable 0000 0110 06h 0 0
WRDI Write Disable 0000 0100 04h 0 0
RDSR 1 Read Status Register 0000 0101 05h 0 1
WRSR Write Status Register 0000 0001 01h 0 1
READ Read Data Bytes 0000 0011 03h 3 1 to ∞
WRITE Write Data Bytes 0000 0010 02h 3 1 to ∞
SLEEP Enter Sleep Mode 1011 1001 B9h 0 0
WAKE Exit Sleep Mode 1010 1011 ABh 0 0

Note:
1. An RDSR command cannot immediately follow a READ command. If an RDSR command immediately follows a READ com-
mand, the output data will not be correct. Any other sequence of commands is allowed. If an RDSR command is required
immediately following a READ command, it is necessary that another command be inserted before the RDSR is executed.
Alternatively, two successive RDSR commands can be issued following the READ command. The second RDSR will output the
proper state of the Status Register.

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Status Register, Memory Protection and Block Write Protection
The status register consists of the 8 bits listed in Table 3. As seen in Table 4, the Status Register Write Disable
bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) to provide hardware
memory block protection. Bits BP0 and BP1 define the memory block arrays that are protected as described
in Table 5. The fast writing speed of the MR2xH40 does not require write status bits. The state of bits 6,5,4,
and 0 can be user modified and do not affect memory operation. All bits in the status register are pre-set
from the factory in the “0” state.

Table 3 – Status Register Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SRWD Don’t Care Don’t Care Don’t Care BP1 BP0 WEL Don’t Care

Memory Protection Modes

When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0
and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1,
status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD,
BP0 and BP1.

Table 4 – Memory Protection Modes

Status
WEL SRWD WP Protected Blocks Unprotected Blocks
Register
0 X X Protected Protected Protected
1 0 X Protected Writable Writable
1 1 Low Protected Writable Protected
1 1 High Protected Writable Writable

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Block Protection Modes
The memory enters hardware block protection when the WP input is low and the Status Register Write Dis-
able (SRWD) bit is set to 0. The memory leaves hardware block protection only when the WP pin goes high.
While WP is low, the write protection blocks for the memory are determined by the status register bits BP0
and BP1 and cannot be modified without taking the WP signal high again.
If the WP signal is high (independent of the status of SRWD bit), the memory is in software protection mode.
This means that block write protection is controlled solely by the status register BP0 and BP1 block write pro-
tect bits and this information can be modified using the WRSR command.

Table 5 – Block Memory Write Protection

Status Register Memory Contents

BP1 BP0 Protected Area Unprotected Area
0 0 None All Memory

0 1 Upper Quarter Lower Three-Quarters

1 0 Upper Half Lower Half

1 1 All None

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Read Status Register (RDSR)
The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can be
read to check the status of write enable latch bit, status register write protect bit, and block write protect
bits. For MR2xH40, the write in progress bit (bit 0) is not written by the memory because there is no write
delay. The RDSR command is entered by driving CS low, sending the command code, and then driving CS
high. An RDSR command cannot immediately follow a READ command. If an RDSR command immediately
follows a READ command, the output data will not be correct. Any other sequence of commands is allowed.
If an RDSR command is required immediately following a READ command, it is necessary that another com-
mand be inserted before the RDSR is executed. Alternatively, two successive RDSR commands can be issued
following the READ command. The second RDSR will output the proper state of the Status Register.

Figure 4 – Read Status Register (RDSR) Timing

CS

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Mode 3

SCK Mode 0

SI 0 0 0 0 0 1 0 1
MSB
Status Register Out
SO High Impedance
7 6 5 4 3 2 1 0
High Z

MSB

Write Enable (WREN)

Figure 5 – Write Enable (WREN) Timing
CS

Mode 3 0 1 2 3 4 5 6 7 Mode 3

SCK Mode 0 Mode 0

Instruction (06h)

SI 0 0 0 0 0 1 1 0

High Impedance
SO

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register (bit 1). The
Write Enable Latch must be set prior to writing either bit in the status register or the memory. The WREN
command is entered by driving CS low, sending the command code, and then driving CS high.

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Write Disable (WRDI)
The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 1) to 0.
This prevents writes to status register or memory. The WRDI command is entered by driving CS low, sending
the command code, and then driving CS high.
The Write Enable Latch (WEL) is reset to 0 on power-up or when the WRDI command is completed.

Figure 6 – Write Disable (WRDI) Timing

CS
Mode 3 0 1 2 3 4 5 6 7 Mode 3

SCK Mode 0 Mode 0

Instruction (04h)

SI 0 0 0 0 0 1 0 0

High Impedance
SO
Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. The
WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a WREN
command while pin WP and the Status Register SRWD (Bit 7) correspond to values that make the status reg-
ister writable as seen in Table 4 on page 8. Status Register bits are non-volatile with the exception of the
WEL which is reset to 0 upon power cycling.

The WRSR command is entered by driving CS low, sending the command code and status register write data
byte, and then driving CS high.

Figure 7 – Write Status Register (WRSR) Timing

CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 3

SCK Mode 0

Instruction (01h) Status Register In

SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0
MSB
High Impedance
SO

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Read Data Bytes (READ)
The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the
24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are read out sequentially
from memory until the read operation is terminated by bringing CS high. The entire memory can be read in
a single command. The address counter will roll over to 0000H when the address reaches the top of memo-
ry.
The READ command is entered by driving CS low and sending the command code. The memory drives the
read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi-
nated by bringing CS high.

Figure 8 – Read Data Bytes (READ) Timing

CS
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

SCK

Instruction (03h) 24-Bit Address

SI 0 0 0 0 0 0 1 1 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
SO 7 6 5 4 3 2 1 0 7
MSB

Write Data Bytes (WRITE)

The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by
the 24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are written sequen-
tially in memory until the write operation is terminated by bringing CS high. The entire memory can be
written in a single command. The address counter will roll over to 0000H when the address reaches the top
of memory.
Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed
without write delays or data polling. Back to back WRITE commands to any random location in memory can
be executed without write delay. MRAM is a random access memory rather than a page, sector, or block
organized memory so it is ideal for both program and data storage.
The WRITE command is entered by driving CS low, sending the command code, and then sequential write
data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS
high.

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Figure 9 – Write Data Bytes (WRITE) Timing

CS
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

SCK

Instruction (02h) 24-Bit Address

SI 0 0 0 0 0 0 1 0 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
High Impedance
SO

CS
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3

SCK Mode 0

Data Byte 2 Data Byte 3 Data Byte N

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
High Impedance
SO

Enter Sleep Mode (SLEEP)

The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall
chip standby power to 15 μA typical. The SLEEP command is entered by driving CS low, sending the com-
mand code, and then driving CS high. The standby current is achieved after time, tDP. If power is removed
when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid
command following SLEEP mode entry is a WAKE command.

Figure 10 – Enter Sleep Mode (SLEEP) Timing

CS
t DP
0 1 2 3 4 5 6 7 Mode 3

SCK Mode 0

Instruction (B9h)

SI 1 0 1 1 1 0 0 1

Active Current Standby Current Sleep Mode Current

SO

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Exit Sleep Mode (WAKE)
The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.
The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.
The memory returns to standby mode after tRDP. The CS pin must remain high until the tRDP period is over.
WAKE must be executed after sleep mode entry and prior to any other command.

Figure 11 – Exit Sleep Mode (WAKE) Timing

CS
t RDP
0 1 2 3 4 5 6 7 Mode 3

SCK Mode 0

Instruction (ABh)

SI 1 0 1 0 1 0 1 1

Sleep Mode Current Standby Current

SO

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ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or electric
fields. However, it is advised that normal precautions be taken to avoid application of any voltage greater
than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid
application of any magnetic field more intense than the maximum field intensity specified in the maximum
ratings.
Table 6 – Absolute Maximum Ratings
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to
recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability.

Symbol Parameter Conditions Value Unit

VDD Supply voltage 2 -0.5 to 4.0 V

VIN Voltage on any pin 2 -0.5 to VDD + 0.5 V

IOUT Output current per pin ±20 mA

PD Package power dissipation 3 0.600 W

Commercial -45 to 95 °C

Industrial -45 to 95 °C
TBIAS Temperature under bias
Extended -45 to 115 °C

AEC-Q100 Grade 1 -45 to 135 °C

Tstg Storage Temperature -55 to 150 °C

TLead Lead temperature during solder (3 minute max) 260 °C

Hmax_write Maximum magnetic field during write Write 12,000 A/m

Maximum magnetic field during read or

Hmax_read Read or Standby 12,000 A/m
standby

Notes:
1. All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than 0.5V. The AC value of
VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than 20mA.

2. Power dissipation capability depends on package characteristics and use environment.

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Table 7 – Operating Conditions
Symbol Parameter Temp Grade Min Max Unit
VDD Power supply voltage 3.0 3.6 V

VIH Input high voltage 2.2 VDD + 0.3 V

VIL Input low voltage -0.5 0.8 V

Commercial 0 70 °C

Industrial -40 85 °C
TA Ambient temperature under bias
Extended -40 105 °C

AEC-Q100 Grade 1 1 -40 125 °C

Notes:
1. AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years out of 20-year life.)

Table 8 – DC Characteristics
Symbol Parameter Conditions Min Max Unit
ILI Input leakage current - ±1 μA

ILO Output leakage current - ±1 μA

IOL = +4 mA - 0.4 V
VOL Output low voltage
IOL = +100 μA - VSS + 0.2v V

IOH = -4 mA 2.4 - V
VOH Output high voltage
IOH = -100 μA VDD - 0.2 - V

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Table 9 – Power Supply Characteristics
Symbol Parameter Conditions Typical Max Unit
@ 1 MHz 5.0 11 mA

IDDR Active Read Current @ 40 MHz 12 17 mA

@ 50MHz 13.8 18.5 mA

@ 1 MHz 9.0 25 mA

IDDW Active Write Current @ 40 MHz 28 42 mA

@ 50 MHz 33 46.5 mA

@ 40 MHz 250 400 μA

ISB1 AC Standby Current (CS High)
@ 50 MHz 650 750 μA

ISB2 CMOS Standby Current (CS High) 90 180 μA

IZZ Standby Sleep Mode Current (CS High) 15 40 μA

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TIMING SPECIFICATIONS

Capacitance

Table 10 – Capacitance
Symbol Parameter Typical Max Unit
CIn Control input capacitance 1 - 6 pF

CI/O Input/Output capacitance 1 - 8 pF

Notes:

1. ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.

AC Measurement Conditions

Table 11 – AC Measurement Conditions

Parameter Value Unit
Logic input timing measurement reference level 1.5 V
Logic output timing measurement reference level 1.5 V
Logic input pulse levels 0 or 3.0 V
Input rise/fall time 2 ns
Output load for low and high impedance parameters See Figure 12
Output load for all other timing parameters See Figure 13

Figure 12 – Output Load for Impedance Parameter Measurements

ZD= 50 Ω
Output

RL = 50 Ω

VL = 1.5 V

Figure 13 – Output Load for all Other Parameter Measurements

3.3 V

590 Ω
Output
435 Ω 30 pF

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Power Up Timing
The MR2xH40 is not accessible for a start-up time, tPU= 400 μs after power up. Users must wait this time
from the time when VDD (min) is reached until the first CS low to allow internal voltage references to become
stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up
sequence.

Table 12 – Power-Up Timing
Symbol Parameter Min Typical Max Unit
VWI Write Inhibit Voltage 2.2 - - V

tPU Startup Time 400 - - μs

Figure 14 – Power-Up Timing
VDD
VDD(max)
Chip Selection not allowed

VDD(min)
Reset state t PU Normal Operation
of the
device
VWI

Time

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AC Timing Parameters

Table 13 – MR20H40 (fSCK = 50MHz) AC Timing Parameters

Industrial Temperature Range, VDD=3.0 to 3.6 V, CL= 30 pF for all values.
Symbol Parameter Temp Range Min Typical Max Unit
fSCK SCK Clock Frequency Industrial 0 - 50 MHz
tRI Input Rise Time Industrial - - 50 ns
tRF Input Fall Time Industrial - - 50 ns
tWH SCK High Time Industrial 7 - - ns
tWL SCK Low Time Industrial 7 - - ns

Synchronous Data Timing see Figure 15

tCS CS High Time Industrial 40 - - ns
tCSS CS Setup Time Industrial 5 - - ns
tCSH CS Hold Time Industrial 5 - - ns
tSU Data In Setup Time Industrial 2 - - ns
tH Data In Hold Time Industrial 5 - - ns
tV Output Valid Industrial 0 - 9 ns
tHO Output Hold Time Industrial 0 - - ns

HOLD Timing see Figure 16

tHD HOLD Setup Time Industrial 5 - - ns
tCD HOLD Hold Time Industrial 5 - - ns
tLZ HOLD to Output Low Impedance Industrial - - 20 ns

tHZ HOLD to Output High Imped-

Industrial - - 20 ns
ance
Other Timing Specifications
tWPS WP Setup To CS Low Industrial 5 - - ns
tWPH WP Hold From CS High Industrial 5 - - ns
tDP Sleep Mode Entry Time Industrial 3 - - μs
tRDP Sleep Mode Exit Time Industrial 400 - - μs
tDIS Output Disable Time Industrial 12 - - ns

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 MR20H40 / MR25H40
Table 14 – MR25H40 (fSCK = 40MHz) AC Timing Parameters
Industrial, Extended and AEC-Q100 Grade 1 Temperature Ranges, VDD=3.0 to 3.6 V, CL= 30 pF for all values.
Symbol Parameter Temp Grade Min Typical Max Unit
fSCK SCK Clock Frequency All 0 - 40 MHz
tRI Input Rise Time All - - 50 ns
tRF Input Fall Time All - - 50 ns
tWH SCK High Time All 11 - - ns
tWL SCK Low Time All 11 - - ns

Synchronous Data Timing see Figure 15

tCS CS High Time All 40 - - ns
tCSS CS Setup Time All 10 - - ns
tCSH CS Hold Time All 10 - - ns
tSU Data In Setup Time All 5 - - ns
tH Data In Hold Time All 5 - - ns

Industrial/Extended 0 - 9 ns
tV Output Valid
AEC-Q100 Grade 1 0 - 10 ns
tHO Output Hold Time All 0 - - ns

Table continues next page.

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 MR20H40 / MR25H40
Table 14 (Cont’d) - MR25H40 (fSCK = 40MHz) AC Timing Parameters
Industrial, Extended and AEC-Q100 Grade 1 Temperature Ranges, VDD=3.0 to 3.6 V, CL= 30 pF for all values.
HOLD Timing see Figure 16
Symbol Parameter Temp Grade Min Typical Max Unit
tHD HOLD Setup Time All 10 - - ns
tCD HOLD Hold Time All 10 - - ns
tLZ HOLD to Output Low Impedance All - - 20 ns
tHZ HOLD to Output High Impedance All - - 20 ns

Other Timing Specifications

tWPS WP Setup To CS Low All 5 - - ns
tWPH WP Hold From CS High All 5 - - ns
tDP Sleep Mode Entry Time All 3 - - μs
tRDP Sleep Mode Exit Time All 400 - - μs
tDIS Output Disable Time All 12 - - ns

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 MR20H40 / MR25H40
Figure 15 – Synchronous Data Timing

Figure 16 –  HOLD Timing

CS
tCD
tCD

SCK

tHD
tHD

HOLD
tHZ tLZ

SO

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 MR20H40 / MR25H40
PART NUMBERS AND ORDERING
Table 15 – Part Numbering System
Product Family Number MR 25H 40
Memory Interface Density Revision Temp Package Grade
Ordering Part Number MR 25H 40 C DC ES
MRAM MR
50 MHz Serial Family 20H
40 MHz Serial Family 25H
256 Kb 256
512 Kb 512
1 Mb 10
4 Mb 40
No Revision Blank
Revision A A
Revision B B
Commercial 0 to 70°C Blank
Industrial -40 to 85°C C
Extended -40 to 105°C V
AEC Q-100 Grade 1 -40 to 125°C M
8-pin DFN in Tray DC
8-pin DFN Tape and Reel DCR
8-pin DFN (small flag) in Tray DF
8-pin DFN (small flag) Tape and Reel DFR
Engineering Samples ES
Customer Samples Blank
Mass Production Blank
Product Family Number and Ordering Part Number given are for illustration only.

Copyright © Everspin Technologies 2018 24 MR20H40 / MR25H40 Revision 12.4 3/2018

 MR20H40 / MR25H40
Table 16 – Ordering Part Numbers
Speed Tempera- Shipping Con-
Temp Grade Package Order Part Number
Grade ture tainer
8-DFN Small Trays MR20H40CDF
50MHz Industrial -40 to +85 C
Flag Tape and Reel MR20H40CDFR
Trays MR25H40CDC 1
8-DFN 1
Tape and Reel MR25H40CDCR 1
Industrial -40 to +85 C
8-DFN Small Trays MR25H40CDF
Flag Tape and Reel MR25H40CDFR
40 MHz
8-DFN Small Trays MR25H40VDF
Extended -40 to +105 C
Flag Tape and Reel MR25H40VDFR

8-DFN Small Trays MR25H40MDF

AEC-Q100 Grade 1 -40 to +125 C
Flag Tape and Reel MR25H40MDFR

Note:
1. The DC pckage option (8-DFN) is not recommended for new designs. Please select the DF (8-DFN small
flag) option for new designs.

Copyright © Everspin Technologies 2018 25 MR20H40 / MR25H40 Revision 12.4, 3/2018

 MR20H40 / MR25H40
PACKAGE OUTLINE DRAWINGS
Figure 17 –  DFN Package Outline

Exposed metal Pad. Do not

connect anything except VSS

A
5 8

DAP Size
4.4 x 4.4
J
B
I
L
G
H
M

Pin 1 Index 4 1
C Detail A F
K N

D E
Detail A

Dimension A B C D E F G H I J K L M N
Max. 5.10 6.10 1.00 1.27 0.45 0.05 0.35 0.70 4.20 4.20 0.261 0.05
C0.35 R0.20
Min. 4.90 5.90 0.90 BSC 0.35 0.00 Ref. 0.50 4.00 4.00 0.195 0.00

Notes:

1. Reference JEDEC MO-229.

2. All dimensions are in mm. Angles in degrees.
3. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm.
4. Warpage shall not exceed 0.10 mm.

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 MR20H40 / MR25H40

Figure 18 – DFN Small Flag Package

Exposed metal Pad. Do not

connect anything except VSS

A
2X 0.10 C
5 8

2X 0.10 C
J
B
I
G L

M H

Pin 1 Index 4 1
C Detail A F
K N

D E
Detail A

Dimension A B C D E F G H I J K L M N
Max. 5.10 6.10 0.90 1.27 0.45 0.05 1.60 0.70 2.10 2.10 .210 0.05
C0.45 R0.20
Min. 4.90 5.90 0.80 BSC 0.35 0.00 1.20 0.50 1.90 1.90 .196 0.00

Notes:

1. Reference JEDEC MO-229.

2. All dimensions are in mm. Angles in degrees.
3. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm.
4. Warpage shall not exceed 0.10 mm.

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 MR20H40 / MR25H40
REVISION HISTORY
Revision Date Description of Change
0 Jan 15, 2010 Product Concept Release
0 .1 Feb. 23, 2010 Fixed typos in text.
1 May 5, 2010 Removed commercial specifications. All parts meet industrial specifications.
Preliminary Product Release. Updated description of status register non-volatility, WAKE
2 Jan 11, 2011
command, Table 3.4.
Removed DIP package part to seperate datasheet. Added inset detail for mechanical pack-
3 Apr 25, 2011
age drawings.
September 22, Added AEC-Q100 Grade 1 ordering option. Revised Table 3.1, Table 3.2, Table 3.4, Table 4.4
4
2011 revised and Note 2 deleted, revised Figure 5.1 and Table 5.1.
Corrected VOL in Table 3.3 to read VOL Max = VSS + 0.2v. Corrected SI waveform in Figure 2.8.
New Small Flag DFN package option added to Page 1 Features and available parts Table 5.1.
5 Nov 18, 2011 DFN Small Flag drawing and dimensions table added as Figure 6.2. Figure 6.1, DFN Pack-
age, cleaned up with better quality drawing and dimension table. No specifications were
changed in Figure 6.1.

CDF and CDFR options changed to Preliminary. Added Small Flag DFN illustrations. Refor-
matted all parametric tables. Revised 8-DFN package drawing to show correct proportion
6 August 23, 2012
for flag and package. Added MR20H40 as 50MHz speed option. Deleted large flag DFN
ordering option for AEC-Q100 products. Corrected errors in DFN package outline drawings.

January 17,
7 Removed Preliminary status from MR25H40CDF, CDFR.
2013

8 May 24, 2013 Removed Preliminary status from MR20H40CDF(R), and from MR20H40DF(R).

Removed Preliminary status from 25H40MDF(R). VWI max to unspecified from TBD. Added
9 March 28, 2014
MSL-3 status to the Features list.

10 July 11, 2014 MR20H40DF and MR20H40DFR withdrawn from sales status.

11 August 13, 2014 Added Extended temperature grade offering.

11.1 May 19, 2015 Revised Everspin contact information.

11.2 June 11, 2015 Corrected Japan Sales Office telephone number.

December 9,
12.0 Clarification of RDSR command operation.
2015

Minor edits to the revised RDSR command operation. Corrected wrong bit number for the
December 18, WEL in the WRDI command description. Clarification of SRWD bit location in the Status Reg-
12.1
2015 ister within the WRSR command description. Condensed Note 1 in Table 2, referring to RDSR
operation after a READ command.

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 MR20H40 / MR25H40
REVISION HISTORY - Cont’d
Revision Date Description of Change
December 13, Change all large flag DFN options to “The DC pckage option (8-DFN) is not recommended
12.2
2016 for new designs. Please select the DF (8-DFN small flag) option for new designs.”

12.3 February 2, 2017 Added tHO and tV relationship to Synchronous Data Timing

12.4 March 23, 2018 Updated the Contact Us table

Copyright © Everspin Technologies 2018 29 MR20H40 / MR25H40 Revision 12.4, 3/2018

 MR20H40 / MR25H40
HOW TO REACH US

Everspin Technologies, Inc.

How to Reach Us: Information in this document is provided solely to enable system and soft-
Home Page: ware implementers to use Everspin Technologies products. There are no
express or implied licenses granted hereunder to design or fabricate any
www.everspin.com
integrated circuit or circuits based on the information in this document.
Everspin Technologies reserves the right to make changes without further
World Wide Information Request notice to any products herein. Everspin makes no warranty, representa-
WW Headquarters - Chandler, AZ tion or guarantee regarding the suitability of its products for any particu-
lar purpose, nor does Everspin Technologies assume any liability arising
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out of the application or use of any product or circuit, and specifically
Chandler, Arizona 85226 disclaims any and all liability, including without limitation consequential
Tel: +1-877-480-MRAM (6726) or incidental damages. “Typical” parameters, which may be provided in
Local Tel: +1-480-347-1111 Everspin Technologies data sheets and/or specifications can and do vary
Fax: +1-480-347-1175 in different applications and actual performance may vary over time. All
operating parameters including “Typicals” must be validated for each cus-
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tomer application by customer’s technical experts. Everspin Technologies
[email protected] does not convey any license under its patent rights nor the rights of oth-
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into the body, or other applications intended to support or sustain life, or
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for any other application in which the failure of the Everspin Technologies
Everspin Europe Support product could create a situation where personal injury or death may oc-
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such unintended or unauthorized application, Buyer shall indemnify and
Japan hold Everspin Technologies and its officers, employees, subsidiaries, affili-
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penses, and reasonable attorney fees arising out of, directly or indirectly,
[email protected] any claim of personal injury or death associated with such unintended or
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Copyright © Everspin Technologies 2018 30 MR20H40 / MR25H40 Revision 12.4 3/2018