Introduction to Analog Layout

Design

Dr. S. L. Pinjare
School Of ECE, REVA University

23 January 2016 1
 Analog VLSI Design
• Implementation of analog circuits and systems using integrated
circuit technology.
• Unique Features of Analog IC Design
– Customized design
– Designed at the circuit level.
– Geometry is an important part of the design.
– Usually implemented as a mixed analog- digital circuit
• Typically Analog is 20% and digital 80% of the chip area.
– Analog requires 80% of the design time
• Requires more iterations
– Passes for success: 2-3 for analog, 1 for digital.
• In general, analog circuits are more complex than digital.
– Need to have good knowledge of both circuit analysis, modeling and
technology
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 Analog Design Flow
• Electrical Design
• Physical Design
• Fabrication and Testing
• Final Product

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 Analog Design Flow
Electrical Design Idea Concept

Define the Design

Comparison with the Redesign Implementation
Design Specification
Simulation

Physical
Design

Fabrication
Testing and Product
Development
23 January 2016 4
 Analog Design Flow
Electrical Design Idea Concept

Define the Design

Comparison with the Redesign Implementation
Design Specification
Simulation

Physical Implementation-Layout
Physical
Design Physical Verification-DRC, ERC, LVS, Antenna

Parasitic Extraction and Back Annotation

Fabrication
Testing and Product
Development
23 January 2016 5
 Analog Design Flow
Electrical Design Idea Concept

Define the Design

Comparison with the Redesign Implementation
Design Specification
Simulation

Physical Implementation-Layout
Physical
Design Physical Verification-DRC,ERC,LVS,Antenna

Parasitic Extraction and Back Annotation

Fabrication Fabrication
Testing and Product
Development
23 January 2016 6
 Analog Design Flow
Electrical Design Idea Concept

Define the Design

Comparison with the Redesign Implementation
Design Specification
Simulation

Physical Implementation-Layout
Physical
Design Physical Verification-DRC,ERC,LVS,Antenna

Parasitic Extraction and Back Annotation

Fabrication Fabrication
Testing and Product
Development Testing PRODUCT
23 January 2016 7
 The Layers
• Layers in a Typical process
Align Purpose Mask CIF
to
1 Active notch Defines Active area CAA 43
2 Pwell 1 Pwell and also sidewall implants(STI) CWP 41
3 Nwell 1 Nwell and also sidewall implants CWN 42
4 Poly 1 Poly gate CPG 46
5 N Select 1 Source drain implants / nLDD implants CSN 45
6 P Select 1 Source drain implants/ pLDD implants CSP 44
7 Contact 4 Defines contacts to poly and active CCP or 47,48
CCA
8 Metal 1 7 First level metal interconnect CMF 49
9 Via1 8 Via between m1 and m2 CVA 50
10 Metal 2 9 Defines second level metal interconnect CMS 51
11 Pad OVGL 10 Defines bond pad openings COG 52
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 Analog Design components
• Active devices
– Transistors
• N-mos and P-mos
• Passives
– Resistors
– Capacitors
– Inductors
• Implemented using existing layers and masks
– Possibly adding a few extra layers

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 The transistor-NMOS
• Four terminal Device
– NMOS Bulk terminal is tied
to p substrate which is tied to
Vss: Ground terminal
• Layers required :
– P-Well (in twin well process)
– N-select
– P-Select
– Active
– Poly
– Contact

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 The transistor-PMOS
• PMOS
• Bulk terminal is tied to N-
Well which is tied to Vdd:
• Layers required :
– N-Well (in twin well process)
– P-select,
– N-Select
– Active
– Poly
– Contact

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 Design of an OpAMP
• Specification
– VDD = 1.8 V
– VSS = 0 V
– Power Dissipation < 0.3 mW
– Load = 2 pF
– Slew rate = 20V/msec
– ICMR+ = 1.6 V
– ICMR_ = 0.8V
– DC gain = 60db = 1000
– Phase Margin = 60o
– Unity Gain BW = 30 MHz

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 Design
Using Slew rate and load estimate 20 uA
current
Using Phase margin and load 800 fF
determine miller capacitance Cc
Using GBW estimate (W/L) of 6
M1 and M2
Using ICMR+ estimate size (W/L) 14
of M3 and M4
Using ICMR- estimate size (W/L) 12
of M5
Using Phase Margin size M6; 174
Using Current requirement size 75
M7(I7= 125 uA)
Using Current requirement size 12
M8(I7= 20 uA)

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 Drawing Wide Transistor
• M6 W/L = 174
.

Active, Poly, Contact and M1

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 MOS transistor Layout
• Non-uniform
current flow

Most of the current

will be shrunk to
this side

M1 Mn
M1 carries the
most current and
Mn carries the
least current).

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 Drawing Wide Transistor
• M6 W/L = 174
.

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 MOS transistor Layout
• Parasitic resistance at source and drain must be kept as
low as possible
• Gate series resistance must be minimized
– Series resistance slows down switching speed
– Also introduces unwanted noise.
• Parasitic source/substrate & drain/substrate capacitances
must be minimized
– Parasitic capacitance slows down switching speed
– Increases power dissipation(Capacitance switching)
– Additional load capacitance
• Need to increase bias current to maintain bandwidth and/or slew rate.
• Can lead to instability in high gain feedback systems.

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 Layout of MOS Transistors
• Criteria for MOS Transistor Layout
– Minimize source/drain resistances.
– Minimize source/substrate & drain/substrate parasitic
capacitances.
– Minimize gate series resistance.
• Parasitic aware layout

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 Layout of MOS Transistors
• Criteria for MOS Transistor Layout
– Minimize source/drain resistances.
– Minimize source/substrate & drain/substrate parasitic
capacitances.
– Minimize gate series resistance.
• Parasitic aware layout

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 Parasitic aware layout
• Multiple Contacts or one big contact

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 MOS transistor Layout
• Reliability issues : Curvature in metal Layer- Can lead
to microfracture

Can lead to Electromigration

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 Layout of MOS Transistors
• Multiple contacts at source/drain
– Current is spread
– Smaller source/drain resistances

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 Parasitic aware layout
• Multiple Contacts or one big contact
• Multiple contacts at source/drain
– High reliability
• Better contact at source/drain
– Smaller contact resistance
» R = Rc/N, where N=number of contacts

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 Layout of MOS Transistors
• Multiple contacts at source/drain
– Current is spread
– Smaller source/drain resistances
• Series resistance is negligible but lateral resistance still
exists.
• Large source/substrate and drain/substrate parasitic
capacitances.

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 Layout of MOS Transistors
• Parasitics in transistor
– Large gate series resistance- Gate is too long.
• Contacts are not allowed on the gate above the channel
– high temperature required to form contacts may destroy
the thin gate oxide.

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 Layout of MOS Transistors
• Poly contact at both ends

Wide transistors need to be split

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 MULTI-GATE FINGER LAYOUT
• Parallel connection of n elements (n = 4 for this
example)
– Reduces the gate resistance of the poly-silicon
• Capacitance unchanged, Large area

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 Multifinger Layout-Shared sources/drains
• Contact space is shared among s d d
transistors s s
• Reduced silicon area.
– Minimizes source/substrate &
drain/substrate parasitic
capacitances.
• important for high speed

Cs = ¾ Cs’
Cd = ½ Cd’

Note that parasitic

capacitors are lesser at
the drain
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 Folding
• Folding reduces gate resistance
• Shared source/drain , Reduced silicon area.

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 Layout of MOS Transistors
• Minimize Source/Substrate and Drain/Substrate Parasitic
Capacitances
– Shared sources/drains.

Another layout

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 Analog layout Issues
• Noise is important in all analog circuits because it limits
dynamic range.

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 Analog layout Issues
• Noise is important in all analog circuits because it limits
dynamic range.
– Body Contact
– Higher neutral body resistance

• Single Body Contact more substrate noise

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 Substrate contact
• Generous use of
SUBSTRATE PLUGS
– help to reduce the resistance
of the neutral body region,
• Minimizes the noise
contributed by this
resistance.
– minimizes substrate noise
because it provides a low
impedance path to ground
for the noise current

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 Substrate contact

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 Layout of a Cascode circuit

Shared Source
Drain

a.

Shared Source
Drain-multifinger
Layout
b. c.
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 Common Terminal

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23 January 2016 School of ECE, REVA Unversity 37
 Antenna Effect
• Metal Etching
• There will be charge accumulation on Metal1 during plasma
etching (of metal1) causing damage to thin gate oxide (Large
metal area)

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 Antenna Effect
• Metal Etching
• There will be charge accumulation on Metal1 during plasma
etching (of metal1) causing damage to thin gate oxide (Large
metal area)

Avoids antenna effect

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 Antenna Effect
• RIE of Poly silicon

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 • Make connections at M1 level.

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 Analog layout Issues
• Matching components
– In analog electronics it is often necessary to have matched
pairs of devices with identical electrical properties, e.g. input
transistors of a differential stage, and current mirror

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 Layout of Matched Transistors
• Matched transistors are used extensively in both analog
and digital CMOS circuits.
– In theory two device with the same size have the same
electrical properties.

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 Layout of Matched Transistors
• Matched transistors are used extensively in both analog
and digital CMOS circuits.
– In theory two device with the same size have the same
electrical properties.

In reality there is always process variations

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 Silicon is anisotropic
• Ion implantation is performed at an angle causing
shadow
• Source and drain may not be symmetric due to ion
implantation angle,
– neccessary to avoid implant depth issues (channeling).

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 Photo-lithographic invariance (PLI)
• Lithography effects are different in different direction.
• Orientation is important in analog circuits for matching
purposes
– C and D are better
– Maintain orientation

C. Gate aligned
D. Parallel gate:

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 Photo-lithographic invariance (PLI)
• Gate aligned
• Parallel gate:
– Two drains have different
surroundings
– Two sources have different
surroundings
• Current flows in the same
direction

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 Well Proximity Effect
• High energy ion implants to form the well.
• Scattering from the edge of the photoresist mask, and embedding
in the silicon surface (near well edge).
• Transistors close to the well edge will therefore have different
properties.
• This is known as the well proximity effect (WPE). Important for
matching.

As with S/D,
implantation angle may
render the scattering
and doping asymmetric
23 January 2016 School of ECE, REVA Unversity 48
 • Shallow trench isolation strains the active area of the
transistor. Influcences mobility and threshold voltage
(stress induced enhancement or suppression of dopant
diffusion).
• Distance between gate and STI impacts perfomance.
• Important for matching.

23 January 2016 School of ECE, REVA Unversity 49

 Matching

• Layout techniques to minimize the errors introduced by

process variations.
• Two electrically equivalent components: A and B
– Drawn identically
– A and B have same shape in
area and perimeter
– Are they Identical ?
– Do they have the same
surrounding?

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 Matching

• Layout techniques to minimize the errors introduced by

process variations.
• Two electrically equivalent components: A and B
– Drawn identically
– A and B have same shape in
area and perimeter
– Are they Identical ?
– Do they have the same
surrounding?

–No?

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 Unit Matching

• Layout techniques to minimize the errors introduced by

process variations.
• Two electrically equivalent components. A and B
– Use Dummies to have
identical surroundings

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 Layout of Matched Transistors
• Add dummy
transistors to
improve symmetry

• Presence of Metal line over • Replicate Metal line over

M2 destroys symmetry M1 improves symmetry

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 Metal Interconnections
• Both the transistor should have same surrounding.
• Unbalanced metal routing will cause the transistors to
see different source voltage.
• Also, distribute reference as current, not bias voltage.

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23 January 2016 School of ECE, REVA Unversity 55
 Unit matching
• Gradient along x-axis destroys symmetry

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 Process Variation
• Process variations can locally be approximated with a
linear gradient.
• Example: Desired Resistor values ; A= 7 units and B = 7
units
• Changed due to Gradient as follows.
• A= 5 units and B = 9 units

5 9

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 Process variations

• can locally be approximated with a linear gradient.

(a): A1 + A2 < B1 + B2
(b): A1 + A2 = B1 + B2 (Common-centroid layout)

2 3 4 5

2 3 4 5

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 Common Centroid Layouts

Cross
coupled

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 Common Centroid Layouts

Tiled

23 January 2016 60
 Common Centroid Layout
• Gradients are compensated
• Poly and metal interconnections are
complex

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23 January 2016 School of ECE, REVA Unversity 62
 Common Centroid Layouts
• Mitigates variation in both x and Y direction

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23 January 2016 64
 M1,2 S

M1 G M2G

M2D
23 January 2016
M1 D 65
 Common Centroid Layout

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 Matched Transistors-Interdigitized Layout Style
• Inter-digitized layout style Averages the process
variations among transistors
– Common terminal is like a serpentine
– Two matched transistors with one common terminal
– Split the transistor in two equal parts
– 4 fingers for each transistors, Arrange AABBAABB

2 3

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 Matched Transistors

To achieve both common-centroid

and PLI matched transistors has to
be split into 4 fingers. AABBBBAA
M
M
M1 G
1 M2D
M1,2 S

M1,2 S
M1 D
M2G
23 January 2016 68
 Matched Transistors
• Or ABBAABBA
• Use dummies if needed
• Uneven total drain area between A and B.
– This is undesirable for ac conditions:
– capacitors and other parameters may not be equal
– A more robust approach

2 3

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 Matched Transistors
M1M2 M2M1 M1M2 M2M1 M1M2
1 2 3 4 5 6 7 8 9 10

M1 1+4+5+8+9 =27
M2 2+3 +6+7+10 = 28

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 Dummy Devices at the Ends

• Dummies are shorted transistors

– Adds to parasitics

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 Interdigital layout

• Split into parallel connections of even parts,

• Half of them will have the drain at the right side and half at the left,
• Be careful how you route the common terminal

M2 M1 M1 M2 M2 M1 M1 M2
M1 M2 M2 M1 M1 M2 M2 M1

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 M2 M1 M1 M2 M2 M1 M1 M2
M1 M2 M2 M1 M1 M2 M2 M1

M1D
M2 G

M1 G
M1,2 S

M2 D

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23 January 2016 74
 Resistors

• All materials have a resistivity

• Typical resistivities
– Metal layer : 0.1 Ohm/square
– n/p-plus contacts and polysilicon: 10-100 Ohm/square
– n-well: 1000 Ohm/square
– low doped poly silicon: 10 k Ohm/square
• more well defined than n-well, i.e. higher accuracy

23 January 2016 75
 Poly-Resistors
• Poly Resistors
– Silicidated poly resistors: 1 − 10 Ohm/sq.
• ≈±30%
– Non-silicidated poly resistors: 50-1000 Ohms per sq.
• ≈±20%
• Small parasitic capacitances to substrate.
• Superior linearity.
• High cost due to the extra mask needed to block silicide layer.

23 January 2016 76
 Diffusion Resistors
• 100-1000 Ohm/sq
– N-well
• Large error : ≈±40%
• Resistance is strongly terminal voltage-dependent and highly nonlinear.
– Depletion width varies with terminal voltages. The cross-section
area varies with terminal voltages
• noisy as all disturbances/noise from substrate can be coupled directly
onto the resistors
• Large parasitic capacitance between n-well and substrate.

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 Ion Implanted
• 500-2000 ohms/square
• Accuracy = ±15%
• Parasitic capacitance to substrate is voltage dependent.
• Piezoresistance effects occur due to chip strain from
mounting

23 January 2016 78
 Metal Resistor
• Low resistance

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 Resistor Layout
• Standard Resistors: Avoid 90 degree angle. 45 degree is
recommended

1. Resistance at the corners cannot Recommended resistor

be estimated accurately layout
2. Current flow at the corner is not
uniform

23 January 2016 80
 Corner Correction

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 Resistor Layout
• Dummy resistors are added to minimizes the effect of process
variation

23 January 2016 82
 Shielded Resistors
• Shielding resistors Layout of shielded resistors
– Connected to a constant voltage (S = shielding resistors)
source
• Prevent self-coupling of the
resistor R/inter-coupling
with others.
• Widely used in analog/RF
design.
• Caution
– a mutual capacitance between
the resistor and its shield exist.

23 January 2016 83
 Layout of Large Resistors
• Use n-well resistors
– have a large sheet resistance.
• Enclosed by a substrate shielding ring, also known as guard ring,
to isolate the resistors from neighboring devices.

23 January 2016 84
 Process Bias Influence on Resistors
• Process bias is where the dimensions of the fabricated
geometries are not the same as the layout data base
dimensions.
• Process biases introduce systematic errors.

23 January 2016 85
 Etch Rate Variations – Polysilicon Resistors
• The size of the area to be etched determines the etch
rate. Smaller areas allow less access to the etchant while
larger areas allow more access to the etchant.

23 January 2016 86
 Etch Rate Variations – Polysilicon Resistors
• The size of the area to be etched determines the etch
rate. Smaller areas allow less access to the etchant while
larger areas allow more access to the etchant.

It may be advisable to connect the dummy strips to ground or

some other low impedance node to avoid static electrical charge
buildup.
23 January 2016 87
 Diffusion Interaction – Diffused Resistors
• Consider three adjacent p+ diffusions into a n epitaxial
region,

• If A, B, and C are resistors that are to be matched, we see that the effective
concentration of B is larger than A or C because of diffusion interaction. This
would cause the B resistor to be smaller even though the geometry is identical.
• Solution: Place identical dummy resistors to the left of A and right of C.
Connect the dummy resistors to a low impedance to prevent the formation of
floating diffusions that might increase the sensitivity to latchup.

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 Thermoelectric Effects

• The thermoelectric effect, also called the Seebeck effect,

is a potential difference that is developed between two
dissimilar materials that are at different temperatures.
• Two possible resistor layouts with regard to the
thermoelectric effect:

23 January 2016 89
 • High sheet resistivity resistors must use p+ or n+ in order to make
contacts to metal. Thus, there is plenty of opportunity for the
thermoelectric effect to cause problems if care is not taken. Below
are three high sheet resistor layouts with differing thermoelectric
performance.

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 Layout of Matched Resistors
• Inter-Digitized Layout
– Minimizes the effect of process variation in x-direction.
• Dummy resistors are added to ensure both resistors have
the exactly same environment.

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 Matched Resistors with Temperature Consideration
• Keep away from power devices

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 Resistor layout guidelines-Matched resistors
• Use same material
• Identical geometry, same orientation
• Close proximity, interdigitate arrayed resistors
• Use dummy elements
• Place resistors in Low stress area
• Place resistors away from power devices
• Use electrostatic shielding

23 January 2016 93
 Capacitors

• There are naturally capacitors between each layer of

metal, polysilicon or silicon
• Dielectrics between different metal layers have a
thickness of 0.5-1 micron, which gives a rather large
area for a given capacitance.
• Key Parameters
– Capacitance per unit area
• Larger specific capacitance (capacitance per unit area)
gives smaller area
– Linearity
– Parasitic capacitance to substrate
– Series resistance - resistance of capacitor plates

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 Types of IC Capacitors
• Poly-diffusion capacitors • Poly-poly capacitors
– .6-.8 fF/µm2(≈±5%). – 0.3 - 0.5 fF/µm2; (≈±10%).
– Matching 0.2% Matching 0.5%
– Nonlinear bottom-plate parasitic – Not available in standard
capacitance.≈20% of inter-plate CMOS processes
capacitance. • Metal-poly capacitors
• MOS capacitors – 0.03-0.05 fF/µm2. (≈±25%).
– 0.6 - 0.8 fF/µm2; (≈±5%). Matching 0.5%
– Matching 0.5% – Capacitance is small, area
– Stable capacitance in strong consuming.
inversion • Metal-metal capacitors
– Non-negligible channel – 0.02-0.04 fF/µm2; (≈±25%).
resistance lowers the quality Matching 0.1%
factor (Q) of the capacitor – Capacitance is small, area
consuming

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 Pn junction capacitor
• Generally made by
diffusion into the well
• Layout: Minimize the
distance between the p+
and n+ diffusions.

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 MOS Gate Capacitor

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 Poly Poly Capacitors

• Highly stable capacitors

• small bottom plate

parasitic

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 Metal-Insulator-Metal (MiM) Capacitors

• In some processes, there is a thin dielectric between a

metal layer and a special metal layer called “capacitor
top metal”. Typically the capacitance is around 1fF/μm2
and is at the level below top metal.
• Good matching is possible with low parasitics

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 Capacitor Errors
• Edge Effects
• There will always be a randomness on the definition of
the edge. However, etching can be influenced by the
presence of adjacent structures.

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 NON-IDEAL EFFECTS- UNDER-CUT
• Non-uniform undercut &/or edge
fringing field effects change the
value of designed capacitors.
• The area and perimeter ratio is
preserved if we use layout Ideal case: no undercut
utilizing unit capacitors. Case 1 Case 2
Area 1:4 1:4
Perimeter 1:2 1:4
Case 1 Typical case: 0.05 undercut
Case 1 Case 2
Area 1:4.46 1:4
P erimeter 1:2.1 1:4
Case 2
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 NON-IDEAL EFFECTS-Corner Rounding
• Etching always causes
corner rounding to
some extent.
• This means that
– 90° corners will be
eroded and
– 270° corners will be
have incomplete
removal of material
• In order to overcome
this effect use an equal
number of 90° & 270°
corners

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 Layout of Matched Capacitors
• Oxide Gradients: Error
due to a variation in
dielectric thickness across
the wafer.
• Minimize the Effect of
Oxide Thickness in both x
and y-directions.
– Common Centroid Structure.
• Dummy capacitors are
needed to ensure the same
environment for C1 and C2.

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 Layout of Matched Capacitors
• C1 and C2 are 2-poly capacitors.
• n-well is employed as a charge
collector to shield the interaction
between the bottom plate and
substrate.
• n-well is biased at multiple
points and connected to a
constant voltage source.

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 Are there any thing else you can improve?
Is there full symmetry between C1 and C2?
23 January 2016 105
 Decreasing Sensitivity to Edge Variation

Insensitive to alignment errors

Sensitive to alignment errors in and the flux reaching the bottom
the upper and lower plates and plate is larger resulting in large
loss of capacitance flux (smaller capacitance.
capacitance).
A structure that minimizes the ratio of perimeter to area (circle is
best).

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 Accurate Matching of Capacitors
• Accurate matching of capacitors depends on the
following influence:
– Mismatched perimeter ratios
– Proximity effects in unit capacitor photolithography
– Mismatched long-range fringe capacitance
– Mismatched interconnect capacitance
– Parasitic interconnect capacitance

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 Long-range fringe capacitance
• Long-range fringe capacitance

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 References

• A. Hastings, The Art of Analog Layout, Prentice-

Hall,2002.
• B. Razavi, Design of Analog CMOS Integrated Circuits,
McGraw-Hill, 2001.

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 Summary
• Use large area to reduce random error
• Common Centroid layout to reduce linear gradient errors
• Use unit element arrays
• Interdigitize for matching
• Use of symmetry (photolithographic invariance)
• Dummy device for similar vicinity
• Guard rings for isolation

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 Thank You

23 January 2016 111