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18eet43 Digital Logic Circuits: P.Karthikeyan

Hazard

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56 views15 pages

18eet43 Digital Logic Circuits: P.Karthikeyan

Hazard

Uploaded by

Anonymous xaeuoo4
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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18EET43 DIGITAL LOGIC

CIRCUITS

Hazard

P.Karthikeyan

19-May-21
Hazards

 Hazards are the unwanted switching transient


that may appear at the output of the digital
circuit.
 Such hazards may result in a malfunction in the
output of the circuit.
 The propagation delay associated with the logic
gates in the circuit is the main cause of hazard.
 propagation delay : It is the time interval between
the application of the input pulse and the
occurrence of the output.
 Hazards occur in combinational circuits, which
will cause faulty operation.
19-May-21
Hazards

 Hazards will also occur in asynchronous


sequential circuits where logic gates are used,
affecting the stable state.

 There are two main types of hazard:


 Static Hazard and
 Dynamic Hazard.

19-May-21
Static and Dynamic Hazard
 When the input to the logic circuit changes, the
output has to remain at a particular logic, but
instead it may change its value momentarily. If
this happens in the logic circuit, then there exists
a static hazard.
 The static hazard can be classified as a
 static-0 hazard and
 static-1 hazard.
 Instead of remaining at logic 1, the output goes
to logic 0 momentarily, then it is a static-1
hazard.
 Similarly, if the output monetarily goes to logic 1,
instead of remaining at 0, it is a static-0 hazard.
19-May-21
Static and Dynamic Hazard

A hazard is said to be
dynamic if the output changes
two or more times when
it should change from
1 to 0 or from 0 to 1.

19-May-21
Illustration of static hazard

19-May-21
Illustration of static hazard

19-May-21
Illustration of static hazard

19-May-21
Static and Dynamic Hazard
 Eliminating Hazards in digital circuit
 Now let us consider an example.
 Construct a hazard-free logic circuit for a
boolean function
 f(A, B, C, D) = ∑ m(0, 2, 6, 7, 8, 10, 12).
 For the given expression,
 let us implement the k-map.

19-May-21
Static and Dynamic Hazard

19-May-21
Static and Dynamic Hazard

19-May-21
Static and Dynamic Hazard

19-May-21
Essential Hazards

 Another type of hazard that may occur in


asynchronous sequential circuits is called
an essential hazard.
 This type of hazard is caused by unequal delays
along two or more paths that originate from the
same input.
 An excessive delay through an inverter circuit in
comparison to the delay associated with the
feedback path may cause such a hazard.

19-May-21
Static and Dynamic Hazard

 Essential hazards cannot be corrected by adding


redundant gates as in static hazards.
 The problem that they impose can be corrected
by adjusting the amount of delay in the affected
path.
 To avoid essential hazards, each feedback loop
must be handled with individual care to ensure
that the delay in the feedback path is long
enough compare d with delays of other signals
that originate from the input terminals.

19-May-21
19-May-21

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