16-Bit 1 MSPS PulSAR®

Unipolar ADC with Reference

AD7667
FEATURES FUNCTIONAL BLOCK DIAGRAM
2.5 V internal reference: typical drift 3 ppm/°C REFBUFIN REF REFGND DVDD DGND
Guaranteed max drift 15 ppm/°C
AGND OVDD
Throughput: AD7667
AVDD
SERIAL OGND
1 MSPS (Warp mode) REF
PORT
800 kSPS (Normal mode) 16
IN
666 kSPS (Impulse mode) SWITCHED DATA[15:0]
INGND CAP DAC
INL: ±2.0 LSB max (±0.0038% of full scale) BUSY
PDREF PARALLEL
16-bit resolution with no missing codes INTERFACE RD
PDBUF CLOCK
S/(N+D): 88 dB min @ 20 kHz PD
CS

THD: –96 dB max @ 20 kHz RESET

CONTROL LOGIC AND
CALIBRATION CIRCUITRY
SER/PAR

Analog input voltage range: 0 V to 2.5 V OB/2C

03035-0-001
No pipeline delay BYTESWAP

Parallel and serial 5 V/3 V interface WARP IMPULSE CNVST

SPI®/QSPI /MICROWIRE /DSP compatible

TM TM Figure 1.
Single 5 V supply operation
Power dissipation Table 1. PulSAR Selection
87 mW typ @ 666 kSPS, 130 µW @ 1 kSPS without REF 800–
Type/kSPS 100–250 500–570 1000
133 mW typ @1 MSPS with REF
Pseudo- AD7651 AD7650/AD7652 AD7653
48-lead LQFP and 48-lead LFCSP packages
Differential AD7660/AD7661 AD7664/AD7666 AD7667
Pin-to-pin compatible with AD7671, AD7677
True Bipolar AD7663 AD7665 AD7671
True AD7675 AD7676 AD7677
APPLICATIONS Differential
Data acquisition 18-Bit AD7678 AD7679 AD7674
Medical instruments Multichannel/ AD7654
Digital signal processing Simultaneous AD7655
Battery-powered systems
Process control PRODUCT HIGHLIGHTS
1. Fast Throughput.
GENERAL DESCRIPTION The AD7667 is a 1 MSPS, charge redistribution, 16-bit SAR
The AD7667 is a 16-bit, 1 MSPS, charge redistribution SAR ADC with internal error correction circuitry.
analog-to-digital converter that operates from a single 5 V 2. Superior INL.
power supply. The part contains a high speed 16-bit sampling The AD7667 has a maximum integral nonlinearity of
ADC, an internal conversion clock, internal reference, error 2.0 LSBs with no missing 16-bit codes.
correction circuits, and both serial and parallel system inter- 3. Internal Reference.
face ports. It features a very high sampling rate mode (Warp), a The AD7667 has an internal reference with a typical
fast mode (Normal) for asynchronous applications, and a temperature drift of 3 ppm/°C.
reduced power mode (Impulse) for low power applications
where power is scaled with the throughput. The AD7667 is 4. Single-Supply Operation.
hardware factory-calibrated and comprehensively tested to The AD7667 operates from a single 5 V supply. In Impulse
ensure ac parameters such as signal-to-noise ratio (SNR) and mode, its power dissipation decreases with throughput.
total harmonic distortion (THD) in addition to the more 5. Serial or Parallel Interface.
traditional dc parameters of gain, offset, and linearity. Operation Versatile parallel or 2-wire serial interface arrangement is
is specified from –40°C to +85°C. compatible with both 3 V and 5 V logic.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD7667

TABLE OF CONTENTS
Specifications..................................................................................... 3 Digital Interface.......................................................................... 22

Timing Specifications....................................................................... 5 Parallel Interface......................................................................... 22

Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 22

ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 23

Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 24

Definitions of Specifications ......................................................... 11 Microprocessor Interfacing....................................................... 26

Typical Performance Characteristics ........................................... 12 Application Hints ........................................................................... 27

Circuit Information ........................................................................ 16 Bipolar and Wider Input Ranges .............................................. 27

Converter Operation.................................................................. 16 Layout .......................................................................................... 27

Typical Connection Diagram ................................................... 18 Evaluating the AD7667’s Performance .................................... 27

Power Dissipation versus Throughput .................................... 20 Outline Dimensions ....................................................................... 28

Conversion Control.................................................................... 21 Ordering Guide .......................................................................... 28

REVISION HISTORY
Revision 0: Initial Version.

Rev. 0 | Page 2 of 28
 AD7667

SPECIFICATIONS
Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range VIN – VINGND 0 VREF V
Operating Input Voltage VIN –0.1 +3 V
VINGND –0.1 +0.5 V
Analog Input CMRR fIN = 100 kHz 64 dB
Input Current 1 MSPS Throughput 19 µA
Input Impedance1
THROUGHPUT SPEED
Complete Cycle In Warp Mode 1 µs
Throughput Rate In Warp Mode 1 1000 kSPS
Time between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 1.25 µs
Throughput Rate In Normal Mode 0 800 kSPS
Complete Cycle In Impulse Mode 1.5 µs
Throughput Rate In Impulse Mode 0 666 kSPS
DC ACCURACY
Integral Linearity Error –2.0 +2.0 LSB2
No Missing Codes 16 Bits
Differential Linearity Error –1.0 +1.5 LSB
Transition Noise 0.7 LSB
Unipolar Zero Error, TMIN to TMAX3 ±25 LSB
Unipolar Zero Error Temperature Drift ±1.0 ppm/°C
Full-Scale Error, TMIN to TMAX3 REF = 2.5 V ±0.08 % of FSR
Full-Scale Error Temperature Drift ±1.0 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB
AC ACCURACY
Signal-to-Noise fIN = 20 kHz 88 89.2 dB4
Spurious Free Dynamic Range fIN = 20 kHz 96 105 dB
Total Harmonic Distortion fIN = 20 kHz –104 –96 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz 88 89 dB
–60 dB Input, fIN = 20 kHz 30 dB
–3 dB Input Bandwidth 13 MHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 250 ns
REFERENCE
Internal Reference Voltage VREF @ 25°C 2.493 2.5 2.507 V
Internal Reference Temperature Drift –40°C to +85°C ±3 ±15 ppm/°C
Output Voltage Hysteresis –40°C to +85°C 50 ppm
Long-Term Drift 100 ppm/1000 Hours
Line Regulation AVDD = 5 V ± 5% ±15 ppm/V
Turn-On Settling Time CREF = 10 µF 5 ms
Temperature Pin
Voltage Output @ 25°C 300 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4 kΩ
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 1 MSPS Throughput 242 µA

Rev. 0 | Page 3 of 28
AD7667
Parameter Conditions Min Typ Max Unit
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 V
VIH 2.0 DVDD + 0.3 V
IIL –1 +1 µA
IIH –1 +1 µA
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL ISINK = 1.6 mA 0.4 V
VOH ISOURCE = –500 µA OVDD – 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.257 V
Operating Current8 1 MSPS Throughput
AVDD9 With Reference and Buffer 18.7 mA
AVDD10 Reference and Buffer Alone 3 mA
DVDD11 7.8 mA
OVDD11 200 µA
Power Dissipation without REF9, 11 666 kSPS Throughput 87 115 mW
1 kSPS Throughput 130 µW
Power Dissipation with REF8, 9 1 MSPS Throughput 133 145 mW
TEMPERATURE RANGE12
Specified Performance TMIN to TMAX –40 +85 °C

1
See Analog Input section.
2
LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.
3
See Definitions of Specifications section. These specifications do not include the error contribution from the external reference.
4
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5
Parallel or serial 16-bit.
6
Conversion results are available immediately after completed conversion.
7
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8
In Warp mode.
9
With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.
10
With PDREF, PDBUF LOW and PD HIGH.
11
Impulse mode. Tested in parallel reading mode
12
Consult factory for extended temperature range.

Rev. 0 | Page 4 of 28
 AD7667

TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter Symbol Min Typ Max Unit
Refer to Figure 33 and Figure 34
Convert Pulse Width t1 10 ns
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1 t2 1/1.25/1.5 µs
CNVST LOW to BUSY HIGH Delay t3 35 ns
BUSY HIGH All Modes except Master Serial Read after Convert t4 0.75/1/1.25 µs
Aperture Delay t5 2 ns
End of Conversion to BUSY LOW Delay t6 10 ns
Conversion Time t7 0.75/1/1.25 µs
Acquisition Time t8 250 ns
RESET Pulse Width t9 10 ns
Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t10 0.75/1/1.25 µs
DATA Valid to BUSY LOW Delay t11 12 ns
Bus Access Request to DATA Valid t12 45 ns
Bus Relinquish Time t13 5 15 ns
Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay t14 10 ns
CS LOW to Internal SCLK Valid Delay2 t15 10 ns
CS LOW to SDOUT Delay t16 10 ns
CNVST LOW to SYNC Delay t17 25/275/525 ns
SYNC Asserted to SCLK First Edge Delay t18 3 ns
Internal SCLK Period3 t19 25 40 ns
Internal SCLK HIGH3 t20 12 ns
Internal SCLK LOW3 t21 7 ns
SDOUT Valid Setup Time3 t22 4 ns
SDOUT Valid Hold Time3 t23 2 ns
SCLK Last Edge to SYNC Delay3 t24 3 ns
CS HIGH to SYNC HI-Z t25 10 ns
CS HIGH to Internal SCLK HI-Z t26 10 ns
CS HIGH to SDOUT HI-Z t27 10 ns
BUSY HIGH in Master Serial Read after Convert3 t28 See Table 4
CNVST LOW to SYNC Asserted Delay t29 0.75/1/1.25 µs
SYNC Deasserted to BUSY LOW Delay t30 25 ns
Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)2
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 3 18 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 25 ns
External SCLK HIGH t36 10 ns
External SCLK LOW t37 10 ns

1
In Warp mode only, the time between conversions is 1ms; otherwise there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3
In Serial Master Read During Convert mode. See Table 4 for Serial Master Read After Convert Mode.

Rev. 0 | Page 5 of 28
AD7667
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns
Internal SCLK Period Minimum t19 25 50 100 200 ns
Internal SCLK Period Maximum t19 40 70 140 280 ns
Internal SCLK HIGH Minimum t20 12 22 50 100 ns
Internal SCLK LOW Minimum t21 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 80 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 55 130 290 ns
BUSY HIGH Width Maximum t24 1.5 2 3 5.25 µs

Rev. 0 | Page 6 of 28
 AD7667

ABSOLUTE MAXIMUM RATINGS

Table 5. AD7667 Stress Ratings1
1.6mA IOL
Parameter Rating
IN2, TEMP2, REF, REFBUFIN, AVDD + 0.3 V to
INGND, REFGND to AGND AGND – 0.3 V TO OUTPUT 1.4V
PIN CL
Ground Voltage Differences 60pF*
AGND, DGND, OGND ±0.3 V
500µA IOH
Supply Voltages

03033-0-002
AVDD, DVDD, OVDD –0.3 V to +7 V * IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
AVDD to DVDD, AVDD to OVDD ±7 V CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
DVDD to OVDD –0.3 V to +7 V
Figure 2. Load Circuit for Digital Interface Timing,
Digital Inputs –0.3 V to DVDD + 0.3 V SDOUT, SYNC, SCLK Outputs CL = 10 pF
PDREF, PDBUF3 ±20 mA
Internal Power Dissipation4 700 mW
Internal Power Dissipation5 2.5 W 2V
Junction Temperature 150°C 0.8V
tDELAY tDELAY
Storage Temperature Range –65°C to +150°C

03033-0-003
2V 2V
Lead Temperature Range 0.8V
0.8V
(Soldering 10 sec) 300°C
Figure 3. Voltage Reference Levels for Timing
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2
See Analog Input section.
3
See the Voltage Reference Input section.
4
Specification is for the device in free air:
48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W.
5
Specification is for the device in free air:
48-Lead LFCSP; θJA = 26°C/W

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 7 of 28
AD7667

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFBUFIN

REFGND
PDBUF
PDREF

INGND
AGND
AGND
AVDD
TEMP

REF
NC
IN
48 47 46 45 44 43 42 41 40 39 38 37

AGND 1 PIN 1
36 AGND
AVDD 2 IDENTIFIER 35 CNVST
NC 3 34 PD
BYTESWAP 4 33 RESET
OB/2C 5 32 CS
WARP 6 AD7667 31 RD
IMPULSE 7 TOP VIEW 30 DGND
(Not to Scale)
SER/PAR 8 29 BUSY
D0 9 28 D15
D1 10 27 D14
D2/DIVSCLK0 11 26 D13
D3/DIVSCLK1 12 25 D12

13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT D5/INVSYNC

D11/RDERROR
OGND
OVDD

D8/SDOUT
D6/INVSCLK
D7/RDC/SDIN

DVDD
DGND

D9/SCLK
D10/SYNC
D4/EXT/INT

03035-0-004
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 36, 41, 42 AGND P Analog Power Ground Pin.
2, 44 AVDD P Input Analog Power Pin. Nominally 5 V.
3, 40 NC No Connect.
6 WARP DI Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest
mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in
order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the
minimum conversion rate.
7 IMPULSE DI Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register.
8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface
mode is selected and some bits of the DATA bus are used as a serial port.
9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
11, 12 D[2:3]or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these
inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the
data output. In other serial modes, these pins are not used.
13 D4 or DI/O When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected
on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock
signal connected to the SCLK input.
14 D5 or DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.
INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC
is active LOW.
15 D6 or DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave modes.

Rev. 0 | Page 8 of 28
 AD7667
Pin No. Mnemonic Type1 Description
16 D7 or DI/O When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus.
RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a
read mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA
with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is
output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only
when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21 D8 or DO When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus.
SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized
to SCLK. Conversion results are stored in an on-chip register. The AD7667 provides the conversion
result, MSB first, from its internal shift register. The DATA format is determined by the logic level of
OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode
when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the
next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next
rising edge.
22 D9 or DI/O When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.
SCLK When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated
depends upon the logic state of the INVSCLK pin.
23 D10 or DO When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus.
SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while the SDOUT output is valid.
24 D11 or DO When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When
RDERROR SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error
flag. In slave mode, when a data read is started and not complete when the following conversion is
complete, the current data is lost and RDERROR is pulsed HIGH.
25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
state of SER/PAR.
29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
30 DGND P Must Be Tied to Digital Ground.
31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7667 and the current conversion, if any, is
aborted. If not used, this pin could be tied to DGND.
34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge
on CNVST puts the internal sample/hold into the hold state and initiates a conversion. The mode is
most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t8) is
complete, the internal sample/hold is put into the hold state and a conversion is immediately started.
37 REF AI/O Reference Input Voltage. On-chip reference output voltage.
38 REFGND AI Reference Input Analog Ground.
39 INGND AI Analog Input Ground.
43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V.

Rev. 0 | Page 9 of 28
AD7667
Pin No. Mnemonic Type1 Description
45 TEMP AO Temperature Sensor Voltage Output.
46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input.
47 PDREF DI This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference
is turned on. When HIGH, the internal reference is switched off and an external reference must be
used.
48 PDBUF DI This pin allows the choice of buffering an internal or external reference with the internal buffer. When
LOW, the buffer is selected. When HIGH, the buffer is switched off.

1
AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.

Rev. 0 | Page 10 of 28
 AD7667

DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity Error (INL) Aperture Delay
Linearity error refers to the deviation of each individual code Aperture delay is a measure of the acquisition performance and
from a line drawn from negative full scale through positive full is measured from the falling edge of the CNVST input to when
scale. The point used as negative full scale occurs ½ LSB before the input signal is held for a conversion.
the first code transition. Positive full scale is defined as a level
Transient Response
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line. Transient response is the time required for the AD7667 to
achieve its rated accuracy after a full-scale step function is
Differential Nonlinearity Error (DNL) applied to its input.
In an ideal ADC, code transitions are 1 LSB apart. Differential
Reference Voltage Temperature Coefficient
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing Reference voltage temperature coefficient is derived from the
codes are guaranteed. maximum and minimum reference output voltage (VREF)
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C
Full-Scale Error using the following equation:
The last transition (from 011…10 to 011…11 in twos comple-
ment coding) should occur for an analog voltage 1½ LSB below VREF ( Max ) – VREF ( Min)
TCVREF (ppm/°C) = × 106
the nominal full scale (2.49994278 V for the 0 V to 2.5 V range). VREF (25°C) × (TMAX – TMIN )
The full-scale error is the deviation of the actual level of the last
where:
transition from the ideal level.
VREF(Max) = Maximum VREF at TMIN, T(25°C), or TMAX
Unipolar Zero Error VREF(Min) = Minimum VREF at TMIN, T(25°C), or TMAX
The first transition should occur at a level ½ LSB above analog VREF(25°C) = VREF at 25°C
ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero TMAX = +85°C
error is the deviation of the actual transition from that point. TMIN = –40°C
Spurious-Free Dynamic Range (SFDR) Thermal Hysteresis
SFDR is the difference, in decibels (dB), between the rms Thermal hysteresis is defined as the absolute maximum change
amplitude of the input signal and the peak spurious signal. of reference output voltage after the device is cycled through
temperature from either
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave T_HYS+ = 25°C to TMAX to 25°C
input. It is related to S/(N+D) and is expressed in bits by the T_HYS– = 25°C to TMIN to 25°C
following formula:
It is expressed in ppm using the following equation:
ENOB = (S/[N+D]dB – 1.76)/6.02
VREF (25°C ) − VREF (T _ HYS)
Total Harmonic Distortion (THD) VHYS ( ppm) = × 10 6
VREF (25°C )
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is where:
expressed in decibels. VREF(25°C) = VREF at 25°C
Signal-to-Noise Ratio (SNR) VREF(T_HYS) = Maximum change of VREF at T_HYS+ or
SNR is the ratio of the rms value of the actual input signal to the T_HYS–
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.

Rev. 0 | Page 11 of 28
AD7667

TYPICAL PERFORMANCE CHARACTERISTICS

2.0 1.5

1.5
1.0
1.0

0.5
0.5

DNL (LSB)
INL (LSB)

0
–0.5

–1.0
–0.5
–1.5

–2.0 –1.0

03035-0-005

03035-0-008
0 16384 32768 49152 65536 0 16384 32768 49152 65536

CODE CODE

Figure 5. Integral Nonlinearity vs. Code Figure 8. Differential Nonlinearity vs. Code

20 20

15 15
NUMBER OF UNITS
NUMBER OF UNITS

10 10

5 5

03035-0-009
0
03035-0-006

0 0.5 1.0 1.5 2.0 –2.0 –1.5 –1.0 –0.5 0

POSITIVE INL (LSB) NEGATIVE INL (LSB)

Figure 6. Typical Positive INL Distribution (102 Units) Figure 9. Typical Negative INL Distribution (102 Units)

30 60

50
NUMBER OF UNITS

40
NUMBER OF UNITS

20

30

10 20

10

0 0
03035-0-010
03035-0-007

0 0.25 0.50 0.75 1.00 1.25 1.50 –1.00 –0.75 –0.50 –0.25 0

POSITIVE DNL (LSB) NEGATIVE DNL (LSB)

Figure 7. Typical Positive DNL Distribution (102 Units) Figure 10. Typical Negative DNL Distribution (102 Units)

Rev. 0 | Page 12 of 28
 AD7667
140000 180000

116794 160000
120000 113049 146923
140000
100000
120000
COUNTS

80000

COUNTS
100000

60000 80000

56646
60000
51940
40000
40000
14654 15970
20000
20000
1 344 308 0 0 35 2602 2958 16 0
0 0

03035-0-011

03035-0-014
7FFE 7FFF 8000 8001 8002 8003 8004 8005 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006

CODE IN HEX CODE IN HEX

Figure 11. Histogram of 261,120 Conversions of a Figure 14. Histogram of 261,120 Conversions of a
DC Input at the Code Transition DC Input at the Code Center

0 –70 120

–20 fS = 1MSPS –75 110

SFDR
fIN = 101.11kHz
–80 100
–40 SNR = 88.9dB
AMPLITUDE (dB of Full Scale)

THD = –94.2dB THD, HARMONICS (dB)

–85 90
–60 SFDR = 94.7dB
S/[N+D] = 88dB –90 80

SFDR (dB)
–80 SECOND
HARMONIC
–95 70
–100
–100 60
–120 THD
–105 50
–140 –110 40
THIRD
–160 –115 HARMONIC 30

–180 –120 20

03035-0-015
03035-0-012

0 100 200 300 400 500 1 10 100 1000

FREQUENCY (kHz) FREQUENCY (kHz)

Figure 12. FFT Plot Figure 15. THD, Harmonics, and SFDR vs. Frequency

91 15.5 91
SNR, S/[N+D] REFERRED TO FULL-SCALE (dB)

90

89 15.0

88
SNR, S/[N+D] (dB)

SNR 90
ENOB (Bits)

87 14.5
SNR
86
S/[N+D] S/[N+D]
85 14.0
89
84
ENOB
83 13.5

82

81 13.0 88
03035-0-013

03035-0-016

1 10 100 1000 –60 –50 –40 –30 –20 –10 0

FREQUENCY (kHz)
INPUT LEVEL (dB)

Figure 13. SNR, S/(N+D), and ENOB vs. Frequency Figure 16. SNR and S/[N+D] vs. Input Level (Referred to Full Scale)

Rev. 0 | Page 13 of 28
AD7667
92 15.0 6
5

ZERO ERROR, FULL-SCALE ERROR (LSB)

ENOB
4
91 14.5
3 FULL-SCALE
2 ERROR
SNR, S/[N+D] (dB)

SNR

ENOB (Bits)
90 14.0 1
0
S/[N+D]
–1
89 13.5
–2 ZERO ERROR
–3
88 13.0 –4
–5

87 12.5 –6

03035-0-020
03035-0-017
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 17. SNR, S/[N+D], and ENOB vs. Temperature Figure 20. Zero Error, Full-Scale Error with Reference vs. Temperature

–100 2.4988

2.4986

THD 2.4984

2.4982
THD, HARMONICS (dB)

–105
2.4980
SECOND
VREF (V)

HARMONIC 2.4978

2.4976

2.4974
–110
THIRD 2.4972
HARMONIC
2.4970

2.4968

–115 2.4966

03035-0-021
03035-0-018

–55 –35 –15 5 25 45 65 85 105 125 –40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 18. THD and Harmonics vs. Temperature Figure 21. Typical Reference Voltage Output vs. Temperature (3 Units)

100000 25
AVDD, WARP/NORMAL
10000
DVDD, WARP/NORMAL 20
OPERATING CURRENTS (µA)

1000
NUMBER OF UNITS

100 15
AVDD, IMPULSE
10
DVDD, IMPULSE 10
OVDD, ALL MODES
1

0.1
5

0.01

PDREF = PDBUF = HIGH 0

0.001
03035-0-022
03035-0-019

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
10 100 1k 10k 100k 1M

SAMPLING RATE (SPS) REFERENCE DRIFT (ppm/°C)

Figure 19. Operating Current vs. Sample Rate Figure 22. Reference Voltage Temperature Coefficient Distribution (102 Units)

Rev. 0 | Page 14 of 28
 AD7667
50
OVDD = 2.7V @ 85°C
45
OVDD = 2.7V @ 25°C
40

35
t12 DELAY (ns)

30

25 OVDD = 5V @ 85°C

20
OVDD = 5V @ 25°C
15

10

03035-0-023
0 50 100 150 200

CL (pF)

Figure 23. Typical Delay vs. Load Capacitance CL

Rev. 0 | Page 15 of 28
AD7667

CIRCUIT INFORMATION
IN
REF
REFGND
SWITCHES
CONTROL
MSB LSB SWA
32,768C 16,384C 4C 2C C C
BUSY
CONTROL
COMP LOGIC
INGND OUTPUT
65,536C CODE

03033-0-020
SWB

CNVST

Figure 24. ADC Simplified Schematic

The AD7667 is a very fast, low power, single supply, precise from the inputs and connected to REFGND. Therefore, the
16-bit analog-to-digital converter (ADC). The AD7667 features differential voltage between IN and INGND captured at the end
different modes to optimize performance according to the of the acquisition phase is applied to the comparator inputs,
applications. In Warp mode, the part can convert 1 million causing the comparator to become unbalanced. By switching
samples per second (1 MSPS). each element of the capacitor array between REFGND and REF,
the comparator input varies by binary weighted voltage steps
The AD7667 provides the user with an on-chip track/hold, (VREF/2, VREF/4, …VREF/65536). The control logic toggles these
successive approximation ADC that does not exhibit any switches, starting with the MSB, to bring the comparator back
pipeline or latency, making it ideal for multiple multiplexed into a balanced condition.
channel applications.
After this process is completed, the control logic generates the
The AD7667 can be operated from a single 5 V supply and can ADC output code and brings the BUSY output LOW.
be interfaced to either 5 V or 3 V digital logic. It is housed in
either a 48-lead LQFP or a 48-lead LFCSP that saves space and Modes Of Operation
allows flexible configurations as either a serial or parallel inter- The AD7667 features three modes of operation: Warp, Normal,
face. The AD7667 is pin-to-pin compatible with PulSAR ADCs and Impulse. Each mode is best suited for specific applications.
and is an upgrade of the AD7666 and AD7661.
Warp mode allows the fastest conversion rate, up to 1 MSPS.
CONVERTER OPERATION However in this mode and this mode only, the full specified
The AD7667 is a successive-approximation ADC based on a accuracy is guaranteed only when the time between conversions
charge redistribution DAC. Figure 24 shows a simplified sche- does not exceed 1 ms. If the time between two consecutive
matic of the ADC. The capacitive DAC consists of an array of conversions is longer than 1 ms (e.g., after power-up), the first
16 binary weighted capacitors and an additional LSB capacitor. conversion result should be ignored. This mode makes the
The comparator’s negative input is connected to a dummy AD7667 ideal for applications where both high accuracy and
capacitor of the same value as the capacitive DAC array. fast sample rate are required.

During the acquisition phase, the common terminal of the array Normal mode is the fastest mode (800 kSPS) without any
tied to the comparator’s positive input is connected to AGND limitations on the time between conversions. This mode makes
via SWA. All independent switches are connected to the analog the AD7667 ideal for asynchronous applications such as data
input IN. Thus, the capacitor array is used as a sampling acquisition systems, where both high accuracy and fast sample
capacitor and acquires the analog signal on IN. Similarly, the rate are required.
dummy capacitor acquires the analog signal on INGND. Impulse mode, the lowest power dissipation mode, allows power
When CNVST goes LOW, a conversion phase is initiated. When saving between conversions. When operating at 1 kSPS, for
example, it typically consumes only 130 µW. This feature makes
the conversion phase begins, SWA and SWB are opened. The
the AD7667 ideal for battery-powered applications.
capacitor array and dummy capacitor are then disconnected

Rev. 0 | Page 16 of 28
 AD7667
Transfer Functions Table 7. Output Codes and Ideal Input Voltages
Using the OB/2C digital input, the AD7667 offers two output Digital Output Code (Hex)
codings: straight binary and twos complement. The LSB size is Analog Straight Twos
VREF/65536, which is about 38.15 µV. The AD7667’s ideal Description Input Binary Complement
transfer characteristic is shown in Figure 25 and Table 7. FSR –1 LSB 2.499962 V FFFF1 7FFF1
FSR – 2 LSB 2.499923 V FFFE 7FFE
Midscale + 1 LSB 1.250038 V 8001 0001
1 LSB = V REF /65536
Midscale 1.25 V 8000 0000
111...111 Midscale – 1 LSB 1.249962 V 7FFF FFFF
ADC CODE (Straight Binary)

111...110
–FSR + 1 LSB 38 µV 0001 8001
111...101
–FSR 0V 00002 80002

1
This is also the code for overrange analog input (VIN – VINGND above
VREF – VREFGND).
2
This is also the code for underrange analog input (VIN below VINGND).
000...010
000...001
000...000
0V 1 LSB VREF – 1 LSB
03033-0-021

0.5 LSB
VREF – 1.5 LSB
ANALOG INPUT

Figure 25. ADC Ideal Transfer Function

ANALOG 20Ω
SUPPLY DIGITAL SUPPLY
(5V) (3.3V OR 5V)
+ + +
10µF 100nF 10µF 100nF 100nF 10µF

AVDD GND DGND DVDD OVDD OGND SERIAL

PORT
SCLK
REF
SDOUT
CR4 REFBUFIN1
100nF
REFGND µC/µP/DSP
BUSY

AD7667 CNVST D3
15Ω
U12 IN
ANALOG INPUT OB/2C
(0V TO 2.5V) SER/PAR DVDD
CC 2.7nF
WARP
BYTESWAP
INGND
IMPULSE

PDREF PD PDBUF RESET CS RD

CLOCK

NOTES
1THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER.
2THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3OPTIONAL LOW JITTER.
4A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M).
SEE VOLTAGE REFERENCE INPUT SECTION.
03035-0-026

Figure 26. Typical Connection Diagram

Rev. 0 | Page 17 of 28
AD7667
TYPICAL CONNECTION DIAGRAM
Figure 26 shows a typical connection diagram for the AD7667. During the acquisition phase, the impedance of the analog
Analog Input input IN can be modeled as a parallel combination of capacitor
C1 and the network formed by the series connection of R1 and
Figure 27 shows an equivalent circuit of the input structure of
C2. C1 is primarily the pin capacitance. R1 is typically 168 Ω
the AD7667.
and is a lumped component made up of some serial resistors
The two diodes, D1 and D2, provide ESD protection for the and the on resistance of the switches. C2 is typically 60 pF and
analog inputs IN and INGND. Care must be taken to ensure is mainly the ADC sampling capacitor. During the conversion
that the analog input signal never exceeds the supply rails by phase, where the switches are opened, the input impedance is
more than 0.3 V. This will cause these diodes to become limited to C1. R1 and C2 make a 1-pole low-pass filter that
forward-biased and start conducting current. These diodes can reduces undesirable aliasing effect and limits the noise.
handle a forward-biased current of 100 mA maximum. For
When the source impedance of the driving circuit is low, the
instance, these conditions could eventually occur when the
AD7667 can be driven directly. Large source impedances
input buffer’s (U1) supplies are different from AVDD. In such a
signifcantly affect the ac performance, especially total harmonic
case, an input buffer with a short-circuit current limitation can
distortion (THD). The maximum source impedance depends
be used to protect the part.
on the amount of THD that can be tolerated. The THD
AVDD degrades as a function of the source impedance and the
maximum input frequency, as shown in Figure 29.
D1 R1 C2
IN
OR INGND
C1 –50
D2
03033-0-023

AGND RS = 500Ω
–60

Figure 27. Equivalent Analog Input Circuit RS = 100Ω

–70
THD (dB)

This analog input structure allows the sampling of the differen- RS = 50Ω
–80
tial signal between IN and INGND. Unlike other converters, RS = 20Ω
INGND is sampled at the same time as IN. By using this –90
differential input, small signals common to both inputs are
rejected, as shown in Figure 28, which represents the typical –100
CMRR over frequency with on-chip and external references.
For instance, by using INGND to sense a remote signal ground, –110

03035-0-029
1 10 100 1000
ground potential differences between the sensor and the local
ADC ground are eliminated. INPUT FREQUENCY (kHz)

Figure 29. THD vs. Analog Input Frequency and Source Resistance
80

75
Driver Amplifier Choice
EXT REF Although the AD7667 is easy to drive, the driver amplifier
70
needs to meet the following requirements:
65

60 • The driver amplifier and the AD7667 analog input circuit

CMRR (dB)

REF
55 must be able to settle for a full-scale step of the capacitor
50 array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, settling at 0.1% to 0.01% is more commonly speci-
45
fied. This could differ significantly from the settling time at
40
a 16-bit level and should be verified prior to driver
35 selection. The tiny op amp AD8021, which combines ultra
30 low noise and high gain-bandwidth, meets this settling
03035-0-028

1 10 100 1000 10000

time requirement even when used with gains up to 13.
FREQUENCY (kHz)

Figure 28. Analog Input CMRR vs. Frequency

Rev. 0 | Page 18 of 28
 AD7667
• The noise generated by the driver amplifier needs to be Voltage Reference Input
kept as low as possible in order to preserve the SNR and The AD7667 allows the choice of either a very low temperature
transition noise performance of the AD7667. The noise drift internal voltage reference or an external 2.5 V reference.
coming from the driver is filtered by the AD7667 analog
input circuit 1-pole low-pass filter made by R1 and C2 or Unlike many ADCs with internal references, the internal
by the external filter, if one is used. The SNR degradation reference of the AD7667 provides excellent performance and
due to the amplifier is can be used in almost all applications.

⎛ ⎞ To use the internal reference along with the internal buffer,

⎜ ⎟ PDREF and PDBUF should both be LOW. This produces 1.2 V
= 20 log ⎜ ⎟
28
SNR LOSS on REFBUFIN which, amplified by the buffer, results in a 2.5 V
⎜ π ⎟
⎜ 784 + f −3dB (Ne N )2 ⎟ reference on the REF pin.
⎝ 2 ⎠
The output impedance of REFBUFIN is 11 kΩ (minimum)
where: when the internal reference is enabled. It is necessary to
f–3dB is the input bandwidth of the AD7667 (13 MHz) or decouple REFBUFIN with a ceramic capacitor greater than
the cutoff frequency of the input filter (3.9 MHz), if 10 nF. Thus the capacitor provides an RC filter for noise
one is used. reduction.
N is the noise factor of the amplifier (+1 in buffer To use an external reference along with the internal buffer,
configuration). PDREF should be HIGH and PDBUF should be LOW. This
powers down the internal reference and allows the 2.5 V
eN is the equivalent input noise voltage of the op amp, in
reference to be applied to REFBUFIN.
nV/√Hz.
To use an external reference directly on REF pin, PDREF and
For instance, a driver with an equivalent input noise of
PDBUF should both be HIGH.
2 nV/√Hz, like the AD8021 with a noise gain of +1 when
configured as a buffer, degrades the SNR by only 0.13 dB PDREF and PDBUF power down the internal reference and the
when using the filter in Figure 26 and by 0.43 dB without. internal reference buffer, respectively. Note that the PDREF and
PDBUF input current should never exceed 20 mA. This could
• The driver needs to have a THD performance suitable to
eventually occur when input voltage is above AVDD (for
that of the AD7667. Figure 15 gives the THD versus
instance, at power-up). In this case, a 100 Ω series resistor is
frequency that the driver should exceed.
recommended.
The AD8021 meets these requirements and is appropriate for
The internal reference is temperature compensated to 2.5 V
almost all applications. The AD8021 needs a 10 pF external
±7 mV. The reference is trimmed to provide a typical drift of
compensation capacitor that should have good linearity as an
3 ppm/°C . This typical drift characteristic is shown in
NPO ceramic or mica type. Moreover, the use of a noninverting
Figure 22. For improved drift performance, an external
+1 gain arrangement is recommended and helps to obtain the
reference, such as the AD780, can be used.
best signal-to-noise ratio.
The AD7667 voltage reference input REF has a dynamic input
The AD8022 could also be used if a dual version is needed and
impedance; it should therefore be driven by a low impedance
gain of 1 is present. The AD829 is an alternative in applications
source with efficient decoupling between the REF and
where high frequency (above 100 kHz) performance is not
REFGND inputs. This decoupling depends on the choice of the
required. In gain of 1 applications, it requires an 82 pF
voltage reference but usually consists of a low ESR tantalum
compensation capacitor. The AD8610 is an option when low
capacitor connected to REF and REFGND with minimum
bias current is needed in low frequency applications.
parasitic inductance. A 10 µF (X5R, 1206 size) ceramic chip
capacitor (or 47 µF tantalum capacitor) is appropriate when
using either the internal reference or one of these
recommended reference voltages:

• The low noise, low temperature drift ADR421 and AD780

• The low power ADR291

• The low cost AD1582

Rev. 0 | Page 19 of 28
AD7667
For applications that use multiple AD7667s, it is more effective 80

to use the internal buffer to buffer the reference voltage. 75 EXT REF

70
Care should be taken with the voltage reference’s temperature
65
coefficient, which directly affects the full-scale accuracy if this
parameter matters. For instance, a ±15 ppm/°C temperature 60

PSRR (dB)
INT REF
coefficient of the reference changes full scale by ±1 LSB/°C. 55

50
Note that VREF can be increased to AVDD – 1.85 V. Since the
input range is defined in terms of VREF, this would essentially 45

increase the range to 0 V to 3 V with an AVDD above 4.85 V. 40

The AD780 can be selected with a 3 V reference voltage. 35

30
The TEMP pin, which measures the temperature of the

03035-0-031
1 10 100 1000 10000
AD7667, can be used as shown in Figure 30. The output of FREQUENCY (kHz)
TEMP pin is applied to one of the inputs of the analog switch
Figure 31. PSRR vs. Frequency
(e.g., ADG779), and the ADC itself is used to measure its own
temperature. This configuration is very useful for improving the
calibration accuracy over the temperature range. POWER DISSIPATION VERSUS THROUGHPUT
When using the Impulse mode of operation (IMPULSE =
TEMP HIGH, WARP = LOW), operating currents are very low during
ADG779
the acquisition phase, allowing significant power savings when
TEMPERATURE
IN SENSOR
the conversion rate is reduced (see Figure 32). The AD7667
ANALOG INPUT
(UNIPOLAR) automatically reduces its power consumption at the end of each
03035-0-024

CC AD7667
AD8021 conversion phase. This makes the part ideal for very low power
battery applications. The digital interface and the reference
Figure 30. Temperature Sensor Connection Diagram remain active even during the acquisition phase. To reduce
operating digital supply currents even further, digital inputs
Power Supply need to be driven close to the power supply rails (i.e., DVDD or
The AD7667 uses three power supply pins: an analog 5 V supply DGND), and OVDD should not exceed DVDD by more than
AVDD, a digital 5 V core supply DVDD, and a digital input/ 0.3 V.
output interface supply OVDD. OVDD allows direct interface
with any logic between 2.7 V and DVDD + 0.3 V. To reduce the 1M
supplies needed, the digital core (DVDD) can be supplied
through a simple RC filter from the analog supply, as shown in
100k WARP MODE POWER
Figure 26. The AD7667 is independent of power supply
POWER DISSIPATION (µW)

sequencing once OVDD does not exceed DVDD by more than

0.3 V, and is thus free of supply voltage induced latch-up. 10k

Additionally, it is very insensitive to power supply variations

over a wide frequency range, as shown in Figure 31, which 1k
IMPULSE MODE POWER

represents PSRR over frequency with on chip and external

references.
100

PDREF = PDBUF = HIGH

10
03035-0-032

10 100 1k 10k 100k 1M

SAMPLING RATE (SPS)

Figure 32. Power Dissipation vs. Sampling Rate

Rev. 0 | Page 20 of 28
 AD7667
CONVERSION CONTROL t2
t1
Figure 33 shows the detailed timing diagrams of the conversion
CNVST
process. The AD7667 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
BUSY
is complete. CNVST operates independently of CS and RD. t4
t3
t6
In Impulse mode, conversions can be automatically initiated. If t5
CNVST is held LOW when BUSY is LOW, the AD7667 controls

03033-0-026
MODE ACQUIRE CONVERT ACQUIRE CONVERT
the acquisition phase and automatically initiates a new con- t7 t8
version. By keeping CNVST LOW, the AD7667 keeps the
conversion process running by itself. It should be noted that the Figure 33. Basic Conversion Timing
analog input must be settled when BUSY goes LOW. Also, at
power-up, CNVST should be brought LOW once to initiate the t9
RESET
conversion process. In this mode, the AD7667 can run slightly
faster than the guaranteed 666 kSPS limits in Impulse mode.
This feature does not exist in Warp and Normal modes. BUSY

Although CNVST is a digital signal, it should be designed with

DATA
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing. t8

03033-0-027
CNVST
The CNVST trace should be shielded with ground and a low
value serial resistor (e.g., 50 Ω) termination should be added
Figure 34. RESET Timing
close to the output of the component that drives this line.
CS = RD = 0
For applications where SNR is critical, the CNVST signal should
t1
have very low jitter. This can be achieved by using a dedicated
CNVST
oscillator for CNVST generation, or by clocking CNVST with a
high frequency, low jitter clock, as shown in Figure 26. t10
BUSY
t4
t3
t11

03033-0-028
DATA
PREVIOUS CONVERSION DATA NEW DATA
BUS

Figure 35. Master Parallel Data Timing for Reading (Continuous Read)

Rev. 0 | Page 21 of 28
AD7667
DIGITAL INTERFACE CS

The AD7667 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or a parallel
interface. The serial interface is multiplexed on the parallel data RD

bus. The AD7667 digital interface also accommodates both 3 V

and 5 V logic by simply connecting the OVDD supply pin of the
AD7667 to the host system interface digital supply. Finally, by BUSY
using the OB/2C input pin, both twos complement or straight
binary coding can be used.
DATA CURRENT
The two signals, CS and RD, control the interface. CS and RD BUS

03033-0-029
CONVERSION

have a similar effect because they are OR’d together internally. t12 t13

When at least one of these signals is HIGH, the interface

Figure 36. Slave Parallel Data Timing for Reading (Read after Convert)
outputs are in high impedance. Usually CS allows the selection
of each AD7667 in multicircuit applications and is held low in a
CS = 0
single AD7667 design. RD is generally used to enable the
CNVST, t1
conversion result on the data bus. RD

PARALLEL INTERFACE
The AD7667 is configured to use the parallel interface when
BUSY
SER/PAR is held LOW. The data can be read either after each t4

conversion, which is during the next acquisition phase, or t3

during the following conversion, as shown in Figure 36 and
Figure 37, respectively. When the data is read during the DATA PREVIOUS

03033-0-030
BUS CONVERSION
conversion, however, it is recommended that it is read only
t12 t13
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital Figure 37. Slave Parallel Data Timing for Reading (Read during Convert)
interface and the most critical analog conversion circuitry.

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in Figure 38, the LSB byte is output on D[7:0] and the CS

MSB is output on D[15:8] when BYTESWAP is LOW. When

BYTESWAP is HIGH, the LSB and MSB bytes are swapped and RD

the LSB is output on D[15:8] and the MSB is output on D[7:0].

By connecting BYTESWAP to an address line, the 16-bit data BYTESWAP
can be read in two bytes on either D[15:8] or D[7:0].
HI-Z HI-Z
PINS D[15:8] HIGH BYTE LOW BYTE
SERIAL INTERFACE
t12 t12 t13
The AD7667 is configured to use the serial interface when HI-Z HI-Z 03033-0-031
PINS D[7:0] LOW BYTE HIGH BYTE
SER/PAR is held HIGH. The AD7667 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with Figure 38. 8-Bit Parallel Interface
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.

Rev. 0 | Page 22 of 28
 AD7667
MASTER SERIAL INTERFACE Usually, because the AD7667 is used with a fast throughput, the
Internal Clock Master Read During Conversion mode is the most recommen-
The AD7667 is configured to generate and provide the serial ded serial mode. In this mode, the serial clock and data toggle at
data clock SCLK when the EXT/INT pin is held LOW. The appropriate instants, minimizing potential feedthrough between
AD7667 also generates a SYNC signal to indicate to the host digital activity and critical conversion decisions.
when the serial data is valid. The serial clock SCLK and the In Read After Conversion mode, it should be noted that unlike
SYNC signal can be inverted if desired. Depending on the in other modes, the BUSY signal returns LOW after the 16 data
RDC/SDIN input, the data can be read after each conversion or bits are pulsed out and not at the end of the conversion phase,
during the following conversion. Figure 39 and Figure 40 show which results in a longer BUSY width.
detailed timing diagrams of these two modes.

EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0

CS, RD
t3

CNVST

BUSY t28
t30
t29
t25
SYNC
t 14 t18
t19
t 20 t21 t 24
t26
SCLK 1 2 3 14 15 16

t 15
t27
SDOUT X D15 D14 D2 D1 D0

03033-0-032
t 16 t23
t 22

Figure 39. Master Serial Data Timing for Reading (Read after Convert)

EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0

CS, RD

t1
CNVST

t3

BUSY

t17
t25
SYNC

t14 t 19
t 20 t 21
t24
t26
t15
SCLK 1 2 3 14 15 16
t18
t27

SDOUT X D15 D14 D2 D1 D0

03033-0-033

t16 t23
t22

Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

Rev. 0 | Page 23 of 28
AD7667
SLAVE SERIAL INTERFACE
External Clock
The AD7667 is configured to accept an externally supplied While the AD7667 is performing a bit decision, it is important
serial data clock on the SCLK pin when the EXT/INT pin is that voltage transients be avoided on digital input/output pins
held HIGH. In this mode, several methods can be used to read or degradation of the conversion result could occur. This is
the data. The external serial clock is gated by CS. When CS and particularly important during the second half of the conversion
RD are both LOW, the data can be read after each conversion or phase because the AD7667 provides error correction circuitry
during the following conversion. The external clock can be that can correct for an improper bit decision made during the
either a continuous or a discontinuous clock. A discontinuous first half of the conversion phase. For this reason, it is
clock can be either normally HIGH or normally LOW when recommended that when an external clock is being provided, it
inactive. Figure 41 and Figure 42 show the detailed timing is a discontinuous clock that is toggling only when BUSY is
diagrams of these methods. Usually, because the AD7667 has a LOW, or, more importantly, that it does not transition during
longer acquisition phase than conversion phase, the data are the latter half of BUSY HIGH.
read immediately after conversion.

EXT/INT = 1 INVSCLK = 0 RD = 0
RD

BUSY
t 35
t 36 t37

SCLK 1 2 3 14 15 16 17 18

t31 t32

SDOUT X D15 D14 D13 D1 D0 X15 X14

t16 t 34

03033-0-034
SDIN X15 X14 X13 X1 X0 Y15 Y14

t33

Figure 41. Slave Serial Data Timing for Reading (Read after Convert)

EXT/INT = 1 INVSCLK = 0 RD = 0
CS

CNVST

BUSY

t3 t35
t36 t37

SCLK 1 2 3 14 15 16

t31
t32
03033-0-035

SDOUT X D15 D14 D13 D1 D0

t 16

Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

Rev. 0 | Page 24 of 28
 AD7667
External Discontinuous Clock Data Read After External Clock Data Read During Conversion
Conversion Figure 42 shows the detailed timing diagrams of this method.
Though the maximum throughput cannot be achieved using During a conversion, while both CS and RD are LOW, the result
this mode, it is the most recommended of the serial slave of the previous conversion can be read. The data is shifted out
modes. Figure 41 shows the detailed timing diagrams of this MSB first with 16 clock pulses, and is valid on both the rising
method. After a conversion is complete, indicated by BUSY and falling edges of the clock. The 16 bits must be read before
returning LOW, the conversion result can be read while both CS the current conversion is complete; otherwise, RDERROR is
and RD are LOW. Data is shifted out MSB first with 16 clock pulsed HIGH and can be used to interrupt the host interface to
pulses and is valid on the rising and falling edges of the clock. prevent incomplete data reading. There is no daisy-chain feature
in this mode and the RDC/SDIN input should always be tied
Among the advantages of this method is the fact that conver- either HIGH or LOW.
sion performance is not degraded because there are no voltage
transients on the digital interface during the conversion process. To reduce performance degradation due to digital activity, a fast
Another advantage is the ability to read the data at any speed up discontinuous clock (at least 18 MHz when Impulse mode is
to 40 MHz, which accommodates both the slow digital host used, 25 MHz when Normal mode is used, or 40 MHz when
interface and the fastest serial reading. Warp mode is used) is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is also
Finally, in this mode only, the AD7667 provides a daisy-chain possible to begin to read data after conversion and continue to
feature using the RDC/SDIN pin for cascading multiple con- read the last bits after a new conversion has been initiated. This
verters together. This feature is useful for reducing component allows the use of a slower clock speed like 14 MHz in Impulse
count and wiring connections when desired, as, for instance, in mode, 18 MHz in Normal mode, and 25 MHz in Warp mode.
isolated multiconverter applications.

An example of the concatenation of two devices is shown in

Figure 43. Simultaneous sampling is possible by using a
common CNVST signal. It should be noted that the RDC/SDIN
input is latched on the opposite edge of SCLK of the one used to
shift out the data on SDOUT. Therefore, the MSB of the
“upstream” converter just follows the LSB of the “downstream”
converter on the next SCLK cycle.

BUSY
OUT

BUSY BUSY

AD7667 AD7667
#2 #1
(UPSTREAM) (DOWNSTREAM)

RDC/SDIN SDOUT DATA

RDC/SDIN SDOUT
OUT

CNVST CNVST

CS CS

SCLK SCLK
03035-0-036

SCLK IN
CS IN
CNVST IN

Figure 43. Two AD7667s in a Daisy-Chain Configuration

Rev. 0 | Page 25 of 28
AD7667
MICROPROCESSOR INTERFACING going LOW) using an interrupt line of the DSP. The serial inter-
The AD7667 is ideally suited for traditional dc measurement face (SPI) on the ADSP-219x is configured for master mode—
applications supporting a microprocessor, and for ac signal (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit
processing applications interfacing to a digital signal processor. (CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by
The AD7667 is designed to interface either with a parallel 8-bit writing to the SPI control register (SPICLTx). To meet all timing
or 16-bit wide interface, or with a general-purpose serial port or requirements, the SPI clock should be limited to 17 Mbps,
I/O ports on a microcontroller. A variety of external buffers can which allows it to read an ADC result in less than 1 µs. When a
be used with the AD7667 to prevent digital noise from coupling higher sampling rate is desired, use of one of the parallel
into the ADC. The following section discusses the use of an interface modes is recommended.
AD7667 with an ADSP-219x SPI equipped DSP.
DVDD
SPI Interface (ADSP-219x)
AD7667* ADSP-219x*
Figure 44 shows an interface diagram between the AD7667 and
SER/PAR
the SPI equipped ADSP-219x. To accommodate the slower EXT/INT
speed of the DSP, the AD7667 acts as a slave device and data BUSY PFx
must be read after conversion. This mode also allows the daisy- CS SPIxSEL (PFx)
chain feature. The convert command can be initiated in RD SDOUT MISOx
INVSCLK SCLK SCKx
response to an internal timer interrupt. The reading process can
CNVST PFx or TFSx

03035-0-037
be initiated in response to the end-of-conversion signal (BUSY
* ADDITIONAL PINS OMITTED FOR CLARITY

Figure 44. Interfacing the AD7667 to an SPI Interface

Rev. 0 | Page 26 of 28
 AD7667

APPLICATION HINTS
BIPOLAR AND WIDER INPUT RANGES Running digital lines under the device should be avoided since
In some applications, it is desirable to use a bipolar or wider these couple noise onto the die. The analog ground plane
analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although should be allowed to run under the AD7667 to avoid noise
the AD7667 has only one unipolar range, simple modifications coupling. Fast switching signals like CNVST or clocks should be
of input driver circuitry allow bipolar and wider input ranges to shielded with digital ground to avoid radiating noise to other
be used without any performance degradation. Figure 45 shows sections of the board, and should never run near analog signal
a connection diagram that allows this. Component values paths. Crossover of digital and analog signals should be avoided.
required and resulting full-scale ranges are shown in Table 8. Traces on different but close layers of the board should run at
right angles to each other. This will reduce the effect of crosstalk
When desired, accurate gain and offset can be calibrated by through the board.
acquiring a ground and voltage reference using an analog
multiplexer (U2), as shown in Figure 45. The power supply lines to the AD7667 should use as large a
trace as possible to provide low impedance paths and reduce the
CF effect of glitches on the power supply lines. Good decoupling is
also important to lower the supply’s impedance presented to the
R1 AD7667 and to reduce the magnitude of the supply spikes.
Decoupling ceramic capacitors, typically 100 nF, should be
ANALOG R2
INPUT 15Ω placed on each power supply pin—AVDD, DVDD, and
U1 IN
OVDD—close to, and ideally right up against these pins and
2.7nF
their corresponding ground pins. Additionally, low ESR 10 µF
AD7667
U2 100nF
capacitors should be located near the ADC to further reduce
R3 R4
low frequency ripple.
INGND

REF The DVDD supply of the AD7667 can be a separate supply or

CREF can come from the analog supply AVDD or the digital interface
supply OVDD. When the system digital supply is noisy or when
03035-0-038

REFGND
fast switching digital signals are present, if no separate supply is
available, the user should connect DVDD to AVDD through an
Figure 45. Using the AD7667 in 16-Bit Bipolar and/or Wider Input Ranges
RC filter (see Figure 26) and the system supply to OVDD and
Table 8. Component Values and Input Ranges the remaining digital circuitry. When DVDD is powered from
the system supply, it is useful to insert a bead to further reduce
Input Range R1 (Ω) R2 (kΩ) R3 (kΩ) R4 (kΩ)
high frequency spikes.
±10 V 500 4 2.5 2
±5 V 500 2 2.5 1.67 The AD7667 has five different ground pins: INGND, REFGND,
0 V to –5 V 500 1 None 0 AGND, DGND, and OGND. INGND is used to sense the analog
input signal. REFGND senses the reference voltage and, because
LAYOUT it carries pulsed currents, should be a low impedance return to
The AD7667 has very good immunity to noise on the power the reference. AGND is the ground to which most internal ADC
supplies. However, care should still be taken with regard to analog signals are referenced; it must be connected with the
grounding layout. least resistance to the analog ground plane. DGND must be tied
to the analog or digital ground plane depending on the config-
The printed circuit board that houses the AD7667 should be uration. OGND is connected to the digital system ground.
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of EVALUATING THE AD7667’S PERFORMANCE
ground planes that can be separated easily. Digital and analog A recommended layout for the AD7667 is outlined in the
ground planes should be joined in only one place, preferably EVAL-AD7667 evaluation board for the AD7667. The
underneath the AD7667, or as close as possible to the AD7667. evaluation board package includes a fully assembled and tested
If the AD7667 is in a system where multiple devices require evaluation board, documentation, and software for controlling
analog-to-digital ground connections, the connection should the board from a PC via the EVAL-CONTROL BRD2.
still be made at one point only, a star ground point that should
be established as close as possible to the AD7667.

Rev. 0 | Page 27 of 28
AD7667

OUTLINE DIMENSIONS
0.75 1.60 9.00 BSC
0.60 MAX SQ
0.45
48 37
1 36

SEATING PIN 1
PLANE
10° TOP VIEW 7.00
1.45 6° (PINS DOWN) BSC SQ
1.40 2° 0.20
1.35 0.09 VIEW A
7°
3.5 ° 12 25
0° 13 24
0.15
0.05 SEATING 0.08 MAX 0.50 0.27
PLANE COPLANARITY BSC 0.22
VIEW A 0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC

Figure 46. 48-Lead Quad Flatpack (LQFP) [ST-48]

Dimensions shown in millimeters

0.30
7.00 0.60 MAX 0.23
BSC SQ 0.18
0.60 MAX PIN 1
INDICATOR
37 48
PIN 1 36 1
INDICATOR

TOP 6.75 BOTTOM 5.25

VIEW BSC SQ VIEW 5.10 SQ
4.95

0.50
0.40 25 12
0.30 24 13
0.25 MIN
5.50
REF
0.80 MAX
1.00
MAX
12° 0.65 TYP
PADDLE CONNECTED TO AGND.
0.85 THIS CONNECTION IS NOT
0.80 0.05 MAX REQUIRED TO MEET THE
0.02 NOM ELECTRICAL PERFORMANCES

0.50 BSC COPLANARITY

0.20 REF 0.08
SEATING
PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Figure 47. 48-Lead Frame Chip Scale Package (LFCSP) [CP-48]

Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7667AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7667ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7667ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
AD7667ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
EVAL-AD7667CB1 Evaluation Board
EVAL-CONTROL BRD22 Controller Board

1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D03035–0–1/04(0)

Rev. 0 | Page 28 of 28