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Experiment No.: 10

This document describes the design of a 4-bit left barrel shifter using VHDL. It includes the circuit diagram and truth table, VHDL code for a 4-1 multiplexer and the barrel shifter, a test bench, and simulation results. The objective is to design and test the barrel shifter circuit. VHDL code is written for the multiplexer and barrel shifter, which is then simulated using a test bench and Xilinx tools to verify the design works as intended.

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samrudhi
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39 views5 pages

Experiment No.: 10

This document describes the design of a 4-bit left barrel shifter using VHDL. It includes the circuit diagram and truth table, VHDL code for a 4-1 multiplexer and the barrel shifter, a test bench, and simulation results. The objective is to design and test the barrel shifter circuit. VHDL code is written for the multiplexer and barrel shifter, which is then simulated using a test bench and Xilinx tools to verify the design works as intended.

Uploaded by

samrudhi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ADVANCED DIGITAL SYSTEM DESIGN

EXPERIMENT NO. : 10

Design 4-bit Left Barrel Shifter using VHDL and Verify them by using
AIM: XILINX Simulator.

The Objective of this experiment is to design VHDL code for 4-bit left barrel
shifter in Xilinx 14.1 ISE Design suite tool, and to test the circuit using test
OBJECTIVE:
bench where outputs are observed for different inputs.

CIRCUIT
DIAGRAM &
TRUTH
TABLE:

Select Lines Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 I3 I2 I1 I0

0 1 I2 I1 I0 I3

1 0 I1 I0 I3 I0

1 1 I0 I3 I2 I1

VHDL CODE: A. VHDL Code for 4:1 MUX:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX_4 IS

Department of Electronics & Telecommunication Engineering, RGCER, Nagpur Page 1 of 5


ADVANCED DIGITAL SYSTEM DESIGN

PORT (A, B, C, D: IN STD_LOGIC;

S: IN STD_LOGIC_VECTOR (1 DOWNTO 0);

Z: OUT STD_LOGIC);

END MUX_4;

ARCHITECTURE Behavioral OF MUX_4 IS

BEGIN

PROCESS (S,A,B,C,D)

BEGIN

CASE S IS

WHEN "00"=> Z <= A;

WHEN "01"=> Z <= B;

WHEN "10"=> Z <= C;

WHEN "11"=> Z <= D;

WHEN OTHERS => NULL;

END CASE;

END PROCESS;

END behavioral;

B. VHDL Code for BARREL SHIFTER:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

ENTITY BARREL IS

PORT (I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

S: IN STD_LOGIC_VECTOR (1 DOWNTO 0);

Y: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));

Department of Electronics & Telecommunication Engineering, RGCER, Nagpur Page 2 of 5


ADVANCED DIGITAL SYSTEM DESIGN

END BARREL;

ARCHITECTURE Behavioral OF BARREL IS

COMPONENT MUX_4

PORT (A, B, C, D: IN STD_LOGIC;

S: IN STD_LOGIC_VECTOR (1 DOWNTO 0);

Z: OUT STD_LOGIC);

END COMPONENT;

BEGIN

u1: MUX_4 PORT MAP (A=>I(3), B=>I(2), C=>I(1), D=>I(0), S(1)=>S(1),


S(0)=>S(0), Z=>Y(3));

u2: MUX_4 PORT MAP (A=>I(2), B=>I(1), C=>I(0), D=>I(3), S(1)=>S(1),


S(0)=>S(0), Z=>Y(2));

u3: MUX_4 PORT MAP (A=>I(1), B=>I(0), C=>I(3), D=>I(2), S(1)=>S(1),


S(0)=>S(0), Z=>Y(1));

u4: MUX_4 PORT MAP (A=>I(0), B=>I(3), C=>I(2), D=>I(1), S(1)=>S(1),


S(0)=>S(0), Z=>Y(0));

END Behavioral;

Department of Electronics & Telecommunication Engineering, RGCER, Nagpur Page 3 of 5


ADVANCED DIGITAL SYSTEM DESIGN

TEST BENCH: library IEEE;


use IEEE.STD_LOGIC_1164.ALL;

ENTITY TEST IS

END TEST;

ARCHITECTURE behavior OF TEST IS

COMPONENT BARREL

PORT (I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

S: IN STD_LOGIC_VECTOR (1 DOWNTO 0);

Y: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));

END COMPONENT;

SIGNAL I: STD_LOGIC_VECTOR (3 DOWNTO 0):= (OTHERS => '0');

SIGNAL S: STD_LOGIC_VECTOR (1 DOWNTO 0):= (OTHERS => '0');

SIGNAL Y: STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

uut: BARREL PORT MAP (I => I, S => S, Y => Y);

stim_proc: PROCESS

BEGIN

I<="1001";

S<="00"; WAIT FOR 100 NS;

S<="01"; WAIT FOR 100 NS;

S<="10"; WAIT FOR 100 NS;

S<="11"; WAIT FOR 100 NS;

END PROCESS;

END;

Department of Electronics & Telecommunication Engineering, RGCER, Nagpur Page 4 of 5


ADVANCED DIGITAL SYSTEM DESIGN

SIMULATION
RESULTS:

RESULT/ Thus we have successfully design 4-bit left barrel shifter using XILINX tools
CONCLUSION: and verified the simulation result.

ROLL NO.: 17
NAME &
NAME: SAMRUDHI CHARDE MARKS SIGNATURE
OUT OF 15 OF
TEACHER Prof. Pradnya
SEM/ BRANCH: VII/ETC-A
Maturkar

Department of Electronics & Telecommunication Engineering, RGCER, Nagpur Page 5 of 5

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