MOSFET Small Signal Model and Analysis

•Just as we did with the BJT, we can consider the

MOSFET amplifier analysis in two parts:
•Find the DC operating point
•Then determine the amplifier output parameters for very
small input signals.

Georgia Tech ECE 3040 - Dr. Alan Doolittle

 MOSFET Small Signal Model and Analysis
Linearize
i1 over “small i1
i2 signal i2
+ Non-Linear I-V + range” + Linear +
V1 relationship
(BJT,
V2 V1 Two Port V2
- MOSFET, - -
Network -
etc…)

iDS

iGS
vDS
vGS

General “y-parameter” Network MOSFET “y-parameter” Network

I1=y11V1 + y12V2 IGS=y11VGS + y12VDS
I2=y21V1 + y22V2 IDS=y21VGS + y22VDS

Georgia Tech ECE 3040 - Dr. Alan Doolittle

 MOSFET Small Signal Model and Analysis

[ =[ [ [
IGS
IDS
y11
y21
[[
y12
y22
VGS
VDS y ij =
∂I j
∂Vi VGS ,Q , VDS ,Q
IGS=y11VGS + y12VDS
IDS=y21VGS + y22VDS Derivative of current-voltage equation
evaluated at the Quiescent Point

MOSFET Amplifiers are biased into Saturation (or Active Mode)

I DS =
Kn
2
[ ]
(VGS − VTN )2 (1 + λ V DS ) for V DS ≥ VGS − VTN

1.) Input Conductance

∂I GS ∂I GS
I GS = 0 ⇒ = 0 and =0 ⇒ y11 = 0 and y12 = 0
∂VGS ∂V DS
2.) Output Conductance
∂I DS λ Kn
= y 22 = (VGS − VT )2
∂VDS 2
3.) Transconductance
∂I DS
= y 21 = K n (VGS − VT )(1 + λ VDS )
∂VGS
Georgia Tech ECE 3040 - Dr. Alan Doolittle
 MOSFET Small Signal Model and Analysis
Compare with BJT Results

There is a large amount of symmetry between the MOSFET and the BJT

MOSFET BJT
λ Kn I DS Each of these IC
y 22 = go = ( )
VGS − VT =
2
parameters y 22 =
2 1 V A + VCE
+ V DS act in the
λ
same manner

I DS IC
y 21 = g m = K n (VGS − VT )(1 + λ VDS ) = y 21 =
 VGS − VTN  VT
 
 2 

Georgia Tech ECE 3040 - Dr. Alan Doolittle

 MOSFET Small Signal Model and Analysis
Putting the mathematical model into a small signal equivalent circuit

Compare this to the BJT small signal equivalent circuit

Georgia Tech ECE 3040 - Dr. Alan Doolittle

 MOSFET Small Signal Model and Analysis
Example: Jaeger 13.94

Calculate the voltage gain, Av=vo/vs

Given: Kn=1 mA/V2 , λ=0.015 V-1
Bias Point of: IDS=2 mA, VDS=7.5V

Georgia Tech ECE 3040 - Dr. Alan Doolittle

 MOSFET Small Signal Model and Analysis
Example: Jaeger 13.94

λ Kn
go = (VGS − VT )2 g m = K n (VGS − VT )(1 + λ VDS )
2

Need to find VGS-VT

I DS =
Kn
2
[ ]
(VGS − VTN )2 (1 + λ VDS )

2 mA =
1 mA / V 2
2
[ ]
(VGS − VTN )2 (1 + 0.015 (7.5) )
4
VGS − VTN = = 1.9V
1.11
Georgia Tech
∴ g m = 2.11 mS g o = 27.1 µ S ⇒ ro = 36.9kΩ ECE 3040 - Dr. Alan Doolittle
 MOSFET Small Signal Model and Analysis
Example: Jaeger 13.94

vo vGS vo
Av = =
vs v s vGS
vGS vo
= − g m (ro R3) = −2.1mS (3.48k ) = −7.35
1Meg
= = 0.99 and Rd
vs 10k + 1Meg vGS
vo vGS vo
∴ Av = = = −7.27 [V / V ]
vs v s vGS

Georgia Tech ECE 3040 - Dr. Alan Doolittle

 MOSFET Small Signal Model and Analysis
Add in capacitances
Overlap of Overlap of
Gate Oxide Gate Oxide

LD LD
Gate to
channel to
Bulk
capacitance

Reverse Bias Junction capacitances

Georgia Tech ECE 3040 - Dr. Alan Doolittle

 MOSFET Small Signal Model and Analysis
Complete Model of a MOSFET
Overlap of Due to effective
γ modulation of the
Gate Oxide g mb = g m threshold voltage.
2 V SB + 2φ F

Overlap of
Gate Oxide Gate to
and Gate to channel to
channel Bulk Reverse Bias Junction capacitances
capacitance capacitance

Georgia Tech ECE 3040 - Dr. Alan Doolittle

 MOSFET Small Signal Model and Analysis
SPICE MOSFET Model
SPICE models the drain current ( IDS ) of an n-channel MOSFET using the
following parameters/equations (SPICE variables are shown in ALL
CAPPITAL LETTERS)

Cutoff: IDS = 0

Linear:
KP  W 
I DS =  V DS [2(VGS − VTH ) − V DS ](1 + (LAMBDA) V DS )
2  LEFF 
Saturation:

I DS =
KP  W

2  LEFF

[ ]
 (VGS − VTH )2 (1 + (LAMBDA) VDS )

Threshold Voltage:
(
VTH = VTO + GAMMA 2 PHI − VBS − 2 PHI )
Channel Length
LEFF=L-2LD
Georgia Tech ECE 3040 - Dr. Alan Doolittle
 MOSFET Small Signal Model and Analysis
SPICE MOSFET Model – Additional Parameters
SPICE takes many of it’s parameters from the integrated circuit
layout design:

W AD=WxLdiff(drain)
AS=WxLdiff(source)
PS=2xLdiff(source)+W L PD=2xLdiff(drain)+W
Ldiff(source)
Ldiff(drain)

Source Gate Drain

L = polysilicon gate length W = polysilicon gate width

AD = drain area AS = source area
PD = perimeter of drain diffusion (not including edge under gate)
PS = perimeter of source diffusion (not including edge under gate)
NRD = number of “squares” in drain diffusion Specified in terms of the
NRS = number of “squares” in source diffusion minimum feature size
Georgia Tech ECE 3040 - Dr. Alan Doolittle
 MOSFET Amplifiers
What is the Maximum Gain Possible?
Is it saturated (Constant current)?, VDS > VGS − VTP
but VDS = VGS
and VTP ≥ 0 for a depletion mode MOSFET so,
0 > −VTP is always satisfied. ⇒ Is Saturated!

AC
Signal
Gate
Bias

go is internal to the
transistor and can not be
avoided. Any additional
resistor due to external
circuitry will lower the
Av , Max = − g m vo
gain. For this reason
K n (VGS − VT )(1 + λ VDS ) current sources are often
Av , Max = −
λ K n (VGS − VT ) used as the “load” instead
2

of bias resistors in
(1 + λ VDS ) amplifier circuits.
Av , Max = −
λ (VGS − VT )
Georgia Tech ECE 3040 - Dr. Alan Doolittle
Work to be done in the lab

AIM: To design and implement a common source NMOS amplifier to amplify the audio signals

Concept:

There are multiple approaches to design an amplifier. One way is as follows:

Just assume DC conditions (DC voltages and resulting currents) first and then obtain the
gain based on those quiescent conditions/values. Build the circuit based on this design approach
and verify both DC and AC conditions.

It includes building an amplifier initially with input signal derived from a function
generator and output dropped across an oscilloscope.

Once the gain is stabilized, then you would use it as an audio amplifier for which, input
would be derived from an audio signal through an audio jack and output could be listened from a
headphone speaker.

In the preceding discussion, all (input and output voltages and currents) signals should be
measured with oscilloscope.

Procedure:

1. Build the circuit in Multisim and simulate

2. Input is applied using an AC source by connecting a function generator from instrument
toolbar.
3. Observe the output.
4. Is output and gain are as expected? Analyze the problem
5. See the model of NMOS and change the model parameters as given in the specifications
6. Again apply the input and see the output. Analyze the change in output
7. Find the gain.