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Dataflow Modeling (D-Sec)

The document discusses dataflow modeling, which is mainly used to describe combinational circuits. Dataflow modeling uses continuous assignments to connect inputs to outputs, where the right-hand side expression is continuously evaluated and assigned to the left-hand side whenever an input changes. Continuous assignments can specify delays and can be used to implicitly declare nets. Delays can be specified in regular assignments, implicit continuous assignments, or directly in net declarations. Logic synthesis tools can use dataflow models to generate gate-level netlists.

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Shachi P Gowda
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109 views26 pages

Dataflow Modeling (D-Sec)

The document discusses dataflow modeling, which is mainly used to describe combinational circuits. Dataflow modeling uses continuous assignments to connect inputs to outputs, where the right-hand side expression is continuously evaluated and assigned to the left-hand side whenever an input changes. Continuous assignments can specify delays and can be used to implicitly declare nets. Delays can be specified in regular assignments, implicit continuous assignments, or directly in net declarations. Logic synthesis tools can use dataflow models to generate gate-level netlists.

Uploaded by

Shachi P Gowda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Dataflow Modeling

Contents

• Dataflow modeling
• Introduction
• Continuous assignment
• Expressions
• Delay
• Constant
• Test bench
Why Dataflow ?
 Any digital system
• Interconnecting registers
• Combinational logic circuits

 Dataflow modeling style is mainly used to describe


combinational circuits.

 The basic mechanism used is the continuous


assignment.
Why Dataflow ?
• A powerful way to implement a design.

• Logic synthesis tools can be used to create a gate-


level net list
Basic Statements
 Continuous assignments Variations

• Net declaration assignments


• Implicit net declarations
‘assign’ statement
The assign statement is used to make continuous assignment in the dataflow
modeling.
assign out = in1 + in2; // in1 + in2 is evaluated and then assigned to out.
Note:
• The LHS of assign statement must always be a scalar or vector net or a
concatenation. It cannot be a register.
‘assign’ statement
Note:

• Continuous statements are always active statements - The RHS


expression is evaluated whenever one of its operands changes. The
result is assigned to the LHS.

• Registers or nets or function calls can come in the RHS of the


assignment.

• Delays can be specified.


Implicit Continuous Assignment
• There can be only one implicit declaration assignment per net because a
net is declared only once.
Continuous Assignments
 Syntax
assign [delay] net1_lvalue = expr1;
assign [delay] net2_lvalue = expr2;
...,
assign [delay] netn_lvalue = exprn;

assign [delay] net1_lvalue = expr1,


[delay] net2_lvalue = expr2,
...,
[delay] netn_lvalue = exprn;
Expressions
 Expression = Operators and Operands
• Operators
• Operands
Operators
Case Equalities
Operands
• constants
• parameters
• nets
• variables (reg, integer, time, real, realtime)
• bit-select
• part-sel
• function calls
• array element
Three Ways of Specifying Delays
 Regular assignment delay
 Implicit continuous assignment delay
 Net declaration delay
Regular Assignment Delays
 The inertial delay model is defaulted

wire in1, in2, out;


assign #10 out = in1 & in2;

 If in1 or in2 changes value again before 10time units when the result
propagates to out, the values of in1 and in2 at the time of recomputation
are considered. This property is called inertial delay.
 Inertial delays also apply to gate delays.
Regular Assignment Delays
Implicit Continuous Assignment Delays
Can use an implicit continuous assignment to specify both a delay
and an assignment on the net.
Net Declaration Delays
 A delay can be specified on a net when it is declared without
putting a continuous assignment on the net. If a delay is specified
on a net out, then any value change applied to the net out is
delayed accordingly.

 Net declaration delays can also be used in gate-level modeling


Net Declaration Delays (Transport delay)
 Associate a delay value with a net declaration
// net delays
wire #10 out;
assign out = in1 & in2;

// regular assignment delay


wire out;
assign #10 out = in1 & in2;

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