EXP NO: 01 DATE: 19-01-09

VERIFICATION OF LOGIC GATES

AIM:
To develop the source code for logic gates by using VHDL/VERILOG and obtain the simulation, synthesis,
place and route and implement into FPGA.

ALGORITM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

LOGIC DIAGRAM:

AND GATE: OR GATE:

LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH TABLE:

A B Y=AB
0 0 0 A B Y=A+B
0 1 0
0 0 0
1 0 0
NOT GATE: 0 1 1
1 1 1
NAND GATE: 1 0 1
LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM 1 1 1
TRUTH TABLE
A B Y=(AB)’
A Y=A’
0 0 1
0 1
1 0 0 1 1
1 0 1
1 1 0
NOR GATE: XOR GATE:
LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH TABLE

A B Y=(A+B)’ A B
XNOR GATE:
0 0 1 0 0 0
LOGIC DIAGRAM: 0 1 0 TRUTH 0 1 1
TABLE: 1 0 0 1 0 1
1 1 0 A B 1 1 0
0 0 1
0 1 0
1 0 0
1 1 1

VHDL SOURCE CODE:

--Design : VERIFICATION OF LOGIC GATES

--Description : To implement LOGIC GATES
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity logicgates is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic_vector(6 downto 0));
end logicgates;

architecture dataflow of logicgates is

begin
c(0)<= a and b;
c(1)<= a or b;
c(2)<= a nand b;
c(3)<= a nor b;
c(4)<= a xor b;
c(5)<= a xnor b;
c(6)<= not a;
end dataflow;

VERILOG SOURCE CODE:

module logicgates1(a, b, c);

input a;
input b;
OUTPUT: [6:0] c;

assign c[0]= a & b;

assign c[1]= a | b;
assign c[2]= ~(a & b);
assign c[3]= ~(a | b);
assign c[4]= a ^ b;
assign c[5]= ~(a ^ b);
assign c[6]= ~ a;

endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY logicgatestest_vhd IS
END logicgatestest_vhd;

ARCHITECTURE testbench OF logicgatestest_vhd IS

COMPONENT logicgates
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;

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 SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';

SIGNAL c : std_logic_vector(6 downto 0);

BEGIN

uut: logicgates PORT MAP(

a => a,
b => b,
c => c
);

tb : PROCESS
BEGIN

a<='0'; b<='0'; wait for 100 ps;

a<='0'; b<='1'; wait for 100 ps;
a<='1'; b<='0'; wait for 100 ps;
a<='1'; b<='1'; wait for 100 ps;

END PROCESS;

END testbench;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : logicgates.ngr
Top Level Output File Name : logicgates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

Design Statistics
# IOs :9

Cell Usage :
# BELS :7
# INV :1
# LUT2 :6
# IO Buffers :9
# IBUF :2
# OBUF :7
=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 3 out of 3584 0%

Number of 4 input LUTs: 6 out of 7168 0%
Number of bonded IOBs: 9 out of 97 9%
=========================================================================

TIMING REPORT

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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.985ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 13 / 7
-------------------------------------------------------------------------
Delay: 7.985ns (Levels of Logic = 3)
Source: a (PAD)
Destination: c<5> (PAD)

Data Path: a to c<5>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 7 0.715 1.201 a_IBUF (a_IBUF)
LUT2:I0->O 1 0.479 0.681 _n00021 (c_0_OBUF)
OBUF:I->O 4.909 c_0_OBUF (c<0>)
----------------------------------------
Total 7.985ns (6.103ns logic, 1.882ns route)
(76.4% logic, 23.6% route)

=========================================================================
CPU : 3.03 / 3.27 s | Elapsed : 3.00 / 4.00 s

Place and root report:

Constraints file: logicgates.pcf.

Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
"logicgates" is an NCD, version 3.1, device xc3s400, package tq144, speed -5
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "ADVANCED 1.35 2005-01-22".
Device Utilization Summary:
Number of External IOBs 9 out of 97 9%
Number of LOCed IOBs 0 out of 9 0%
Number of Slices 3 out of 3584 1%
Number of SLICEMs 0 out of 1792 0%
Overall effort level (-ol): Standard (set by user)

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Placer effort level (-pl): Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): Standard (set by user)
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:989697) REAL time: 0 secs
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs
Phase 3.2
Phase 3.2 (Checksum:1c9c37d) REAL time: 0 secs
Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 0 secs
Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 0 secs
Phase 6.8
Phase 6.8 (Checksum:98a327) REAL time: 0 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 0 secs
Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 0 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 0 secs
Writing design to file logicgates.ncd
Total REAL time to Placer completion: 0 secs
Total CPU time to Placer completion: 0 secs
Starting Router
Phase 1: 19 unrouted; REAL time: 0 secs
Phase 2: 19 unrouted; REAL time: 0 secs
Phase 3: 1 unrouted; REAL time: 0 secs
Phase 4: 0 unrouted; REAL time: 0 secs
Total REAL time to Router completion: 0 secs
Total CPU time to Router completion: 0 secs
Generating "PAR" statistics.
INFO:Par:340 -
The Delay report will not be generated when running non-timing driven PAR
with effort level Standard or Medium. If a delay report is required please do
one of the following: 1) use effort level High, 2) use the following
environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
constraints for the design.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 1 secs
Total CPU time to PAR completion: 1 secs
Peak Memory Usage: 76 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file logicgates.ncd
PAR done!

RESULT:
Thus the outputs of Basic Logic Gates are verified by simulating and synthesizing the VHDL and
VERILOG code.

EXP NO: 02 DATE: 22-01-09

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 ADDERS AND SUBTRACTORS
AIM:
To develop the source code for adders and subtractors by using VHDL/VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.

ALGORITM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

BASIC ADDERS & SUBTRACTORS:

HALF ADDER:

LOGIC DIAGRAM: TRUTH TABLE:

A B SUM CARRY

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

VHDL SOURCE CODE:

--Design : HALF ADDER

--Description : To implement HALF ADDER
--Author
--Reg no : 2882101
--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hadd is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end hadd;
architecture dataflow of hadd is
begin
sum <= a xor b;
carry <= a and b;
end dataflow;

Behavioral Modeling:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity haddbehavioral is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end haddbehavioral;
architecture Behavioral of haddbehavioral is
begin
p1:process (a,b)
begin
sum<= a xor b;
carry<= a and b;
end process p1;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity haddstructural is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end haddstructural;

architecture structural of haddstructural is

component xor2
port(a,b:in std_logic;
z:out std_logic);
end component;
component and2
port(a,b:in std_logic;
z:out std_logic);
end component;
begin
x1: xor2 port map (a,b,sum);
a1: and2 port map (a,b,carry);
end structural;

and2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is
begin
z<= a and b;

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end dataflow;

xor2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;

VERILOG SOURCE CODE:

Dataflow Modeling:

module ha_dataflow(a, b, s, ca);

input a;
input b;
output s;
output ca;
assign#2 s=a^b;
assign#2 ca=a&b;
endmodule

Behavioral Modeling:

module ha_behv(a, b, s, ca);

input a;
input b;
output s;
output ca;
reg s,ca;
always @ (a or b) begin
s=a^b;
ca=a&b;
end
endmodule

Structural Modeling:

module ha_struct(a, b, s, ca);

input a;
input b;
output s;
output ca;
xor
x1(s,a,b);
and
a1(ca,a,b);
endmodule
TEST BENCH(VHDL):

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_bench_vhd IS
END test_bench_vhd;

ARCHITECTURE behavior OF test_bench_vhd IS

COMPONENT hadd
PORT(
a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';

--Outputs
SIGNAL sum : std_logic;
SIGNAL carry : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: hadd PORT MAP(
a => a,
b => b,
sum => sum,
carry => carry
);

tb : PROCESS
BEGIN

a<='0'; b<='0'; wait for 100 ps;

a<='0'; b<='1'; wait for 100 ps;
a<='1'; b<='0'; wait for 100 ps;
a<='1'; b<='1'; wait for 100 ps;

END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0%

Number of 4 input LUTs: 2 out of 7168 0%
Number of bonded IOBs: 4 out of 97 4%
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns

HALF SUBSTRACTOR:

LOGIC DIAGRAM: TRUTH TABLE

A B DIFFERENCE BORROW

0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

VHDL SOURCE CODE:

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 --Design : HALF SUBSTRACTOR
--Description : To implement HALF SUBSTRACTOR
--Author : --Reg no : 2882101
--Version : Xilinx- 7.1i
Dataflow Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hsub_dataflow is
Port ( a : in std_logic;
b : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end hsub_dataflow;
architecture dataflow of hsub_dataflow is
begin
diff <= a xor b;
borrow <= not a and b;
end dataflow;

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hsub_behv is
Port ( a : in std_logic;
b : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end hsub_behv;
architecture Behavioral of hsub_behv is
begin
p1:process(a,b)
variable abar:std_logic;
begin
abar:= not a;
diff<=a xor b;
borrow<=abar and b;
end process p1;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hsub_structural is
Port ( a : in std_logic;
b : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end hsub_structural;
architecture structural of hsub_structural is
component xor2
port(a,b:in std_logic;

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 z:out std_logic);
end component;
component and2
port(a,b:in std_logic;
z:out std_logic);
end component;
component not1
port(a:in std_logic;
z:out std_logic);
end component;
signal abar:std_logic;
begin
x1:xor2 port map (a,b,diff);
a1:and2 port map (abar,b,borrow);
n1:not1 port map (a,abar);
end structural;

and2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is
begin
z<= a and b;
end dataflow;

xor2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;

not1 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is

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begin
z<= not a;
end dataflow;

VERILOG SOURCE CODE:

Dataflow Modeling:

module hs_dataflow(a, b, dif, bor);

input a;
input b;
output dif;
output bor;
wire abar;
assign#3 abar=~a;
assign#3 dif=a^b;
assign#3 bor=b&abar;
endmodule

Behavioral Modeling:

module hs_behv(a, b, dif, bor);

input a;
input b;
output dif;
output bor;
reg dif,bor;
reg abar;
always@(a or b) begin
abar=~a;
dif=a^b;
bor=b&abar;
end
endmodule

Structural Modeling:

module hs_struct(a, b, dif, bor);

input a;
input b;
output dif;
output bor;
wire abar;
xor
x1(dif,a,b);
not
n1(abar,a);
and
a1(bor,abar,b);
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

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ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT hsub_dataflow
PORT(
a : IN std_logic;
b : IN std_logic;
diff : OUT std_logic;
borrow : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';

--Outputs
SIGNAL diff : std_logic;
SIGNAL borrow : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: hsub_dataflow PORT MAP(
a => a,
b => b,
diff => diff,
borrow => borrow
);

tb : PROCESS
BEGIN

a<='0'; b<='0'; wait for 100 ps;

a<='0'; b<='1'; wait for 100 ps;
a<='1'; b<='0'; wait for 100 ps;
a<='1'; b<='1'; wait for 100 ps;

END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0%

Number of 4 input LUTs: 2 out of 7168 0%
Number of bonded IOBs: 4 out of 97 4%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns

FULL ADDER:

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LOGIC DIAGRAM: TRUTH TABLE:

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

VHDL SOURCE CODE:

--Design : FULL ADDER

--Description : To implement FULL ADDER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_dataflow is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_dataflow;
architecture dataflow of fadd_dataflow is
signal p,q,r,s:std_logic;
begin
p<= a xor b;
q<= a and b;
r<= b and c;
s<= c and a;
sum<= p xor c;
carry<= q or r or s;
end dataflow;

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_behv is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_behv;
architecture Behavioral of fadd_behv is

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begin
p1:process(a,b,c)
variable r,s,t:std_logic;
begin
r:= a and b;
s:= b and c;
t:= c and a;
sum<= a xor b xor c;
carry<= r or s or t;
end process p1;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_structural is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_structural;
architecture structural of fadd_structural is
component xor2
port(a,b:in std_logic;
z:out std_logic);
end component;
component and2
port(a,b:in std_logic;
z:out std_logic);
end component;
component or3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
signal p,q,r,s:std_logic;
begin
x1: xor2 port map (a,b,p);
x2: xor2 port map (p,c,sum);
a1: and2 port map (a,b,q);
a2: and2 port map (b,c,r);
a3: and2 port map (c,a,s);
o1: or3 port map (q,r,s,carry);
end structural;

and2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is

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begin
z<= a and b;
end dataflow;

or3 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or3 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
z : out std_logic);
end or3;
architecture dataflow of or3 is
begin
z<= a or b or c;
end dataflow;

xor2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;

VERILOG SOURCE CODE:

Dataflow Modeling:

module fulladddataflow(a, b, cin, sum, carry);

input a;
input b;
input cin;
output sum;
output carry;
assign sum=a^b^cin;
assign carry=(a & b) | (b & cin) | (cin & a);
endmodule

Behavioral Modeling:

module fuladbehavioral(a, b, c, sum, carry);

input a;
input b;
input c;
output sum;
output carry;

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 reg sum,carry;
reg t1,t2,t3;
always @ (a or b or c) begin
sum = (a^b)^c;
t1=a & b;
t2=b & c;
t3=a & c;
carry=(t1 | t2) | t3;
end
endmodule

Structural Modeling:

module fa_struct(a, b, c, sum, carry);

input a;
input b;
input c;
output sum;
output carry;
wire p,q,r,s;
xor
x1(p,a,b),
x2(sum,p,c);
and
a1(q,a,b),
a2(r,b,c),
a3(s,a,c);
or
o1(carry,q,r,s);
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test1_vhd IS
END test1_vhd;

ARCHITECTURE behavior OF test1_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fadd_dataflow
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';

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 --Outputs
SIGNAL sum : std_logic;
SIGNAL carry : std_logic;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fadd_dataflow PORT MAP(
a => a,
b => b,
c => c,
sum => sum,
carry => carry
);

tb : PROCESS
BEGIN

a<='0'; b<='0'; c<='0'; wait for 100 ps;

a<='0'; b<='0'; c<='1'; wait for 100 ps;
a<='0'; b<='1'; c<='0'; wait for 100 ps;
a<='0'; b<='1'; c<='1'; wait for 100 ps;
a<='1'; b<='0'; c<='0'; wait for 100 ps;
a<='1'; b<='0'; c<='1'; wait for 100 ps;
a<='1'; b<='1'; c<='0'; wait for 100 ps;
a<='1'; b<='1'; c<='1'; wait for 100 ps;
END PROCESS;
END;

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================

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* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0%

Number of 4 input LUTs: 2 out of 7168 0%
Number of bonded IOBs: 5 out of 97 5%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns

FULL SUBSTRACTOR:

LOGIC DIAGRAM: TRUTH TABLE:

A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

VHDL SOURCE CODE:

--Design :FULL SUBSTRACTOR

--Description : To implement FULL SUBSTRACTOR
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Dataflow Modeling:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub_dataflow is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub_dataflow;
architecture dataflow of fsub_dataflow is
signal abar:std_logic;
begin
abar<=not a;
diff<=a xor b xor c;
borrow<=(abar and b) or (b and c) or (c and abar);
end dataflow;

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub_behv is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub_behv;
architecture Behavioral of fsub_behv is
begin
p1:process(a,b,c)
variable abar,r,s,t:std_logic;
begin
abar:=not a;
r:=abar and b;
s:=b and c;
t:=c and abar;
diff<=a xor b xor c;
borrow<=r or s or t;
end process p1;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub_structural is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub_structural;
architecture structural of fsub_structural is

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component xor2
port(a,b:in std_logic;
z:out std_logic);
end component;
component and2
port(a,b:in std_logic;
z:out std_logic);
end component;
component not1
port(a:in std_logic;
z:out std_logic);
end component;
component or3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
signal p,q,r,s,abar:std_logic;
begin
x1:xor2 port map (a,b,p);
x2:xor2 port map (p,c,diff);
n1:not1 port map (a,abar);
a1:and2 port map (abar,b,q);
a2:and2 port map (b,c,r);
a3:and2 port map (c,abar,s);
o1:or3 port map (q,r,s,borrow);
end structural;

VERILOG SOURCE CODE:

Dataflow Modeling:

module fulsubdataflow(a, b, cin, diff, borrow);

input a;
input b;
input cin;
output diff;
output borrow;
wire abar;
assign abar= ~ a;
assign diff=a^b^cin;
assign borrow=(abar & b) | (b & cin) |(cin & abar);

endmodule

Behavioral Modeling:

module fulsubbehavioral(a, b, cin, diff, borrow);

input a;
input b;
input cin;
output diff;
output borrow;
reg t1,t2,t3;
reg diff,borrow;
reg abar;
always @ (a or b or cin) begin
abar= ~ a;
diff = (a^b)^cin;
t1=abar & b;
t2=b & cin;

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 t3=cin & abar;
borrow=(t1 | t2) | t3;
end
endmodule

Structural Modeling:

module fs_struct(a, b, c, diff, borrow);

input a;
input b;
input c;
output diff;
output borrow;
wire abar,p,q,r,s;
not
n1(abar,a);
xor
x1(p,a,b),
x2(diff,p,c);
and
a1(q,abar,b),
a2(r,abar,c),
a3(s,a,c);
or
o1(borrow,q,r,s);
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tst_vhd IS
END tst_vhd;

ARCHITECTURE behavior OF tst_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fsub_dataflow
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
diff : OUT std_logic;
borrow : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';

--Outputs
SIGNAL diff : std_logic;
SIGNAL borrow : std_logic;

BEGIN

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 -- Instantiate the Unit Under Test (UUT)
uut: fsub_dataflow PORT MAP(
a => a,
b => b,
c => c,
diff => diff,
borrow => borrow
);

tb : PROCESS
BEGIN
a<='0'; b<='0'; c<='0'; wait for 100 ps;
a<='0'; b<='0'; c<='1'; wait for 100 ps;
a<='0'; b<='1'; c<='0'; wait for 100 ps;
a<='0'; b<='1'; c<='1'; wait for 100 ps;
a<='1'; b<='0'; c<='0'; wait for 100 ps;
a<='1'; b<='0'; c<='1'; wait for 100 ps;
a<='1'; b<='1'; c<='0'; wait for 100 ps;
a<='1'; b<='1'; c<='1'; wait for 100 ps;
END PROCESS;
END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0%

Number of 4 input LUTs: 2 out of 7168 0%
Number of bonded IOBs: 5 out of 97 5%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns

FULL ADDER USING TWO HALF ADDERS:

LOGIC DIAGRAM: TRUTH TABLE:

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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VHDL SOURCE CODE:

--Design : FULL ADDER USING TWO HALF ADDERS

--Description : To implement FULL ADDER USING TWO HALF ADDERS
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd2 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd2;
architecture structural of fadd2 is
component hadd
port(a,b:in std_logic;
sum,carry:out std_logic);
end component;
component or2
port(a,b:in std_logic;
z:out std_logic);
end component;
signal p,q,r:std_logic;
begin
h1:hadd port map (a,b,p,q);
h2:hadd port map (p,c,sum,r);
o1:or2 port map (r,q,carry);
end structural;

hadd component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hadd is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end hadd;
architecture dataflow of hadd is
begin
sum <= a xor b;
carry <= a and b;
end dataflow;

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or2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end or2;
architecture dataflow of or2 is
begin
z<= a or b;
end dataflow;

VERILOG SOURCE CODE:

Structural Modeling:

module fa_2ha(a, b, c, sum, carry);

input a;
input b;
input c;
output sum;
output carry;
wire p,q,r;
ha_dataflow
h1(a,b,p,q),
h2(p,c,sum,r);
or
o1(carry,q,r);
endmodule

module ha_dataflow(a, b, s, ca);

input a;
input b;
output s;
output ca;
assign#2 s=a^b;
assign#2 ca=a&b;
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tst_vhd IS
END tst_vhd;

ARCHITECTURE behavior OF tst_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fadd2
PORT(
a : IN std_logic;
b : IN std_logic;

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 c : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';

--Outputs
SIGNAL sum : std_logic;
SIGNAL carry : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fadd2 PORT MAP(
a => a,
b => b,
c => c,
sum => sum,
carry => carry
);

tb : PROCESS
BEGIN
a<='0'; b<='0'; c<='0'; wait for 100 ps;
a<='0'; b<='0'; c<='1'; wait for 100 ps;
a<='0'; b<='1'; c<='0'; wait for 100 ps;
a<='0'; b<='1'; c<='1'; wait for 100 ps;
a<='1'; b<='0'; c<='0'; wait for 100 ps;
a<='1'; b<='0'; c<='1'; wait for 100 ps;
a<='1'; b<='1'; c<='0'; wait for 100 ps;
a<='1'; b<='1'; c<='1'; wait for 100 ps;
END PROCESS;
END;

Simulation output:

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Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0%

Number of 4 input LUTs: 2 out of 7168 0%
Number of bonded IOBs: 5 out of 97 5%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns

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FULL SUBTRACTOR USING TWO HALF SUBTRACTORS:

LOGIC DIAGRAM: TRUTH TABLE:

A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

VHDL SOURCE CODE:

--Design : FULL SUBTRACTOR USING TWO HALF SUBTRACTORS

--Description : To implement FULL SUBTRACTOR USING TWO HALF SUBTRACTORS
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub2 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub2;
architecture structural of fsub2 is
component hsub_dataflow
port(a,b:in std_logic;
diff,borrow:out std_logic);
end component;
component or2
port(a,b:in std_logic;
z:out std_logic);
end component;
signal p,q,r:std_logic;
begin
h1:hsub_dataflow port map (a,b,p,q);
h2:hsub_dataflow port map (p,c,diff,r);
o1:or2 port map (r,q,borrow);
end structural;

hsub component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity hsub_dataflow is
Port ( a : in std_logic;
b : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end hsub_dataflow;
architecture dataflow of hsub_dataflow is
begin
diff <= a xor b;
borrow <= not a and b;
end dataflow;

VERILOG SOURCE CODE:

Structural Modeling:

module fs_2hs(a, b, c, diff, borrow);

input a;
input b;
input c;
output diff;
output borrow;
wire p,q,r;
hs_dataflow
h1(a,b,p,q),
h2(p,c,diff,r);
or
o1(borrow,q,r);
endmodule

module hs_dataflow(a, b, dif, bor);

input a;
input b;
output dif;
output bor;
wire abar;
assign#3 abar=~a;
assign#3 dif=a^b;
assign#3 bor=b&abar;
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tst_vhd IS
END tst_vhd;

ARCHITECTURE behavior OF tst_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fsub2
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
diff : OUT std_logic;

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 borrow : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';

--Outputs
SIGNAL diff : std_logic;
SIGNAL borrow : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fsub2 PORT MAP(
a => a,
b => b,
c => c,
diff => diff,
borrow => borrow
);

tb : PROCESS
BEGIN
a<='0'; b<='0'; c<='0'; wait for 100 ps;
a<='0'; b<='0'; c<='1'; wait for 100 ps;
a<='0'; b<='1'; c<='0'; wait for 100 ps;
a<='0'; b<='1'; c<='1'; wait for 100 ps;
a<='1'; b<='0'; c<='0'; wait for 100 ps;
a<='1'; b<='0'; c<='1'; wait for 100 ps;
a<='1'; b<='1'; c<='0'; wait for 100 ps;
a<='1'; b<='1'; c<='1'; wait for 100 ps;
END PROCESS;
END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0%

Number of 4 input LUTs: 2 out of 7168 0%
Number of bonded IOBs: 5 out of 97 5%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns

RIPPLE CARRY ADDER (Binary adder):

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 LOGIC DIAGRAM:

A(0) B(0) A(1) B(1) A(2) B(2) A(3) B(3)

Cin

S(0) S(1) S(2) S(3)

VHDL SOURCE CODE:

--Design : RIPPLE CARRY ADDER

--Description : To implement RIPPLE CARRY ADDER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rca is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end rca;
architecture structural of rca is
component fadd_behv
port(a,b,c:in std_logic;
sum,carry:out std_logic);
end component;
signal c0,c1,c2:std_logic;
begin
f1:fadd_behv port map (a(0),b(0),c,s(0),c0);
f2:fadd_behv port map (a(1),b(1),c0,s(1),c1);
f3:fadd_behv port map (a(2),b(2),c1,s(2),c2);
f4:fadd_behv port map (a(3),b(3),c2,s(3),cout);
end structural;

fadd_behv component source code:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_behv is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_behv;
architecture Behavioral of fadd_behv is
begin
p1:process(a,b,c)
variable r,s,t:std_logic;
begin
r:= a and b;
s:= b and c;
t:= c and a;
sum<= a xor b xor c;
carry<= r or s or t;
end process p1;
end Behavioral;

VERILOG SOURCE CODE:

Structural Modeling:
module rcastructural(a, b, c, s, cout);
input [3:0] a;
input [3:0] b;
input c;
output [3:0] s;
output cout;
wire c1,c2,c3;
fulladddataflow
f1(a[0],b[0],c,s[0],c1),
f2(a[1],b[1],c1,s[1],c2),
f3(a[2],b[2],c2,s[2],c3),
f4(a[3],b[3],c3,s[3],cout);
endmodule
FULL ADDER SOURCE CODE:

module fulladddataflow(a, b, cin, sum, carry);

input a;
input b;
input cin;
output sum;
output carry;
assign sum=a^b^cin;
assign carry=(a & b) | (b & cin) | (cin & a);
endmodule

TEST BENCH(VHDL):

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT rca
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
c : IN std_logic;
s : OUT std_logic_vector(3 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL c : std_logic := '0';
SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL s : std_logic_vector(3 downto 0);
SIGNAL cout : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: rca PORT MAP(
a => a,
b => b,
c => c,
s => s,
cout => cout
);

tb : PROCESS
BEGIN
a<="0010";b<="1001";c<='1'; wait for 200 ps;
a<="1100";b<="0101";c<='0'; wait for 200 ps;
a<="1111";b<="0100";c<='1'; wait for 200 ps;
END PROCESS;
END;

Simulation output:

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Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
--------------------------
Selected Device : 3s400tq144-5
Number of Slices: 5 out of 3584 0%
Number of 4 input LUTs: 9 out of 7168 0%
Number of bonded IOBs: 14 out of 97 14%
=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------

Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 11.747ns

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FAST ADDERS:

CARRY SELECT ADDER:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : CARRY SELECT ADDER

--Description : To implement CARRY SELECT ADDER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity csa is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic;
su : inout std_logic_vector(3 downto 0);
sd : inout std_logic_vector(3 downto 0);
s : out std_logic_vector(7 downto 0);
cout : out std_logic);
end csa;
architecture structural of csa is
component rca
port(a,b:in std_logic_vector(3 downto 0);
c:in std_logic;
s:out std_logic_vector(3 downto 0);
cout:out std_logic);
end component;
component mux2
port(a,b,s:in std_logic;
z:out std_logic);
end component;
signal c1,c2,c3:std_logic;
begin

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r1:rca port map (a(3 downto 0),b(3 downto 0),c,s(3 downto 0),c1);
r2:rca port map (a(7 downto 4),b(3 downto 0),'0',su(3 downto 0),c2);
r3:rca port map (a(7 downto 4),b(3 downto 0),'1',sd(3 downto 0),c3);
m1:mux2 port map (su(0),sd(0),c1,s(4));
m2:mux2 port map (su(1),sd(1),c1,s(5));
m3:mux2 port map (su(2),sd(2),c1,s(6));
m4:mux2 port map (su(3),sd(3),c1,s(7));
m5:mux2 port map (c2,c3,c1,cout);
end structural;

rca component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rca is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end rca;
architecture structural of rca is
component fadd_behv
port(a,b,c:in std_logic;
sum,carry:out std_logic);
end component;
signal c0,c1,c2:std_logic;
begin
f1:fadd_behv port map (a(0),b(0),c,s(0),c0);
f2:fadd_behv port map (a(1),b(1),c0,s(1),c1);
f3:fadd_behv port map (a(2),b(2),c1,s(2),c2);
f4:fadd_behv port map (a(3),b(3),c2,s(3),cout);
end structural;

mux2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux2 is
Port ( a : in std_logic;
b : in std_logic;
s : in std_logic;
z : out std_logic);
end mux2;
architecture behv of mux2 is
begin
process(a,b,s)
begin
if (s='0') then
z<=a;
else
z<=b;
end if;
end process;
end behv;

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VERILOG SOURCE CODE:

Structural Modeling:

module carryselectadder(a, b, cin, sum, cout);

input [8:1] a;
input [8:1] b;
input cin;
output [8:1]sum;
output cout;
wire c,ctop,cbot;
wire [3:0]stop,sbot;
rcast
r1(a[4:1],b[4:1],cin,sum[4:1],c),
r2(a[8:5],b[8:5],0,sbot[3:0],cbot),
r3(a[8:5],b[8:5],1,stop[3:0],ctop);
mux2
m1(stop[0],sbot[0],c,sum[5]),
m2(stop[1],sbot[1],c,sum[6]),
m3(stop[2],sbot[2],c,sum[7]),
m4(stop[3],sbot[3],c,sum[8]),
m5(ctop,cbot,c,cout);
endmodule

rca component source code:

module rcast(a, b, c, s, ca);

input [3:0] a;
input [3:0] b;
input c;
output [3:0] s;
output ca;
wire c1,c2,c3;
fulladddataflow
f1(a[0],b[0],c,s[0],c1),
f2(a[1],b[1],c1,s[1],c2),
f3(a[2],b[2],c2,s[2],c3),
f4(a[3],b[3],c3,s[3],ca);
endmodule

mux2 component source code:

module mux2(i0, i1, s0, y);

input i0;
input i1;
input s0;
output y;
wire s0bar,p,q;
not
n1(s0bar,s0);
and
a1(p,i0,s0bar),
a2(q,i1,s0);
or
o1(y,p,q);
endmodule

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TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT csa
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
c : IN std_logic;
su : INOUT std_logic_vector(3 downto 0);
sd : INOUT std_logic_vector(3 downto 0);
s : OUT std_logic_vector(7 downto 0);
cout : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL c : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');

--BiDirs
SIGNAL su : std_logic_vector(3 downto 0);
SIGNAL sd : std_logic_vector(3 downto 0);

--Outputs
SIGNAL s : std_logic_vector(7 downto 0);
SIGNAL cout : std_logic;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: csa PORT MAP(
a => a,
b => b,
c => c,
su => su,
sd => sd,
s => s,
cout => cout
);

tb : PROCESS
BEGIN
a<="11111010";b<="10101011";c<='1'; wait for 200ps;
a<="11001011";b<="11100011";c<='0'; wait for 200ps;
END PROCESS;

END;

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Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 21 out of 3584 0%

Number of 4 input LUTs: 37 out of 7168 0%
Number of bonded IOBs: 34 out of 97 35%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 16.084ns

CARRY SKIP ADDER:

LOGIC DIAGRAM:

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VHDL SOURCE CODE:

--Design : CARRY SKIP ADDER

--Description : To implement CARRY SKIP ADDER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cskadd is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic;
s : out std_logic_vector(7 downto 0);
cout : out std_logic);
end cskadd;
architecture structural of cskadd is
component rca
port(a,b:in std_logic_vector(3 downto 0);
c:in std_logic;
s:out std_logic_vector(3 downto 0);
cout:out std_logic);
end component;
component skip
port(a,b:in std_logic_vector(3 downto 0);
c:in std_logic;
z:out std_logic);
end component;
component or2
port(a,b:in std_logic;
z:out std_logic);
end component;
signal c1,c2,c3,x1,x2:std_logic;
begin
r1:rca port map (a(3 downto 0),b(3 downto 0),c,s(3 downto 0),c1);
r2:rca port map (a(7 downto 4),b(7 downto 4),c2,s(7 downto 4),c3);
s1:skip port map (a(3 downto 0),b(3 downto 0),c,x1);
s2:skip port map (a(7 downto 4),b(7 downto 4),c2,x2);
o1:or2 port map (c1,x1,c2);
o2:or2 port map (c3,x2,cout);
end structural;

rca component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rca is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : in std_logic;
s : out std_logic_vector(3 downto 0);

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 cout : out std_logic);
end rca;
architecture structural of rca is
component fadd_behv
port(a,b,c:in std_logic;
sum,carry:out std_logic);
end component;
signal c0,c1,c2:std_logic;
begin
f1:fadd_behv port map (a(0),b(0),c,s(0),c0);
f2:fadd_behv port map (a(1),b(1),c0,s(1),c1);
f3:fadd_behv port map (a(2),b(2),c1,s(2),c2);
f4:fadd_behv port map (a(3),b(3),c2,s(3),cout);
end structural;

or2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end or2;
architecture dataflow of or2 is
begin
z<= a or b;
end dataflow;

skip component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity skip is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : in std_logic;
z : out std_logic);
end skip;
architecture dataflow of skip is
begin
z<=(a(0) xor b(0)) and (a(1) xor b(1)) and (a(2) xor b(2)) and (a(3) xor b(3)) and c;
end dataflow;

VERILOG SOURCE CODE:

Structural Modeling:

module cskadd(a, b, cin, sum, cout);

input [8:1] a;
input [8:1] b;
input cin;
output [8:1] sum;
output cout;
wire c1,c2,c3,x1,x2;
rcast

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 r1(a[4:1],b[4:1],cin,sum[4:1],c1),
r2(a[8:5],b[8:5],c2,sum[8:5],c3);
skpckt
s1(a[4:1],b[4:1],cin,x1),
s2(a[8:5],b[8:5],c2,x2);
or
o1(c2,x1,c1),
o2(cout,x2,c3);
endmodule

rca component source code:

module rcast(a, b, c, s, ca);

input [3:0] a;
input [3:0] b;
input c;
output [3:0] s;
output ca;
wire c1,c2,c3;
fulladddataflow
f1(a[0],b[0],c,s[0],c1),
f2(a[1],b[1],c1,s[1],c2),
f3(a[2],b[2],c2,s[2],c3),
f4(a[3],b[3],c3,s[3],ca);
endmodule

skipckt component source code:

module skpckt(x, y, z, sk);

input [3:0] x;
input [3:0] y;
input z;
output sk;
wire [3:0]p;
wire sk1;
xor
x1(p[0],x[0],y[0]),
x2(p[1],x[1],y[1]),
x3(p[2],x[2],y[2]),
x4(p[3],x[3],y[3]);
and
a1(sk1,p[0],p[1],p[2],p[3]),
a2(sk,sk1,z);
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cskadd
PORT(

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 a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
c : IN std_logic;
s : OUT std_logic_vector(7 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL c : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL s : std_logic_vector(7 downto 0);
SIGNAL cout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cskadd PORT MAP(
a => a,
b => b,
c => c,
s => s,
cout => cout
);
tb : PROCESS
BEGIN
a<="11111010";b<="10101011";c<='1'; wait for 200ps;
a<="11001011";b<="11100011";c<='0'; wait for 200ps;
END PROCESS;
END;

Simulation output:

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Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 13 out of 3584 0%

Number of 4 input LUTs: 23 out of 7168 0%
Number of bonded IOBs: 26 out of 97 26%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 17.358ns

CARRY LOOK AHEAD ADDER:

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LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : CARRY LOOK AHEAD ADDER

--Description : To implement CARRY LOOK AHEAD ADDER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity calkadd is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic;
s : out std_logic_vector(7 downto 0);
cout : out std_logic);
end calkadd;
architecture structural of calkadd is
component fulladd
port(a,b,c:in std_logic;
s,ca:out std_logic);
end component;
signal c0,c1,c2,c3,c4,c5,c6:std_logic;
begin
f1:fulladd port map (a(0),b(0),c,s(0),c0);
f2:fulladd port map (a(1),b(1),c0,s(1),c1);
f3:fulladd port map (a(2),b(2),c1,s(2),c2);
f4:fulladd port map (a(3),b(3),c2,s(3),c3);
f5:fulladd port map (a(4),b(4),c3,s(4),c4);
f6:fulladd port map (a(5),b(5),c4,s(5),c5);
f7:fulladd port map (a(6),b(6),c5,s(6),c6);
f8:fulladd port map (a(7),b(7),c6,s(7),cout);
end structural;

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fulladd component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladd is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
ca : out std_logic);
end fulladd;
architecture dataflow of fulladd is
signal l,m,g,p:std_logic;
begin
l<=a xor b;
m<=p and c;
g<=a and b;
p<=a or b;
s<=c xor l;
ca<=g or m;
end dataflow;

VERILOG SOURCE CODE:

Structural Modeling:

module clkadd(x, y, cin, sum, cout);

input [7:0] x;
input [7:0] y;
input cin;
output [7:0] sum;
output cout;
wire a1,a2,a3,a4,a5,a6,a7;
fulladddataflow
f1(x[0],y[0],cin,sum[0],a1),
f2(x[1],y[1],a1,sum[1],a2),
f3(x[2],y[2],a2,sum[2],a3),
f4(x[3],y[3],a3,sum[3],a4),
f5(x[4],y[4],a4,sum[4],a5),
f6(x[5],y[5],a5,sum[5],a6),
f7(x[6],y[6],a6,sum[6],a7),
f8(x[7],y[7],a7,sum[7],cout);
endmodule

fulladd component source code:

module fulladddataflow(a, b, cin, sum, carry);

input a;
input b;
input cin;
output sum;
output carry;
assign sum=a^b^cin;
assign carry=(a & b) | (b & cin) | (cin & a);
endmodule

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TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT calkadd
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
c : IN std_logic;
s : OUT std_logic_vector(7 downto 0);
cout : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL c : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');

--Outputs
SIGNAL s : std_logic_vector(7 downto 0);
SIGNAL cout : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: calkadd PORT MAP(
a => a,
b => b,
c => c,
s => s,
cout => cout
);

tb : PROCESS
BEGIN
a<="11111010";b<="10101011";c<='1'; wait for 200ps;
a<="11001011";b<="11100011";c<='0'; wait for 200ps;
END PROCESS;
END;

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Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 10 out of 3584 0%

Number of 4 input LUTs: 17 out of 7168 0%
Number of bonded IOBs: 26 out of 97 26%

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=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 17.102ns

RESULT:
Thus the OUTPUT’s of Adders,Subtractors and Fast Adders are verified by synthesizing and simulating the
VHDL and VERILOG code.

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EXP NO: 03 DATE: 22-02-09

ENCODERS AND DECODERS

AIM:
To develop the source code for encoders and decoders by using VHDL/VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.

ALGORITM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

ENCODER:

LOGIC DIAGRAM: TRUTH TABLE:

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

VHDL SOURCE CODE:

--Design : ENCODER
--Description : To implement ENCODER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_dataflow is
Port ( d : in std_logic_vector(7 downto 0);
z : out std_logic_vector(2 downto 0));
end encoder_dataflow;
architecture dataflow of encoder_dataflow is
begin
z(2)<= d(4) or d(5) or d(6) or d(7);
z(1)<= d(2) or d(3) or d(6) or d(7);
z(0)<= d(1) or d(3) or d(5) or d(7);
end dataflow;

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Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_behv is
Port ( d : in std_logic_vector(7 downto 0);
e : in std_logic;
z : out std_logic_vector(2 downto 0));
end encoder_behv;
architecture Behavioral of encoder_behv is
begin
p1:process(d,e)
begin
if (e='1') then
case d is
when "10000000"=>z<="000";
when "01000000"=>z<="001";
when "00100000"=>z<="010";
when "00010000"=>z<="011";
when "00001000"=>z<="100";
when "00000100"=>z<="101";
when "00000010"=>z<="110";
when "00000001"=>z<="111";
when others=>z<="ZZZ";
end case;
else
z<="XXX";
end if;
end process p1;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_struct is
Port ( d : in std_logic_vector(7 downto 0);
z : out std_logic_vector(2 downto 0));
end encoder_struct;
architecture structural of encoder_struct is
component or4
port(a,b,c,d:in std_logic;
z:out std_logic);
end component;
begin
o1:or4 port map (d(4),d(5),d(6),d(7),z(0));
o2:or4 port map (d(2),d(3),d(6),d(7),z(1));
o3:or4 port map (d(1),d(3),d(5),d(7),z(2));
end structural;

or4 component source code:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or4 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
z : out std_logic);
end or4;
architecture dataflow of or4 is
begin
z<=a or b or c or d;
end dataflow;

VERILOG SOURCE CODE:

Dataflow Modeling:

module encod_data(d, x, y, z);

input [7:0] d;
output x;
output y;
output z;
assign#3 x=d[4]|d[5]|d[6]|d[7];
assign#3 y=d[2]|d[3]|d[6]|d[7];
assign#3 z=d[1]|d[3]|d[5]|d[7];
endmodule

Behavioral Modeling:

module encoderbehav(d, x, y, z);

input [7:0] d;
output x;
output y;
output z;
reg x,y,z;
always @ (d [7:0]) begin
x= d[4] | d[5] | d[6] | d[7];
y= d[2] | d[3] | d[6] | d[7];
z= d[1] | d[3] | d[5] | d[7];
end
endmodule

Structural Modeling:

module encod_struct(d, x, y, z);

input [7:0] d;
output x;
output y;
output z;
or
o1(x,d[4],d[5],d[6],d[7]),
o2(y,d[2],d[3],d[6],d[7]),
o3(z,d[1],d[3],d[5],d[7]);
endmodule
TEST BENCH(VHDL):

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT encoder_dataflow
PORT(
d : IN std_logic_vector(7 downto 0);
z : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL z : std_logic_vector(2 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: encoder_dataflow PORT MAP(
d => d,
z => z
);

tb : PROCESS
BEGIN
d<="10000000"; wait for 100ps;
d<="00010000"; wait for 100ps;
d<="00100000"; wait for 100ps;
END PROCESS;

END;

Simulation output:

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Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 2 out of 3584 0%

Number of 4 input LUTs: 3 out of 7168 0%
Number of bonded IOBs: 11 out of 97 11%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.760ns

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DECODERS:

LOGIC DIAGRAM: TRUTH TABLE:

A B C Z(0) Z(1) Z(2) Z(3)

0 0 1 0 1 1 1
0 1 1 1 0 1 1
1 0 1 1 1 0 1
1 1 1 1 1 1 0

VHDL SOURCE CODE:

--Design : DECODER
--Description : To implement DECODER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_dataflow is
Port ( a : in std_logic;
b : in std_logic;
e : in std_logic;
z : out std_logic_vector(3 downto 0));
end decoder_dataflow;
architecture dataflow of decoder_dataflow is
signal abar,bbar:std_logic;
begin
abar<= not a;
bbar<= not b;
z(0)<= not (abar and bbar and e);
z(1)<= not (abar and b and e);
z(2)<= not (a and bbar and e);
z(3)<= not (a and b and e);
end dataflow;

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Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_behv is
Port ( a : in std_logic;
b : in std_logic;
e : in std_logic;
z : out std_logic_vector(3 downto 0));
end decoder_behv;
architecture Behavioral of decoder_behv is
begin
p1:process(a,b)
begin
if (e='1') then
z(0)<= not a and not b ;
z(1)<= not a and b;
z(2)<= a and not b;
z(3)<= a and b;
else
z<="1111";
end if;
end process p1;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_struct is
Port ( a : in std_logic;
b : in std_logic;
e : in std_logic;
z : out std_logic_vector(3 downto 0));
end decoder_struct;
architecture structural of decoder_struct is
component nand3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
component not1
port(a:in std_logic;
z:out std_logic);
end component;
signal abar,bbar:std_logic;
begin
n1:not1 port map (a,abar);
n2:not1 port map (b,bbar);
a1:nand3 port map (abar,bbar,e,z(0));
a2:nand3 port map (abar,b,e,z(1));
a3:nand3 port map (a,bbar,e,z(2));
a4:nand3 port map (a,b,e,z(3));
end structural;

nand3 component source code:

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nand3 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
z : out std_logic);
end nand3;
architecture dataflow of nand3 is
begin
z<= not (a and b and c);
end dataflow;

not1 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is
begin
z<= not a;
end dataflow;

VERILOG SOURCE CODE:

Dataflow Modeling:

module decoderdataflow(a,b,en, z);

input a,b,en;
output [0:3] z;
wire abar,bbar;
assign # 1 abar=~a;
assign # 1 bbar =~b;
assign # 2 z[0]=(abar & bbar & en);
assign # 2 z[1]=(abar & b & en);
assign # 2 z[2]=(a & bbar & en);
assign # 2 z[0]=(a & b & en);
endmodule

Behavioral Modeling:

module decoderbehv(a, b, en, z);

input a;
input b;
input en;
output [3:0] z;

reg [3:0] z;

always @ (a,b,en) begin

z[0] = ~ ((~a) & (~b) & en);

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 z[1] = ~ ((~a) & b & en);
z[2] = ~ (a & (~b) & en);
z[3] = ~ (a & b & en);

end
endmodule

Structural Modeling:

module decod_struct(a, b, e, z);

input a;
input b;
input e;
output [3:0] z;
wire abar,bbar;
not
n1(abar,a),
n2(bbar,b);
and
a1(z[0],abar,bbar,e),
a2(z[1],abar,b,e),
a3(z[2],a,bbar,e),
a4(z[3],a,b,e);
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT decoder_dataflow
PORT(
a : IN std_logic;
b : IN std_logic;
e : IN std_logic;
z : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL e : std_logic := '0';

--Outputs
SIGNAL z : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: decoder_dataflow PORT MAP(

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 a => a,
b => b,
e => e,
z => z
);

tb : PROCESS
BEGIN
a<='0';b<='0';e<='0'; wait for 100ps;
a<='0';b<='0';e<='1'; wait for 100ps;
a<='0';b<='1';e<='1'; wait for 100ps;
a<='1';b<='0';e<='1'; wait for 100ps;
a<='1';b<='1';e<='1'; wait for 100ps;
END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 2 out of 3584 0%

Number of 4 input LUTs: 4 out of 7168 0%
Number of bonded IOBs: 7 out of 97 7%

=========================================================================

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TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.858ns

RESULT:

Thus the OUTPUT’s of Encoder and Decoder are verified by synthesizing and simulating the VHDL and
VERILOG code.

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EXP NO: 04 DATE: 04-02-09

MULTIPLEXER AND DEMULTIPLEXER

AIM:
To develop the source code for multiplexer and demultiplexer by using VHDL/VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.

ALGORITM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

MULTIPLEXER:

LOGIC DIAGRAM:
TRUTH TABLE:
1
D0 2 9
8

SELECT INPUT OUTPUT

1
D1 2 9
8
2
3

4
1 Y S1 S0 Y
5

0 0 D0
1
D2 2 9
8

1
0 1 D1
D3 2 9

1 0 D2
8
2

1 1 D3
1

S1 S0

VHDL SOURCE CODE:

--Design : MULTIPLEXER
--Description : To implement MULTIPLEXER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_dataflow is
Port ( d : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_dataflow;
architecture dataflow of mux_dataflow is
signal s0bar,s1bar,p,q,r,st:std_logic;
begin
p<= d(0) and s0bar and s1bar;

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q<= d(1) and s0bar and s(1);
r<= d(2) and s(0) and s1bar;
st<= d(3) and s(0) and s(1);
s0bar<= not s(0);
s1bar<= not s(1);
y<= p or q or r or st;
end dataflow;

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_behv is
Port ( d : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_behv;
architecture Behavioral of mux_behv is
begin
p1:process(d,s)
begin
if (s(0)<='0' and s(1)<='0') then
y<=d(0);
elsif (s(0)<='0' and s(1)<='1') then
y<=d(1);
elsif (s(0)<='1' and s(1)<='0') then
y<=d(2);
else
y<=d(3);
end if;
end process p1;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_struct is
Port ( d : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_struct;
architecture structural of mux_struct is
component not1
port(a:in std_logic;
z:out std_logic);
end component;
component and3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
component or4
port(a,b,c,d:in std_logic;
z:out std_logic);
end component;
signal s0bar,s1bar,p,q,r,st:std_logic;

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begin
n1:not1 port map (s(0),s0bar);
n2:not1 port map (s(1),s1bar);
a1:and3 port map (d(0),s0bar,s1bar,p);
a2:and3 port map (d(1),s0bar,s(1),q);
a3:and3 port map (d(2),s(0),s1bar,r);
a4:and3 port map (d(3),s(0),s(1),st);
o1:or4 port map (p,q,r,st,y);
end structural;

and3 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and3 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
z : out std_logic);
end and3;
architecture dataflow of and3 is
begin
z<=a and b and c;
end dataflow;

not1 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is
begin
z<= not a;
end dataflow;

or4 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or4 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
z : out std_logic);
end or4;
architecture dataflow of or4 is
begin
z<=a or b or c or d;
end dataflow;

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VERILOG SOURCE CODE:

Dataflow Modeling:

module muxdataflow(s, i, y);

input [1:0] s;
input [3:0] i;
output y;
wire s2,s3,s4,s5,s6,s7;
assign s2 = ~s[1];
assign s3 = ~s[0];
assign s4 = i[0]&s2&s3;
assign s5 = i[1]&s2&s[0];
assign s6 = i[2]&s[1]&s3;
assign s7 = i[3]&s[1]&s[0];
assign y = s4 | s5 | s6 | s7;
endmodule

Behavioral Modeling:

module mux_behv(i, s0, s1, y);

input [3:0] i;
input s0;
input s1;
output y;
reg y;
always@(i or s0 or s1)
case({s1,s0})
2'd0:y=i[0];
2'd1:y=i[1];
2'd2:y=i[2];
2'd3:y=i[3];
default:$display("invalid control signals");
endcase
endmodule

Structural Modeling:

module mux_struct(i, s0, s1, y);

input [3:0] i;
input s0;
input s1;
output y;
wire s2,s3,s4,s5,s6,s7;
not
n1(s2,s1),
n2(s3,s0);
and
a1(s4,i[0],s2,s3),
a2(s5,i[1],s2,s0),
a3(s6,i[2],s1,s3),
a4(s7,i[3],s1,s0);
or
o1(y,s4,s5,s6,s7);
endmodule

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TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux_dataflow
PORT(
d : IN std_logic_vector(3 downto 0);
s : IN std_logic_vector(1 downto 0);
y : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL d : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');

--Outputs
SIGNAL y : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: mux_dataflow PORT MAP(
d => d,
s => s,
y => y
);

tb : PROCESS
BEGIN
d<="0101";s<="00"; wait for 100ps;
d<="0011";s<="01"; wait for 100ps;
d<="1110";s<="10"; wait for 100ps;
END PROCESS;
END;

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Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0%

Number of 4 input LUTs: 2 out of 7168 0%
Number of bonded IOBs: 7 out of 97 7%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:

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---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 8.138ns

DEMULTIPLEXER:

LOGIC DIAGRAM: `
TRUTH TABLE:
S1 S0

INPUT OUTPUT
D S0 S1 Y0 Y1 Y2 Y3
1 0 0 1 0 0 0
1

1 0 1 0 1 0 0
1 1 0 0 0 1 0
2

Din 2
3 1 1 1 0 0 0 1
1
4 Y0
5

2
3
1
4 Y1
5

2
3
1
4 Y2
5

2
3
1
4 Y3
5

Enable

VHDL SOURCE CODE:

--Design : DEMULTIPLEXER
--Description : To implement DEMULTIPLEXER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_dataflow is
Port ( d : in std_logic;
s : in std_logic_vector(1 downto 0);
z : out std_logic_vector(3 downto 0));
end demux_dataflow;
architecture dataflow of demux_dataflow is
signal s0bar,s1bar:std_logic;
begin
s0bar<= not s(0);

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s1bar<= not s(1);
z(0)<=d and s0bar and s1bar;
z(1)<=d and s0bar and s(1);
z(2)<=d and s(0) and s1bar;
z(3)<=d and s(0) and s(1);
end dataflow;

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_behv is
Port ( d : in std_logic;
s : in std_logic_vector(1 downto 0);
z : out std_logic_vector(3 downto 0));
end demux_behv;
architecture Behavioral of demux_behv is
begin
p1:process(d,s)
begin
if (s(0)<='0' and s(1)<='0') then
z(0)<=d;
z(1)<='Z';
z(2)<='Z';
z(3)<='Z';
elsif (s(0)<='0' and s(1)<='1') then
z(0)<='Z';
z(1)<=d;
z(2)<='Z';
z(3)<='Z';
elsif (s(0)<='1' and s(1)<='0') then
z(0)<='Z';
z(1)<='Z';
z(2)<=d;
z(3)<='Z';
else
z(0)<='Z';
z(1)<='Z';
z(2)<='Z';
z(3)<=d;
end if;
end process p1;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_struct is
Port ( d : in std_logic;
s : in std_logic_vector(1 downto 0);
z : out std_logic_vector(3 downto 0));
end demux_struct;
architecture structural of demux_struct is
component not1
port(a:in std_logic;

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 z:out std_logic);
end component;
component and3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
signal s0bar,s1bar:std_logic;
begin
n1:not1 port map (s(0),s0bar);
n2:not1 port map (s(1),s1bar);
a1:and3 port map (d,s0bar,s1bar,z(0));
a2:and3 port map (d,s0bar,s(1),z(1));
a3:and3 port map (d,s(0),s1bar,z(2));
a4:and3 port map (d,s(0),s(1),z(3));
end structural;

and3 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and3 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
z : out std_logic);
end and3;
architecture dataflow of and3 is
begin
z<=a and b and c;
end dataflow;

not1 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is
begin
z<= not a;
end dataflow;

VERILOG SOURCE CODE:

Dataflow Modeling:

module demuxdataflow(s0,s1,i,y);
input s0,s1,i;
output [3:0] y;
wire s2,s3;
assign #2 s2=~s0;
assign #2 s3=~s1;
assign #3 y[0]=i&s2&s3;
assign #3 y[1]=i&s2&s1;

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 assign #3 y[2]=i&s0&s3;
assign #3 y[3]=i&s0&s1;
endmodule

Behavioral Modeling:

module demux_behv(s0, s1, i, y);

input s0;
input s1;
input i;
output [3:0] y;
reg [3:0] y;
reg s2,s3;
always@(i or s0 or s1)
begin
s2=~s0;
s3=~s1;
y[0]=i & s2 & s3;
y[1]=i & s2 & s1;
y[2]=i & s0 & s3;
y[3]=i & s0 & s1;
end
endmodule

Structural Modeling:

module demux_struct(s0, s1, i, y);

input s0;
input s1;
input i;
output [3:0] y;
wire s2,s3;
not
n1(s2,s0),
n2(s3,s1);
and
a1(y[0],i,s2,s3),
a2(y[1],i,s2,s1),
a3(y[2],i,s0,s3),
a4(y[3],i,s0,s1);
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT demux_dataflow
PORT(
d : IN std_logic;
s : IN std_logic_vector(1 downto 0);
z : OUT std_logic_vector(3 downto 0)

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 );
END COMPONENT;

--Inputs
SIGNAL d : std_logic := '0';
SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');

--Outputs
SIGNAL z : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: demux_dataflow PORT MAP(
d => d,
s => s,
z => z
);

tb : PROCESS
BEGIN
d<='1'; s<="00"; wait for 100ps;
d<='0'; s<="01"; wait for 100ps;
d<='1'; s<="10"; wait for 100ps;
END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 2 out of 3584 0%

Number of 4 input LUTs: 4 out of 7168 0%
Number of bonded IOBs: 7 out of 97 7%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.858ns

RESULT:

Thus the OUTPUT’s of Multiplexers and Demultiplexers are verified by synthesizing and simulating the
VHDL and VERILOG code.

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EXP NO: 05 DATE: 06-02-09

DESIGN OF CODE CONVERTERS AND COMPARATOR

AIM:
To develop the source code for code converters and comparator by using VHDL/VERILOG and obtained
the simulation, synthesis, place and route and implement into FPGA.

ALGORITHM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

CODE CONVERTER (BCD TO GRAY):

LOGIC DIAGRAM:
TRUTH TABLE:

BCD GRAY
0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
VHDL SOURCE CODE:

--Design : BCD TO GRAY CONVERTER

--Description : To implement BCD TO GRAY CONVERTER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b2g_dataflow is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end b2g_dataflow;
architecture dataflow of b2g_dataflow is
begin
g(0)<=b(0) xor b(1);
g(1)<=b(1) xor b(2);

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g(2)<=b(2) xor b(3);
g(3)<=b(3);
end dataflow;

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b2g_behv is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end b2g_behv;
architecture Behavioral of b2g_behv is
begin
p1:process(b)
begin
g(3)<=b(3);
g(2)<=b(3) xor b(2);
g(1)<=b(2) xor b(1);
g(0)<=b(1) xor b(0);
end process p1;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b2g_struct is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end b2g_struct;
architecture structural of b2g_struct is
component xor2
port(a,b:in std_logic;
z:out std_logic);
end component;
component not1
port(a:in std_logic;
z:out std_logic);
end component;
signal p:std_logic;
begin
x1:xor2 port map (b(0),b(1),g(0));
x2:xor2 port map (b(1),b(2),g(1));
x3:xor2 port map (b(2),b(3),g(2));
n1:not1 port map (b(3),p);
n2:not1 port map (p,g(3));
end structural;

not1 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is

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 Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is
begin
z<= not a;
end dataflow;

xor2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;

VERILOG SOURCE CODE:

Dataflow Modeling:

module b2g_data(b, g);

input [3:0] b;
output [3:0] g;
assign#2 g[3]=b[3];
assign#2 g[2]=b[3]^b[2];
assign#3 g[1]=b[2]^b[1];
assign#3 g[0]=b[1]^b[0];
endmodule

Behavioral Modeling:

module b2g_behv(b, g);

input [3:0] b;
output [3:0] g;
reg [3:0] g;
always@(b) begin
g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule

Structural Modeling:

module b2gstructural(b, g);

input [3:0] b;
output [3:0] g;
xor
x1(g[0],b[0],b[1]),
x2(g[1],b[1],b[2]),

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 x3(g[2],b[2],b[3]);
and
a1(g[3],b[3]);
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT b2g_dataflow
PORT(
b : IN std_logic_vector(3 downto 0);
g : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL g : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: b2g_dataflow PORT MAP(
b => b,
g => g
);

tb : PROCESS
BEGIN
b<="0000"; wait for 100ps;
b<="0100"; wait for 100ps;
b<="1000"; wait for 100ps;
END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 2 out of 3584 0%

Number of 4 input LUTs: 3 out of 7168 0%
Number of bonded IOBs: 8 out of 97 8%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns

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CODE CONVERTER (BCD TO EXCESS 3):

LOGIC DIAGRAM
TRUTH TABLE:

BCD EXCESS 3
0000 0011
0001 0100
0010 0101
BCD EXCESS 3 0011 0110
0100 0111
0101 1000
0110 1001
VHDL SOURCE CODE: 0111 1010
1000 1011
--Design : BCD TO EXCESS 3 CONVERTER
--Description : To implement BCD TO EXCESS 1001 1100
3CONVERTER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Dataflow Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd2excess_data is
Port ( b : in std_logic_vector(3 downto 0);
e : out std_logic_vector(3 downto 0));
end bcd2excess_data;
architecture dataflow of bcd2excess_data is
signal b0bar,b1bar,b2bar,b3bar,p,q,r,s,t : std_logic;
begin
b0bar<=not b(0);
b1bar<=not b(1);
b2bar<=not b(2);
b3bar<=not b(3);
e(0)<= b0bar ;
e(1)<= b(0) xnor b(1);
p<=b1bar and b0bar;
q<=p and b(2);
r<= b(0) or b(1);
s<= r and b2bar;
e(2)<= q or s;
t<= r and b(2);
e(3)<= t or b(3);
end dataflow;

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd2excess_behv is

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 Port ( b : in std_logic_vector(3 downto 0);
e : out std_logic_vector(3 downto 0));
end bcd2excess_behv;
architecture Behavioral of bcd2excess_behv is
begin
process(b)
begin
e<=b+"0011";
end process;
end Behavioral;

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd2excess_struct is
Port ( b : in std_logic_vector(3 downto 0);
e : out std_logic_vector(3 downto 0));
end bcd2excess_struct;
architecture structural of bcd2excess_struct is
component not1 is
port(a:in std_logic;z:out std_logic);
end component;
component and2 is
port(a,b:in std_logic;z:out std_logic);
end component;
component or2 is
port(a,b:in std_logic;z:out std_logic);
end component;
component xnor2 is
port(a,b:in std_logic;z:out std_logic);
end component;
signal b0bar,b1bar,b2bar,b3bar,p,q,r,s,t:std_logic;
begin
n1:not1 port map(b(0),b0bar);
n2:not1 port map(b(1),b1bar);
n3:not1 port map(b(2),b2bar);
n4:not1 port map(b(3),b3bar);
e(0)<=b0bar;
x1:xnor2 port map (b(0),b(1),e(1));
a1:and2 port map (b0bar,b1bar,p);
a2:and2 port map (b(2),p,q);
o1:or2 port map(b(0),b(1),r);
a3:and2 port map(r,b2bar,s);
o2:or2 port map (q,s,e(2));
a4:and2 port map (r,b(2),t);
o3:or2 port map(b(3),t,e(3));
end structural;

VERILOG SOURCE CODE:

Dataflow Modeling:

module bcd2ex3_data(b, e);

input [3:0] b;
output [3:0] e;
wire s1,s2,s3,s4,s5,s6,s7;

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 assign#2 s1=~b[2];
assign#2 s2=~b[1];
assign#2 s3=~b[0];
assign#3 s4=b[1]|b[0];
assign#4 s5=b[1]&s2&s3;
assign#5 s6=s1&s4;
assign#5 s7=b[2]&s4;
assign#5 e[3]=b[3]|s7;
assign#5 e[2]=s5|s6;
assign#5 e[1]=b[0]^~b[1];
assign#6 e[0]=s3;
endmodule

Behavioral Modeling:

module bcd2ex3_behv(b, e);

input [3:0] b;
output [3:0] e;
reg [3:0] e;
reg s1,s2,s3,s4,s5,s6,s7;
always@(b) begin
s1=~b[2];
s2=~b[1];
s3=~b[0];
s4=b[1]|b[0];
s5=b[1]&s2&s3;
s6=s1&s4;
s7=b[2]&s4;
e[3]=b[3]|s7;
e[2]=s5|s6;
e[1]=b[0]^~b[1];
e[0]=s3;
end
endmodule

Structural Modeling:

module bcd2excessstructural(b, e);

input [3:0] b;
output [3:0] e;
wire s1,s2,s3,s4,s5,s6,s7;
not
n1(s1,b[2]),
n2(s2,b[1]),
n3(s3,b[0]);
or
o1(s4,b[1],b[0]),
o2(e[3],b[3],s7),
o3(e[2],s5,s6);
xor
x1(e[1],b[0],b[1]);
and
a1(s5,b[1],s2,s3),
a2(s6,s1,s4),
a3(s7,b[2],s4),
a4(e[0],s3);
endmodule

TEST BENCH(VHDL):

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT bcd2excess_behv
PORT(
b : IN std_logic_vector(3 downto 0);
e : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');

--Outputs
SIGNAL e : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: bcd2excess_behv PORT MAP(
b => b,
e => e
);

tb : PROCESS
BEGIN
b<="0000"; wait for 100ps;
b<="0101"; wait for 100ps;
b<="1000"; wait for 100ps;
END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-4

Number of Slices: 2 out of 3584 0%

Number of 4 input LUTs: 3 out of 7168 0%
Number of bonded IOBs: 8 out of 97 8%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.073ns

4 BIT COMPARATOR:

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LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : 4-BIT COMPARATOR

--Description : To implement 4-BIT COMPARATOR
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator_behv is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
x : out std_logic;
y : out std_logic;
z : out std_logic);
end comparator_behv;
architecture Behavioral of comparator_behv is
begin
p1:process(a,b)
begin
if (a<b) then
x<='1';
y<='0';
z<='0';
elsif (a=b) then
x<='0';
y<='1';
z<='0';
else
x<='0';
y<='0';
z<='1';
end if;
end process p1;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module comparatorbehvioral(a, b, x, y, z);

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 input [3:0] a;
input [3:0] b;
output x;
output y;
output z;
reg x,y,z;
always @ (a,b) begin
if(a==b)
begin
x=1'b1;
y=1'b0;
z=1'b0;
end
else if (a<b) begin
x=1'b0;
y=1'b1;
z=1'b0;
end
else
begin
x=1'b0;
y=1'b0;
z=1'b1;
end
end
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT comparator_behv
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
x : OUT std_logic;
y : OUT std_logic;
z : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL x : std_logic;
SIGNAL y : std_logic;
SIGNAL z : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comparator_behv PORT MAP(
a => a,

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 b => b,
x => x,
y => y,
z => z
);
tb : PROCESS
BEGIN
a<="0001";b<="1010"; wait for 100ps;
a<="1001";b<="0001"; wait for 100ps;
a<="1111";b<="1111"; wait for 100ps;
END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
========================================================================

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Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 5 out of 3584 0%

Number of 4 input LUTs: 9 out of 7168 0%
Number of bonded IOBs: 11 out of 97 11%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 10.635ns

RESULT:
Thus the OUTPUT’s of Code converters and comparator are verified by synthesizing and simulating the
VHDL and VERILOG code.

EXP NO: 06 DATE: 16-02-09

DESIGN OF FLIP FLOPS

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AIM:
To develop the source code for flip flops by using VHDL/VERILOG and Obtained the simulation,
synthesis, place and route and implement into FPGA.

ALGORITHM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

SR FLIPFLOP:

LOGIC DIAGRAM: TRUTH TABLE:

1
Q(t) S R Q(t+1)
S 3 1
2 3 0 0 0 0
2 Q
0 0 1 0
0 1 0 1
CP 0 1 1 X
1 0 0 1
1
1 3
1 0 1 0
3 2 Q 1 1 0 1
2
R 1 1 1 X

VHDL SOURCE CODE:

--Design : SR-FLIP FLOP

--Description : To implement SR-FLIP FLOP
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
Port ( s : in std_logic;
r : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end srff;
architecture Behavioral of srff is
begin
process(s,r,clk,rst,q,qbar)
begin

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if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (s='0' and r='0') then
q<=q;
qbar<=qbar;
elsif (s='0' and r='1') then
q<='0';
qbar<='1';
elsif (s='1' and r='0') then
q<='1';
qbar<='0';
else
q<='X';
qbar<='X';
end if;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module srflipflop(s, r, clk, rst, q, qbar);

input s;
input r;
input clk;
input rst;
output q;
output qbar;
reg q,qbar;
always @ (posedge(clk) or posedge(rst)) begin
if(rst==1'b1) begin
q= 1'b0;qbar= 1'b1;
end
else if(s==1'b0 && r==1'b0)
begin
q=q; qbar=qbar;
end
else if(s==1'b0 && r==1'b1)
begin
q= 1'b0; qbar= 1'b1;
end
else if(s==1'b1 && r==1'b0)
begin
q= 1'b1; qbar= 1'b0;
end
else
begin
q=1'bx;qbar=1'bx;
end
end
endmodule
TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

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USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT srff
PORT(
s : IN std_logic;
r : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL s : std_logic := '0';
SIGNAL r : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';

--BiDirs
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: srff PORT MAP(
s => s,
r => r,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);

tb : PROCESS
BEGIN
clk<='0'; wait for 50ps;
clk<='1'; wait for 50ps;
end process;
rst<='1','0' after 200ps;
tb1:process
begin
s<= '1' , '0' after 400ps;
r<= '1' , '0' after 300ps , '1' after 500ps;
wait for 1ns;
END PROCESS;

END;
Simulation output:

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Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : srff.ngr
Top Level Output File Name : srff
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

Design Statistics
# IOs :6

Macro Statistics :
# Registers :2
# 1-bit register :2

Cell Usage :
# BELS :3
# LUT2 :3
# FlipFlops/Latches :2
# FDCE :1
# FDPE :1
# Clock Buffers :1
# BUFGP :1

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# IO Buffers :5
# IBUF :3
# OBUF :2
=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 2 out of 3584 0%

Number of Slice Flip Flops: 2 out of 7168 0%
Number of 4 input LUTs: 3 out of 7168 0%
Number of bonded IOBs: 6 out of 97 6%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 3.529ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found

JK FLIPFLOP:

LOGIC DIAGRAM: TRUTH TABLE:

1
Q(t) J K Q(t+1)
K 2 9 1
8
2
3
Q 0 0 0 0
0 0 1 0
CP
0 1 0 1
0 1 1 1
1
1
3
1 0 0 1
J
2
8
9 2 Q 1 0 1 0
1 1 0 1
1 1 1 0

VHDL SOURCE CODE:

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 --Design : JK-FLIP FLOP
--Description : To implement JK-FLIP FLOP
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port ( j : in std_logic;
k : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end jkff;
architecture Behavioral of jkff is
begin
process(j,k,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (j='0' and k='0') then
q<=q;
qbar<=qbar;
elsif (j='0' and k='1') then
q<='0';
qbar<='1';
elsif (j='1' and k='0') then
q<='1';
qbar<='0';
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module jkff(j, k, clk, rst, q, qbar);

input j;
input k;
input clk;
input rst;
output q;
output qbar;
reg q;

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 reg qbar;
always @ (posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if (j==1'b0 && k==1'b0)
begin
q=q;
qbar=qbar;
end
else if (j==1'b0 && k==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if (j==1'b1 && k==1'b0)
begin
q=1'b1;
qbar=1'b0;
end
else
begin
q=~q;
qbar=~qbar;
end
end
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT jkff
PORT(
j : IN std_logic;
k : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL j : std_logic := '0';
SIGNAL k : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';

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 --BiDirs
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: jkff PORT MAP(
j => j,
k => k,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);

tb : PROCESS
BEGIN
clk<='0'; wait for 50ps;
clk<='1'; wait for 50ps;
end process;
rst<='1','0' after 200ps;
tb1:process
begin
j<= '1' , '0' after 400ps;
k<= '1' , '0' after 300ps , '1' after 500ps;
wait for 1ns;
END PROCESS;

END;

Simulation output:

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Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 2 out of 3584 0%

Number of Slice Flip Flops: 2 out of 7168 0%
Number of 4 input LUTs: 3 out of 7168 0%
Number of bonded IOBs: 6 out of 97 6%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+

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Timing Summary:
---------------
Speed Grade: -5

Minimum period: 2.085ns (Maximum Frequency: 479.513MHz)

Minimum input arrival time before clock: 3.529ns
Maximum output required time after clock: 6.280ns
Maximum combinational path delay: No path found

D FLIPFLOP:

LOGIC DIAGRAM: TRUTH TABLE:

1
D
2
3 1
3
Q
Q(t) D Q(t+1)
2
1

CP
0 0 0
1
0 1 1
1
3 2
3
Q 1 0 0
3

1 1 1

VHDL SOURCE CODE:

--Design : D-FLIP FLOP

--Description : To implement D-FLIP FLOP
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end dff;
architecture Behavioral of dff is
begin
process(d,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (d='0') then
q<='0';
qbar<='1';
else
q<='1';
qbar<='0';
end if;
end if;
end process;

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end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module dff(d, clk, rst, q, qbar);

input d;
input clk;
input rst;
output q;
output qbar;
reg q;
reg qbar;
always @ (posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
q=1'b0;
qbar=1'b1;
end
else if (d==1'b0)
begin
q=1'b0;
qbar=1'b1;
end
else
begin
q=1'b1;
qbar=1'b0;
end end endmodule
TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT dff
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';

--BiDirs
SIGNAL q : std_logic;

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 SIGNAL qbar : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: dff PORT MAP(
d => d,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);

tb : PROCESS
BEGIN
clk<='0'; wait for 50ps;
clk<='1'; wait for 50ps;
end process;
rst<='1','0' after 200ps;
tb1:process
begin
d<= '1' , '0' after 400ps;
wait for 1ns;
END PROCESS;

END;
Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *

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=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0%

Number of Slice Flip Flops: 2 out of 7168 0%
Number of bonded IOBs: 5 out of 97 5%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 2.796ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found

T FLIPFLOP:

LOGIC DIAGRAM: TRUTH TABLE:

Q(t) T Q(t+1)
1
T 2 9 1
8 3
2 Q
0 0 0
CP 0 1 1
1
1
3
1 0 1
2 9 2 Q
8
1 1 0

VHDL SOURCE CODE:

--Design : T-FLIP FLOP

--Description : To implement T-FLIP FLOP
--Author : AMRUTHA V

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 --Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end tff;
architecture Behavioral of tff is
begin
process(t,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (t='0') then
q<=q;
qbar<=qbar;
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;
VERILOG SOURCE CODE:

Behavioral Modeling:

module tff(t, clk, rst, q, qbar);

input t;
input clk;
input rst;
output q;
output qbar;
reg q,qbar;
always @ (posedge(clk) or posedge(rst)) begin
if(rst==1'b1) begin
q= 1'b0;qbar= 1'b1;
end
else if (t==1'b0)
begin
q=q; qbar=qbar;

end
else
begin
q=~q; qbar=~qbar;
end
end
endmodule

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TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT tff
PORT(
t : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL t : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';

--BiDirs
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: tff PORT MAP(
t => t,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);

tb : PROCESS
BEGIN
clk<='0'; wait for 50ps;
clk<='1'; wait for 50ps;
end process;
rst<='1','0' after 200ps;
tb1:process
begin
t<= '1','0' after 400ps;
wait for 1ns;
END PROCESS;

END;

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Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 1 out of 3584 0%

Number of Slice Flip Flops: 2 out of 7168 0%
Number of bonded IOBs: 5 out of 97 5%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

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------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 2.707ns (Maximum Frequency: 369.372MHz)

Minimum input arrival time before clock: 1.984ns
Maximum output required time after clock: 6.280ns
Maximum combinational path delay: No path found

MASTER-SLAVE SR FLIP-FLOP:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : MASTER SLAVE SR-FLIP FLOP

--Description : To implement MASTER SLAVE SR-FLIP FLOP
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sr_ms is
Port ( s : in std_logic;
r : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end sr_ms;

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architecture structural of sr_ms is
component srff
Port ( s : in std_logic;
r : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end component;
component not1
port(a:in std_logic;
z:out std_logic);
end component;
signal clkbar,s1,r1:std_logic;
begin
n1:not1 port map (clk,clkbar);
sr1:srff port map (s,r,clk,rst,s1,r1);
sr2:srff port map (s1,r1,clkbar,rst,q,qbar);
end structural;

srff component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
Port ( s : in std_logic;
r : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end srff;
architecture Behavioral of srff is
begin
process(s,r,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (s='0' and r='0') then
q<=q;
qbar<=qbar;
elsif (s='0' and r='1') then
q<='0';
qbar<='1';
elsif (s='1' and r='0') then
q<='1';
qbar<='0';
else
q<='X';
qbar<='X';
end if;
end if;
end process;
end Behavioral;

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VERILOG SOURCE CODE:

Structurl modeling:

module srff_ms(s, r, clk, rst, q, qbar);

input s;
input r;
input clk;
input rst;
output q;
output qbar;
wire s1,r1;
srflipflop
sr1(s,r,clk,rst,s1,r1),
sr2(s1,r1,~clk,rst,q,qbar);
endmodule

srflipflop component source code:

module srflipflop(s, r, clk, rst, q, qbar);

input s;
input r;
input clk;
input rst;
output q;
output qbar;
reg q,qbar;
always @ (posedge(clk) or posedge(rst)) begin
if(rst==1'b1) begin
q= 1'b0;qbar= 1'b1;
end
else if(s==1'b0 && r==1'b0)
begin
q=q; qbar=qbar;
end
else if(s==1'b0 && r==1'b1)
begin
q= 1'b0; qbar= 1'b1;
end
else if(s==1'b1 && r==1'b0)
begin
q= 1'b1; qbar= 1'b0;
end
else
begin
q=1'bx;qbar=1'bx;
end
end
endmodule

TEST BENCH (VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

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ARCHITECTURE behavior OF test_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sr_ms
PORT(
s : IN std_logic;
r : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL s : std_logic := '0';
SIGNAL r : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--BiDirs
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sr_ms PORT MAP(
s => s,
r => r,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);
tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 200ps;
s<='1','0' after 400ps;
r<='1','0' after 300ps,'1' after 500ps;
END;

Simulation output:

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Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 3 out of 3584 0%

Number of Slice Flip Flops: 4 out of 7168 0%
Number of 4 input LUTs: 6 out of 7168 0%
Number of bonded IOBs: 6 out of 97 6%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

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 FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 6.881ns (Maximum Frequency: 145.332MHz)

Minimum input arrival time before clock: 3.529ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found

RESULT:
Thus the OUTPUT’s of Flip Flops are verified by synthesizing and simulating the VHDL and VERILOG
code.

EXP NO: 07 DATE: 20-02-09

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 DESIGN OF REGISTER USING LATCHES AND FLIP FLOPS
AIM:
To develop the source code for register and latches using flip-flops by using VHDL/VERILOG and
Obtained the simulation, synthesis, place and route and implement into FPGA.

ALGORITHM:

STEP 1: Define the specification and initialize the design.

STEP 2: Declare the name of the entity and architecture by using VHDL source code.
STEP 3: Write the source code in VERILOG.
STEP 4: Check the syntax and debug the error is found. Obtain the synthesis report.
STEP 5: Verify the output by simulating the source code.
STEP 6: Write the all-possible combination of input using the test bench.
STEP 7: Obtain the place and route report.

REGISTER USING FLIP FLOPS:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : REGISTER USING FLIP FLOPS

--Description : To implement REGISTER USING FLIP FLOPS
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reguff is
Port ( d : in std_logic_vector(7 downto 0);
clk : in std_logic;
rst : in std_logic;
q : inout std_logic_vector(7 downto 0);
qbar : inout std_logic_vector(7 downto 0));
end reguff;
architecture Behavioral of reguff is
begin
process(d,clk,rst)
begin
if (clk='1' and clk'event) then
if (rst='1') then
q<="00000000";
qbar<="11111111";
else

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q<=d;
qbar<=not d;
end if;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module register1(d, clk, rst, q, qbar);

input [7:0]d;
input clk;
input rst;
output [7:0]q;
output [7:0]qbar;
reg [7:0]q;
reg [7:0]qbar;
always @( posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
q=8'b0;
qbar=8'b11111111;
end
else
begin
q=d;
qbar=~d;
end
end
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT reguff
PORT(
d : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic_vector(7 downto 0);
qbar : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;

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 --Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');

--BiDirs
SIGNAL q : std_logic_vector(7 downto 0);
SIGNAL qbar : std_logic_vector(7 downto 0);
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: reguff PORT MAP(
d => d,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);

tb : PROCESS
BEGIN
clk <='0'; wait for 50 ps;
clk <='1'; wait for 50 ps;
END PROCESS;
rst <='1','0' after 200 ps;
d<="00010001","00001111" after 400 ps,"11110000" after 600 ps,"11111111" after 800 ps;
END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 9 out of 3584 0%

Number of Slice Flip Flops: 16 out of 7168 0%
Number of bonded IOBs: 26 out of 97 26%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 16 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 2.796ns

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 Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found

REGISTER USING LATCHES:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : REGISTER USING LATCHES

--Description : To implement REGISTER USING LATCHES
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity regulat is
Port ( d : in std_logic_vector(7 downto 0);
rst : in std_logic;
en : in std_logic;
q : inout std_logic_vector(7 downto 0);
qbar : inout std_logic_vector(7 downto 0));
end regulat;
architecture Behavioral of regulat is
begin
process(d,rst,en)
begin
if (rst='1') then
q<="00000000";
qbar<="11111111";
elsif (en='1') then
q<=d;
qbar<=not d;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

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module latch1(d, rst, en, q, qbar);
input [7:0]d;
input rst;
input en;
output [7:0]q;
output [7:0]qbar;
reg [7:0]q;
reg [7:0]qbar;
always @ (en or rst) begin
if (rst==1'b1)
begin
q=8'b0;
qbar=8'b11111111;
end
else if (en==1'b1)
begin
q=d;
qbar=~d;
end
end
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT regulat
PORT(
d : IN std_logic_vector(7 downto 0);
rst : IN std_logic;
en : IN std_logic;
q : INOUT std_logic_vector(7 downto 0);
qbar : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL rst : std_logic := '0';
SIGNAL en : std_logic := '0';
SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');

--BiDirs
SIGNAL q : std_logic_vector(7 downto 0);
SIGNAL qbar : std_logic_vector(7 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: regulat PORT MAP(

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 d => d,
rst => rst,
en => en,
q => q,
qbar => qbar
);

tb : PROCESS
BEGIN
wait for 1 ns;
END PROCESS;
en<='1','0' after 200 ps, '1' after 300 ps, '0' after 400 ps;
rst<='1','0' after 100 ps;
d<="01010101","11110000" after 100 ps,"11111111" after 200 ps,"00001111" after 300 ps;
END;

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:

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---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 9 out of 3584 0%

Number of Slice Flip Flops: 16 out of 7168 0%
Number of bonded IOBs: 26 out of 97 26%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
en | BUFGP | 16 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 2.796ns
Maximum output required time after clock: 6.141ns
Maximum combinational path delay: No path found

RESULT:

Thus the OUTPUT’s of 8-bit register using flip flops and latches are verified by synthesizing and
simulating the VHDL and VERILOG code.

EXP NO: 08 DATE: 24-02-09

DESIGN OF SHIFT REGISTERS

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AIM:
To develop the source code for shift registers unit by using VHDL/VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.

ALGORITM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

SERIAL-IN SERIAL-OUT SHIFT REGISTER:

LOGIC DIAGRAM :

VHDL SOURCE CODE:

--Design : SISO SHIFT REGISTER

--Description : To implement SISO SHIFT REGISTER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity siso is
Port ( d : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end siso;
architecture Behavioral of siso is
signal x:std_logic_vector(7 downto 0);
begin
process(d,clk,rst)
begin
if (rst='1') then
q<='X';
elsif (clk='1' and clk'event) then
x(0)<=d;
x(1)<=x(0);
x(2)<=x(1);
x(3)<=x(2);

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x(4)<=x(3);
x(5)<=x(4);
x(6)<=x(5);
x(7)<=x(6);
q<=x(7);
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module siso(din, clk, rst, dout);

input din;
input clk;
input rst;
output dout;
reg dout;
reg [7:0]x;
always @ (posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
dout=8'hzz;
end
else
begin
x={x[6:0],din};
dout=x[7];
end
end
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT siso
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--Outputs

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 SIGNAL q : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: siso PORT MAP(
d => d,
clk => clk,
rst => rst,
q => q
);

tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 200ps;
d<='1','0' after 1 ns;
END;

Simulation output:

Synthesis RTL Schematic:

Synthesis Report
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : siso.ngr
Top Level Output File Name : siso
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

Design Statistics
# IOs :4

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Macro Statistics :
# Registers :1
# 1-bit register :1
# Shift Registers :1
# 8-bit shift register :1

Cell Usage :
# BELS :3
# GND :1
# INV :1
# VCC :1
# FlipFlops/Latches :2
# FD :1
# FDE :1
# Shifters :1
# SRL16E :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers :3
# IBUF :2
# OBUF :1
=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s400pq208-5

Number of Slices: 1 out of 3584 0%

Number of Slice Flip Flops: 2 out of 7168 0%
Number of 4 input LUTs: 1 out of 7168 0%
Number of bonded IOBs: 4 out of 141 2%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |3 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 3.637ns (Maximum Frequency: 274.963MHz)

Minimum input arrival time before clock: 3.144ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found

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Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 3.637ns (frequency: 274.963MHz)
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay: 3.637ns (Levels of Logic = 0)
Source: Mshreg_x<7>_srl_0 (FF)
Destination: Mshreg_x<7>_0 (FF)
Source Clock: clk rising
Destination Clock: clk rising

Data Path: Mshreg_x<7>_srl_0 to Mshreg_x<7>_0

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
SRL16E:CLK->Q 1 2.780 0.681 Mshreg_x<7>_srl_0 (Mshreg_x<7>__net0)
FDE:D 0.176 Mshreg_x<7>_0
----------------------------------------
Total 3.637ns (2.956ns logic, 0.681ns route)
(81.3% logic, 18.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset: 3.144ns (Levels of Logic = 2)
Source: rst (PAD)
Destination: Mshreg_x<7>_0 (FF)
Destination Clock: clk rising

Data Path: rst to Mshreg_x<7>_0

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.715 0.681 rst_IBUF (rst_IBUF)
INV:I->O 2 0.479 0.745 Mshreg_x<7>_inst_inv_01_INV_0 (Mshreg_x<7>_inst_inv_0)
FDE:CE 0.524 Mshreg_x<7>_0
----------------------------------------
Total 3.144ns (1.718ns logic, 1.426ns route)
(54.6% logic, 45.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 6.216ns (Levels of Logic = 1)
Source: q (FF)
Destination: q (PAD)
Source Clock: clk rising

Data Path: q to q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.626 0.681 q (q_OBUF)
OBUF:I->O 4.909 q_OBUF (q)

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 ----------------------------------------
Total 6.216ns (5.535ns logic, 0.681ns route)
(89.0% logic, 11.0% route)

=========================================================================
CPU : 6.88 / 7.56 s | Elapsed : 7.00 / 8.00 s

-->

Total memory usage is 100732 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

Place&Route Report

Constraints file: siso.pcf.

Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
"siso" is an NCD, version 3.1, device xc3s400, package pq208, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000

Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

Device speed data version: "ADVANCED 1.35 2005-01-22".

Device Utilization Summary:

Number of BUFGMUXs 1 out of 8 12%

Number of External IOBs 4 out of 141 2%
Number of LOCed IOBs 0 out of 4 0%

Overall effort level (-ol): Standard (set by user)

Placer effort level (-pl): Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): Standard (set by user)

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 3 secs

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs

Phase 3.2
.

Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 3 secs

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Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 3 secs

Phase 6.8
.
Phase 6.8 (Checksum:989b6b) REAL time: 3 secs

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secs

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 3 secs

Writing design to file siso.ncd

Total REAL time to Placer completion: 3 secs

Total CPU time to Placer completion: 2 secs

Starting Router

Phase 1: 12 unrouted; REAL time: 3 secs

Phase 2: 9 unrouted; REAL time: 3 secs

Phase 3: 0 unrouted; REAL time: 3 secs

Phase 4: 0 unrouted; REAL time: 3 secs

Total REAL time to Router completion: 3 secs

Total CPU time to Router completion: 2 secs

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX6| No | 2 | 0.035 | 0.936 |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 -
The Delay report will not be generated when running non-timing driven PAR
with effort level Standard or Medium. If a delay report is required please do
one of the following: 1) use effort level High, 2) use the following
environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs

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Total CPU time to PAR completion: 2 secs

Peak Memory Usage: 76 MB

Placement: Completed - No errors found.

Routing: Completed - No errors found.

Number of error messages: 0

Number of warning messages: 0
Number of info messages: 1

Writing design to file siso.ncd

PAR done!

SERIAL IN PARALLEL OUT SHIFT REGISTER:

LOGIC DIAGRAM :

VHDL SOURCE CODE:

--Design : SIPO SHIFT REGISTER

--Description : To implement SIPO SHIFT REGISTER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sipo is
Port ( d : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic_vector(7 downto 0));
end sipo;
architecture Behavioral of sipo is
begin
process(d,clk,rst)
begin
if (rst='1') then

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q<="ZZZZZZZZ";
elsif (clk='1' and clk'event) then
q(0)<=d;
q(1)<=q(0);
q(2)<=q(1);
q(3)<=q(2);
q(4)<=q(3);
q(5)<=q(4);
q(6)<=q(5);
q(7)<=q(6);
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module sipo(din, clk, rst, dout);

input din;
input clk;
input rst;
output [7:0] dout;
reg[7:0]dout;
reg[7:0]x;
always @ (posedge(clk) or posedge(rst))
begin
if(rst)
dout=8'hzz;
else
begin
x={x[6:0],din};
dout=x;
end
end
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sipo
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';

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 SIGNAL rst : std_logic := '0';
--BiDirs
SIGNAL q : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sipo PORT MAP(
d => d,
clk => clk,
rst => rst,
q => q
);
tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 200ps;
d<='1','0' after 1ns;
END;

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================

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* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 5 out of 3584 0%

Number of Slice Flip Flops: 8 out of 7168 0%
Number of bonded IOBs: 11 out of 97 11%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |8 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 1.572ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: 6.756ns

PARALLEL-IN PARELLEL-OUT SHIFT REGISTER:

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LOGIC DIAGRAM :

VHDL SOURCE CODE:

--Design : PIPO SHIFT REGISTER

--Description : To implement PIPO SHIFT REGISTER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pipo is
Port ( d : in std_logic_vector(7 downto 0);
clk : in std_logic;
rst : in std_logic;
q : out std_logic_vector(7 downto 0));
end pipo;
architecture Behavioral of pipo is
begin
process(d,clk,rst)
begin
if (rst='1') then
q<="ZZZZZZZZ";
elsif (clk='1' and clk'event) then
q(0)<=d(0);
q(1)<=d(1);
q(2)<=d(2);
q(3)<=d(3);
q(4)<=d(4);
q(5)<=d(5);
q(6)<=d(6);
q(7)<=d(7);
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

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Behavioral Modeling:

module pipo(clk, rst, din, dout);

input clk;
input rst;
input [7:0] din;
output [7:0] dout;
reg [7:0] dout;
always @ (posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
dout=8'hzz;
end
else
begin
dout=din;
end
end
endmodule
TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT pipo
PORT(
d : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL q : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pipo PORT MAP(
d => d,
clk => clk,
rst => rst,
q => q
);
tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 200ps;

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 d<="10101100","11110001" after 400ps;
END;

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 5 out of 3584 0%

Number of Slice Flip Flops: 8 out of 7168 0%
Number of bonded IOBs: 18 out of 97 18%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |

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-----------------------------------+------------------------+-------+
clk | BUFGP |8 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 1.572ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: 6.756ns

PARALLEL-IN SERIAL-OUT SHIFT REGISTER:

LOGIC DIAGRAM :

VHDL SOURCE CODE:

--Design : PISO SHIFT REGISTER

--Description : To implement PISO SHIFT REGISTER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity piso is
Port ( d : in std_logic_vector(7 downto 0);
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
q : out std_logic);
end piso;
architecture Behavioral of piso is
begin
process(d,clk,rst,load)
variable x:std_logic_vector(7 downto 0);
begin
if (clk='1' and clk'event) then
if (rst='1') then
q<='Z';
else
if (load='0') then

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x:=d;
else
q<=x(0);
x(0):=x(1);
x(1):=x(2);
x(2):=x(3);
x(3):=x(4);
x(4):=x(5);
x(5):=x(6);
x(6):=x(7);
x(7):='Z';
end if;
end if;
end if;
end process;
end Behavioral;
VERILOG SOURCE CODE:

Behavioral Modeling:

module piso(din, clk, rst, load, dout);

input [7:0] din;
input clk;
input rst;
input load;
output dout;
reg dout;
reg [8:0]x;
always @(posedge(clk) or posedge(rst)) begin
if (rst==1'b1)
begin
dout=1'bz;
end
else
begin
if (load==1'b0)
begin
x=din;
end
else
x={x[7:0],1'hz};
dout=x[8];
end
end
endmodule

TEST BENCH(VHDL):

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT piso
PORT(
d : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
rst : IN std_logic;
load : IN std_logic;
q : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL load : std_logic := '0';
SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');

--Outputs
SIGNAL q : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: piso PORT MAP(
d => d,
clk => clk,
rst => rst,
load => load,
q => q
);
tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 200ps;
load<='0','1' after 400ps;
d<="10100011","11110000" after 1400ps;
END;

Simulation output:

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Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 6 out of 3584 0%

Number of Slice Flip Flops: 11 out of 7168 0%
Number of 4 input LUTs: 8 out of 7168 0%
Number of bonded IOBs: 12 out of 97 12%
Number of GCLKs: 1 out of 8 12%

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=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 11 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 2.021ns (Maximum Frequency: 494.841MHz)

Minimum input arrival time before clock: 3.658ns
Maximum output required time after clock: 6.427ns
Maximum combinational path delay: No path found

RESULT:
Thus the OUTPUT’s of 8-bit shift register are verified by synthesizing and simulating the VHDL and
VERILOG code.

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EXP NO: 09 DATE: 04-03-09

SYNCHRONOUS AND ASYNCHRONOUS COUNTER

AIM:
To develop the source code for synchronous and asynchronous counter by using VHDL/VERILOG and
obtain the simulation, synthesis, place and route and implement into FPGA.

ALGORITM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

SYNCHRONOUS COUNTER:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : SYNCHRONOUS COUNTER

--Description : To implement SYNCHRONOUS COUNTER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity syncounter is
Port ( clk : in std_logic;
rst : in std_logic;
q : inout std_logic_vector(3 downto 0));
end syncounter;
architecture structural of syncounter is
component tff
port(t,clk,rst:in std_logic;
q,qbar:inout std_logic);
end component;
component and2

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port(a,b:in std_logic;
z:out std_logic);
end component;
signal x1,x2:std_logic;
signal x3,x4,x5,x6:std_logic:='Z';
begin
t1:tff port map ('1',clk,rst,q(0),x3);
t2:tff port map (q(0),clk,rst,q(1),x4);
t3:tff port map (x1,clk,rst,q(2),x5);
t4:tff port map (x2,clk,rst,q(3),x6);
a1:and2 port map (q(0),q(1),x1);
a2:and2 port map (x1,q(2),x2);
end structural;

tff component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end tff;
architecture Behavioral of tff is
begin
process(t,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (t='0') then
q<=q;
qbar<=qbar;
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;

and2 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is
begin
z<=a and b;

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end dataflow;

VERILOG SOURCE CODE:

Behavioral Modeling:

module syncntr(clk, rst, q);

input clk;
input rst;
output [3:0]q;
reg [3:0]q;
reg [3:0]x=0;
always @ (posedge(clk) or posedge(rst))
begin
if (rst==1'b1)
begin
q=4'b0;
end
else
begin
x=x+1'b1;
end
q=x;
end
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT syncounter
PORT(
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';

--BiDirs
SIGNAL q : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: syncounter PORT MAP(
clk => clk,
rst => rst,

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 q => q
);

tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 100ps;
END;

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 2 out of 3584 0%

Number of Slice Flip Flops: 4 out of 7168 0%
Number of 4 input LUTs: 2 out of 7168 0%
Number of bonded IOBs: 6 out of 97 6%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 3.388ns (Maximum Frequency: 295.186MHz)

Minimum input arrival time before clock: No path found
Maximum output required time after clock: 6.318ns
Maximum combinational path delay: No path found

ASYNCHRONOUS COUNTER:

LOGIC DIAGRAM:

VHDL SOURCE CODE:

--Design : ASYNCHRONOUS COUNTER

--Description : To implement ASYNCHRONOUS COUNTER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity asyncounter is
Port ( clk : in std_logic;
rst : in std_logic;
q : inout std_logic_vector(3 downto 0));

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end asyncounter;
architecture structural of asyncounter is
component tff
port(t,clk,rst:in std_logic;
q,qbar:inout std_logic);
end component;
signal x1,x2,x3:std_logic;
signal x4:std_logic:='Z';
begin
t1:tff port map ('1',clk,rst,q(0),x1);
t2:tff port map ('1',x1,rst,q(1),x2);
t3:tff port map ('1',x2,rst,q(2),x3);
t4:tff port map ('1',x3,rst,q(3),x4);
end structural;

tff component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end tff;
architecture Behavioral of tff is
begin
process(t,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (t='0') then
q<=q;
qbar<=qbar;
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module asyncntr(clk, rst, s, q);

input clk;
input rst;
input s;
output [3:0] q;
reg [3:0] q;
reg [3:0] x=0;
always @ (posedge(clk) or posedge(rst))
begin

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 if (rst==1'b1)
begin
q=4'b0;
end
else if (s==1'b0)
begin
x=x-1'b1;
end
else if (s==1'b1)
begin
x=x+1'b1;
end
q=x;
end
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT asyncounter
PORT(
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';

--BiDirs
SIGNAL q : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: asyncounter PORT MAP(
clk => clk,
rst => rst,
q => q
);

tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 100ps;
END;

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Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 4 out of 3584 0%

Number of Slice Flip Flops: 7 out of 7168 0%
Number of bonded IOBs: 6 out of 97 6%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |

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-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
t1/qbar:Q | NONE |2 |
t2/qbar:Q | NONE |2 |
t3/qbar:Q | NONE |1 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR
resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent
skew problems.

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 2.733ns (Maximum Frequency: 365.925MHz)

Minimum input arrival time before clock: No path found
Maximum output required time after clock: 6.280ns
Maximum combinational path delay: No path found

RESULT:
Thus the OUTPUT’s of Synchronous and Asynchronous counter are verified by synthesizing and
simulating the VHDL and VERILOG code.

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EXP NO: 10 DATE: 10-03-09

DESIGN OF MOORE AND MEALY FSM

AIM:
To develop the source code for moore and melay FSM by using VHDL/VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.

ALGORITM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

MOORE FSM:

LOGIC DIAGRAM:

VHDL SOURCE CODE

--Design : MOORE FSM
--Description : To implement MOORE FSM
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity moorefsm is
Port ( a : in std_logic;
clk : in std_logic;
z : out std_logic);
end moorefsm;
architecture Behavioral of moorefsm is
type state_type is (st0,st1,st2,st3);
signal moore_state:state_type;
begin
process(clk)
begin
if (clk='0') then
case moore_state is

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when st0=>
z<='1';
if (a='1') then
moore_state<=st2;
end if;

when st1=>
z<='0';
if (a='1') then
moore_state<=st3;
end if;

when st2=>
z<='0';
if (a='0') then
moore_state<=st1;
else
moore_state<=st3;
end if;

when st3=>
z<='1';
if (a='1') then
moore_state<=st0;
end if;

end case;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module moorefsm(a,clk,z);
input a;
input clk;
output z;
reg z;

parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]moore_state;
initial
begin
moore_state=st0;
end
always @ (posedge(clk))
case(moore_state)
st0:
begin
z=1;
if(a)
moore_state=st2;
end

st1:
begin
z=0;
if(a)

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 moore_state=st3;
end

st2:
begin
z=0;
if(~a)
moore_state=st1;
else
moore_state=st3;
end

st3:
begin
z=1;
if(a)
moore_state=st0;
end
endcase
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT moorefsm
PORT(
a : IN std_logic;
clk : IN std_logic;
z : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL clk : std_logic := '0';
--Outputs
SIGNAL z : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: moorefsm PORT MAP(
a => a,
clk => clk,
z => z
);

tb : PROCESS
BEGIN
clk<='1'; wait for 50 ps;
clk<='0'; wait for 50 ps;
END PROCESS;
a<='1','0' after 1 ns;

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END;

Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 3 out of 3584 0%

Number of Slice Flip Flops: 5 out of 7168 0%
Number of 4 input LUTs: 5 out of 7168 0%
Number of bonded IOBs: 3 out of 97 3%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------

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-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |5 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 2.910ns (Maximum Frequency: 343.648MHz)

Minimum input arrival time before clock: 2.444ns
Maximum output required time after clock: 6.141ns
Maximum combinational path delay: No path found

MEALY FSM:

TRUTH TABLE:

VHDL SOURCE CODE

--Design : MEALY FSM
--Description : To implement MEALY FSM
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mealyfsm is
Port ( a : in std_logic;
clk : in std_logic;
z : out std_logic);
end mealyfsm;
architecture Behavioral of mealyfsm is
type mealy_type is (st0,st1,st2,st3);
signal pst,nst:mealy_type;
begin
process(clk)
begin
if (clk='0') then
pst<=nst;

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end if;
end process;
p1:process(pst,a)
begin
case pst is

when st0=>
if (a='1') then
z<='1';
nst<=st3;
else
z<='0';
end if;

when st1=>
if (a='1') then
z<='0';
nst<=st0;
else
z<='1';
end if;

when st2=>
if (a='1') then
z<='1';
nst<=st1;
else
z<='0';
end if;

when st3=>
z<='0';
if (a='0') then
nst<=st2;
else
nst<=st1;
end if;

end case;
end process p1;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module mealayfsm(a, clk, z);

input a;
input clk;
output z;
reg z;

parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]mealy_state;
initial
begin
mealy_state=st0;
end
always @ (posedge(clk))
case(mealy_state)

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 st0:
begin
if(a) begin
z=1;
mealy_state=st3; end
else
z=0;
end

st1:
begin
if(a) begin
z=0;
mealy_state=st0; end
else
z=1;
end

st2:
begin
if(a) begin
z=1;
mealy_state=st1; end
else
z=0;
end

st3:
begin
z=0;
if(a) begin
mealy_state=st1; end
else
mealy_state=st2;
end

endcase
endmodule

TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mealyfsm
PORT(
a : IN std_logic;
clk : IN std_logic;
z : OUT std_logic
);
END COMPONENT;
--Inputs

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 SIGNAL a : std_logic := '0';
SIGNAL clk : std_logic := '0';
--Outputs
SIGNAL z : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: mealyfsm PORT MAP(
a => a,
clk => clk,
z => z
);

tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
a<='1','0' after 1ns;
END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 5 out of 3584 0%

Number of Slice Flip Flops: 8 out of 7168 0%
Number of 4 input LUTs: 6 out of 7168 0%
Number of bonded IOBs: 3 out of 97 3%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
_n0009(_n00091:O) | NONE(*)(nst_3) |4 |
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR
resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent
skew problems.

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 2.518ns
Maximum output required time after clock: 7.561ns
Maximum combinational path delay: 7.931ns

RESULT:
Thus the OUTPUT’s of Moore and Mealy fsm are verified by synthesizing and simulating the VHDL and
VERILOG code.

EXP NO: 11 DATE: 16-03-09

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 STATIC AND ROLLING DISPLAY
AIM:
To develop the source code Static and Rolling Display by using VHDL/VERILOG and Obtained the
simulation, synthesis, place and route and implement into FPGA.

ALGORITHM:

STEP 1: Define the specification and initialize the design.

STEP 2: Declare the name of the entity and architecture by using VHDL source code.
STEP 3: Write the source code in VERILOG.
STEP 4: Check the syntax and debug the error is found. Obtain the synthesis report.
STEP 5: Verify the output by simulating the source code.
STEP 6: Write the all-possible combination of input using the test bench.
STEP 7: Obtain the place and route report.

VHDL SOURCE CODE

--Design : STATIC AND ROLLING DISPLAY

--Description : To implement STATIC AND ROLLING DISPLAY
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity static_rolling is
Port ( clk : in std_logic;
rst : in std_logic;
a1,a2,a3 : in std_logic_vector(7 downto 0);
stat_roll : in std_logic;
a_out : out std_logic_vector(23 downto 0));
end static_rolling;
architecture Behavioral of static_rolling is
signal count:integer;
begin
process(clk,rst,a1,a2,a3,count)
begin
if(clk='1' and clk'event) then
if(rst='1')then
a_out<=(others=>'0');
count<=0;
else
if(stat_roll='0')then
a_out<=a1 & a2 & a3;
else
count<=count+1;
if(count=3)then
count<=0;
end if;
case count is
when 0=>a_out<=a1&a2&a3;
when 1=>a_out<=a2&a3&a1;
when 2=>a_out<=a3&a1&a2;

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 when others=>null;
end case;
end if;
end if;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module stat_rolling(a_out, clk, rst, a_in1, a_in2, a_in3, stat_roll);

output [23:0] a_out;
input clk;
input rst;
input [7:0] a_in1;
input [7:0] a_in2;
input [7:0] a_in3;
input stat_roll;
reg [23:0] a_out;
reg x;
integer count=0;
always@(posedge(clk) or posedge(rst))
begin
if(rst)
begin
a_out=32'd0;
x=1'b0;
end
else
begin
if(stat_roll)
begin
if(x==1'b0)
a_out={a_in1,a_in2,a_in3};
else
a_out=a_out;
end
else
begin
x=1'b1;
count=count+1;
if(count==3)
count=0;
case(count)
0:a_out={a_in1,a_in2,a_in3};
1:a_out={a_in3,a_in1,a_in2};
2:a_out={a_in2,a_in3,a_in1};
default:a_out={a_in1,a_in2,a_in3};
endcase
end
end
end
endmodule

TEST BENCH(VERILOG):

module static_test_v;

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 // Inputs
reg clk;
reg rst;
reg [7:0] a_in1;
reg [7:0] a_in2;
reg [7:0] a_in3;
reg stat_roll;

// OUTPUT:s
wire [23:0] a_out;

// Instantiate the Unit Under Test (UUT)

stat_rolling uut (
.a_out(a_out),
.clk(clk),
.rst(rst),
.a_in1(a_in1),
.a_in2(a_in2),
.a_in3(a_in3),
.stat_roll(stat_roll)
);
always
#5 clk=~clk;

initial
begin
// Initialize Inputs
clk = 1'b0;rst=1'b1;a_in1=8'haa;a_in2=8'hff;a_in3=8'h00;stat_roll=1'b1;
#15 rst = 1'b0;
#25 stat_roll = 1'b0;
#20 stat_roll = 1'b1;
#15 stat_roll = 1'b0;
// Wait 100 ns for global reset to finish

// Add stimulus here

end

endmodule

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 66 out of 3584 1%

Number of Slice Flip Flops: 58 out of 7168 0%
Number of 4 input LUTs: 104 out of 7168 1%
Number of bonded IOBs: 51 out of 97 52%
Number of GCLKs: 1 out of 8 12%
=========================================================================
TIMING REPORT

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 58 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 10.080ns (Maximum Frequency: 99.205MHz)

Minimum input arrival time before clock: 5.139ns
Maximum OUTPUT: required time after clock: 6.216ns
Maximum combinational path delay: No path found

RESULT:
Thus the OUTPUT’s of Static and Rolling display are verified by synthesizing and simulating the VHDL
and VERILOG code.
EXP NO: 12 DATE: 18-03-09

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 FREQUENCY DIVIDER
AIM:
To develop the source code Frequency divider and multiplier by using VHDL/VERILOG and Obtained the
simulation, synthesis, place and route and implement into FPGA.

ALGORITHM:

STEP 1: Define the specification and initialize the design.

STEP 2: Declare the name of the entity and architecture by using VHDL source code.
STEP 3: Write the source code in VERILOG.
STEP 4: Check the syntax and debug the error is found. Obtain the synthesis report.
STEP 5: Verify the output by simulating the source code.
STEP 6: Write the all-possible combination of input using the test bench.
STEP 7: Obtain the place and route report.

LOGIC DIAGRAM:

VHDL SOURCE CODE

--Design : FREQUENCY DIVIDER

--Description : To implement FREQUENCY DIVIDER
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity freqdiv1 is
Port (x: in integer range 1 to 31;
clk,rst : in std_logic;
freq_out : inout std_logic);
end freqdiv1;

architecture Behavioral of freqdiv1 is

signal count: integer range 1 to 31:=1;
begin
process(clk,rst,x,count,freq_out)
begin
if(clk='1' and clk'event) then
if(rst='1') then
freq_out<=clk;
else

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 if(count>1) then
count<=count-1;
else
count<=x;
freq_out<=not(freq_out);
end if;
end if;
end if;
end process;

end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module freq_div(x, clk, rst, freq_out);

input [3:0] x;
input clk;
input rst;
output freq_out;
reg freq_out;
integer count=1;
always @ (posedge(clk) or posedge(rst))
begin
if (rst==1'b1)
begin
freq_out=clk;
end
else if (count>1)
begin
count=count-1'b1;
end
else
begin
count=x;
freq_out= ~freq_out;
end
end
endmodule

TEST BENCH(VERILOG):

module freqdiv_test_v;

// Inputs
reg [3:0] x;
reg clk;
reg rst;

// OUTPUT:s
wire freq_out;

// Instantiate the Unit Under Test (UUT)

freq_div uut (
.freq_out(freq_out),
.x(x),
.clk(clk),
.rst(rst)
);

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 always
#5clk=~clk;

initial begin
rst=1'b1;x=4'd5;clk=1'b0;
#10 rst=1'b0;
#200 x=4'd2;
#100 x = 4'd3;
end

endmodule

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 44 out of 3584 1%

Number of Slice Flip Flops: 32 out of 7168 0%
Number of 4 input LUTs: 83 out of 7168 1%
Number of bonded IOBs: 3 out of 97 3%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 32 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 11.542ns (Maximum Frequency: 86.640MHz)

Minimum input arrival time before clock: No path found
Maximum OUTPUT: required time after clock: 6.280ns
Maximum combinational path delay: No path found

RESULT:

Thus the OUTPUT’s of Frequency Divider are verified by synthesizing and simulating the VHDL and
VERILOG code.

EXP NO: 13 DATE: 19-03-09

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 DESIGN OF ARITHMATIC AND LOGIC UNIT
AIM:
To develop the source code for arithmetic and logic unit by using VHDL/VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.

ALGORITM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

LOGIC DIAGRAM:

TRUTH TABLE:

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VHDL SOURCE CODE

--Design : ALU
--Description : To implement ALU
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

Structural Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic;
s : in std_logic_vector(3 downto 0);
y : out std_logic_vector(7 downto 0));
end alu;
architecture structural of alu is
component arith
port(a,b:in std_logic_vector(7 downto 0);
c:in std_logic;
s:in std_logic_vector(2 downto 0);
x:out std_logic_vector(7 downto 0));
end component;
component logic
port(a,b:in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto 0);
x:out std_logic_vector(7 downto 0));
end component;
component mux1
port(a,b:in std_logic_vector(7 downto 0);
s:in std_logic;
x:out std_logic_vector(7 downto 0));
end component;
signal x1,x2:std_logic_vector(7 downto 0);
begin
a1:arith port map (a(7 downto 0),b(7 downto 0),c,s(2 downto 0),x1(7 downto 0));
l1:logic port map (a(7 downto 0),b(7 downto 0),s(2 downto 0),x2(7 downto 0));
m1:mux1 port map (x1(7 downto 0),x2(7 downto 0),s(3),y(7 downto 0));
end structural;

arithmetic component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity arith is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic;
s : in std_logic_vector(2 downto 0);
x : out std_logic_vector(7 downto 0));
end arith;
architecture Behavioral of arith is
begin

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process(a,b,c,s)
begin
case s is
when "000" => x <= a;
when "001" => x <= a+1;
when "010" => x <= a-1;
when "011" => x <= b;
when "100" => x <= b+1;
when "101" => x <= b-1;
when "110" => x <= a+b;
when others => x <= a+b+c;
end case;
end process;
end Behavioral;

logic component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logic is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
s : in std_logic_vector(2 downto 0);
x : out std_logic_vector(7 downto 0));
end logic;
architecture Behavioral of logic is
begin
process(a,b,s)
begin
case s is
when "000" => x <= not a;
when "001" => x <= not b;
when "010" => x <= a and b;
when "011" => x <= a nand b;
when "100" => x <= a or b;
when "101" => x <= a nor b;
when "110" => x <= a xor b;
when others => x <= a xnor b;
end case;
end process;
end Behavioral;

mux1 component source code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux1 is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
s : in std_logic;
x : out std_logic_vector(7 downto 0));
end mux1;
architecture Behavioral of mux1 is
begin
process(a,b,s)
begin
if (s='0') then
x<=a;

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else
x<=b;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module alu(a, b, cin, s, y);

input [7:0] a;
input [7:0] b;
input cin;
input [3:0] s;
output [7:0] y;
reg [7:0]y;

always @ (a or b or s)
begin
case(s)
4'b0000: y=a;
4'b0001: y=a+1;
4'b0010: y=a-1;
4'b0011: y=b;
4'b0100: y=b+1;
4'b0101: y=b-1;
4'b0110: y=a+b;
4'b0111: y=a+b+cin;
4'b1000: y=~a;
4'b1001: y=~b;
4'b1010: y=a&b;
4'b1011: y=a|b;
4'b1100: y=~(a&b);
4'b1101: y=~(a|b);
4'b1110: y=a^b;
4'b1111: y=~(a^b);
endcase
end
endmodule
TEST BENCH(VHDL)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT alu
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
c : IN std_logic;
s : IN std_logic_vector(3 downto 0);
y : OUT std_logic_vector(7 downto 0)

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 );
END COMPONENT;

--Inputs
SIGNAL c : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL s : std_logic_vector(3 downto 0) := (others=>'0');

--Outputs
SIGNAL y : std_logic_vector(7 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: alu PORT MAP(
a => a,
b => b,
c => c,
s => s,
y => y
);

tb : PROCESS
BEGIN
a<="10101010";b<="11001100";c<='1';s<="1010"; wait for 300ps;
a<="10101010";b<="11001100";c<='1';s<="1100"; wait for 300ps;
END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 57 out of 3584 1%

Number of 4 input LUTs: 88 out of 7168 1%
Number of bonded IOBs: 29 out of 97 29%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 12.860ns

RESULT:
Thus the OUTPUT’s of Arithmetic Logic Unit are verified by synthesizing and simulating the VHDL and
VERILOG code.

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EXP NO: 14 DATE: 23-03-09

BARREL SHIFTER
AIM:
To develop the source code for barrel shifter by using VHDL/VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.

ALGORITM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

LOGICAL DIAGRAM:

VHDL SOURCE CODE

--Design : BARREL SHIFTER
--Description : To implement BARREL SHIFTER
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i
Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bar_shftr is
generic ( n : positive := 7 );

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 Port ( data : in std_logic_vector(n-1 downto 0);
sel : in integer range 0 to n-1;
bar_out : out std_logic_vector(n-1 downto 0));
end bar_shftr;
architecture Behavioral of bar_shftr is
begin
process(sel,data)
variable var_buf : std_logic_vector(n-1 downto 0);
begin
var_buf:=data;
for k in 1 to sel loop
var_buf:=var_buf(n-2 downto 0) & var_buf(n-1);
end loop;
bar_out<=var_buf;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module barrel(aout, clk, rst, a, sft, lr);

input clk, rst, lr;
input [7:0]a;
input [2 :0]sft;
output [7:0]aout;
reg [7:0]aout;
always @ (posedge clk) begin

if (rst )
aout = 8'd0;
else
begin
if (lr)
aout = a << sft;
else
aout = a >> sft;
end
end
endmodule

TEST BENCH(VERILOG):

module test_v;
// Inputs
reg clk;
reg rst;
reg [7:0] a;
reg [2:0] sft;
reg lr;
// Outputs
wire [7:0] aout;
// Instantiate the Unit Under Test (UUT)
barrel uut (
.aout(aout),
.clk(clk),
.rst(rst),
.a(a),
.sft(sft),
.lr(lr)

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 );
always
#5clk=~clk;
initial
begin
// Initialize Inputs
a=8'h10;
clk =1'b0;rst = 1'b1;sft = 3'd3;lr=1'b0;
#5 rst=1'b0;
#20 sft=3'd5;
#10 lr=1'b1;
#20 sft=3'd1;
end
endmodule

Simulation output:

Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-4

Number of Slices: 26 out of 3584 0%

Number of Slice Flip Flops: 8 out of 7168 0%
Number of 4 input LUTs: 47 out of 7168 0%
Number of bonded IOBs: 22 out of 97 22%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |8 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: 10.125ns
Maximum output required time after clock: 7.165ns
Maximum combinational path delay: No path found

RESULT:

Thus the OUTPUT’s of Barrel Shifter are verified by synthesizing and simulating the VHDL and
VERILOG code.

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EXP NO: 15 DATE: 24-03-09

TRAFFIC LIGHT CONTROLLER

AIM:
To develop the source code for traffic light controller by using VHDL/VEILOG and obtain the simulation,
place and route and implementation into FPGA.

ALGORITHM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all the possible combinations of input using test bench.

LOGIC DIAGRAM:

VHDL SOURCE CODE

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 --Design : TRAFFIC LIGHT CONTROLLER
--Description : To implement TRAFFIC LIGHT CONTROLLER
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tflc is
Port ( clk : in std_logic;
rst : in std_logic;
g1,g2,g3,g4 : out std_logic_vector(1 downto 0);
r1,r2,r3,r4 : out std_logic;
y1,y2,y3,y4 : out std_logic);
end tflc;
architecture Behavioral of tflc is
type state is (s1,s2,s3,s4);
signal pst:state;
signal count:integer:=0;
begin
process(clk,rst)
begin
if (clk='1' and clk'event) then
if (rst='1') then
pst<=s1;
else
case pst is

when s1=>
if (count=4) then
y1<='1';y2<='0';y3<='0';y4<='0';
count<=0;
pst<=s2;
else
g1<="11";g2<="00";g3<="00";g4<="10";
r1<='0';r2<='1';r3<='1';r4<='1';
y1<='0';y2<='0';y3<='0';y4<='0';
pst<=s1;
count<=count+1;
end if;

when s2=>
if (count=4) then
y1<='0';y2<='1';y3<='0';y4<='0';
count<=0;
pst<=s3;
else
g1<="10";g2<="11";g3<="00";g4<="00";
r1<='1';r2<='0';r3<='1';r4<='1';
y1<='0';y2<='0';y3<='0';y4<='0';
pst<=s2;
count<=count+1;
end if;

when s3=>

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if (count=4) then
y1<='0';y2<='0';y3<='1';y4<='0';
count<=0;
pst<=s4;
else
g1<="00";g2<="10";g3<="11";g4<="00";
r1<='1';r2<='1';r3<='0';r4<='1';
y1<='0';y2<='0';y3<='0';y4<='0';
pst<=s3;
count<=count+1;
end if;

when s4=>
if (count=4) then
y1<='0';y2<='0';y3<='0';y4<='1';
count<=0;
pst<=s1;
else
g1<="00";g2<="00";g3<="10";g4<="11";
r1<='1';r2<='1';r3<='1';r4<='0';
y1<='0';y2<='0';y3<='0';y4<='0';
pst<=s4;
count<=count+1;
end if;

end case;
end if;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module tflc(g1,g2,g3,g4,r1,r2,r3,r4,y1,y2,y3,y4,clk,rst);
output [1:0] g1,g2,g3,g4;
output r1,r2,r3,r4,y1,y2,y3,y4;
input clk;
input rst;
reg [1:0] g1,g2,g3,g4;
reg r1,r2,r3,r4,y1,y2,y3,y4;
parameter st1=0,st2=1,st3=2,st4=3;
reg [0:1] pst;
reg [2:0]count=0;
initial
begin
pst=st1;
end
always @ (posedge(clk) or posedge(rst))
begin
if (rst==1'b1)
pst=st1;
else
case(pst)
st1:
if (count==3'b110) begin
y1=1'b1;y2=1'b0;y3=1'b0;y4=1'b0;
count=3'b000;
pst=st2;

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end
else
begin
g1=2'b11;g2=2'b00;g3=2'b00;g4=2'b10;
r1=1'b0;r2=1'b1;r3=1'b1;r4=1'b1;
y1=1'b0;y2=1'b0;y3=1'b0;y4=1'b0;
pst=st1;
count=count+1'b1;
end
st2:
if (count==3'b110) begin
y1=1'b0;y2=1'b1;y3=1'b0;y4=1'b0;
count=3'b000;
pst=st3;
end
else
begin
g1=2'b10;g2=2'b11;g3=2'b00;g4=2'b00;
r1=1'b1;r2=1'b0;r3=1'b1;r4=1'b1;
y1=1'b0;y2=1'b0;y3=1'b0;y4=1'b0;
pst=st2;
count=count+1'b1;
end
st3:
if (count==3'b110) begin
y1=1'b0;y2=1'b0;y3=1'b1;y4=1'b0;
count=1'b0;
pst=st4;
end
else
begin
g1=2'b00;g2=2'b10;g3=2'b11;g4=2'b00;
r1=1'b1;r2=1'b1;r3=1'b0;r4=1'b1;
y1=1'b0;y2=1'b0;y3=1'b0;y4=1'b0;
pst=st3;
count=count+1'b1;
end
st4:
if (count==3'b110) begin
y1=1'b0;y2=1'b0;y3=1'b0;y4=1'b1;
count=1'b0;
pst=st1;
end
else
begin
g1=2'b00;g2=2'b00;g3=2'b10;g4=2'b11;
r1=1'b1;r2=1'b1;r3=1'b1;r4=1'b0;
y1=1'b0;y2=1'b0;y3=1'b0;y4=1'b0;
pst=st4;
count=count+1'b1;
end
endcase
end
endmodule

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TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_vhd IS
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT tflc
PORT(
clk : IN std_logic;
rst : IN std_logic;
g1 : OUT std_logic_vector(1 downto 0);
g2 : OUT std_logic_vector(1 downto 0);
g3 : OUT std_logic_vector(1 downto 0);
g4 : OUT std_logic_vector(1 downto 0);
r1 : OUT std_logic;
r2 : OUT std_logic;
r3 : OUT std_logic;
r4 : OUT std_logic;
y1 : OUT std_logic;
y2 : OUT std_logic;
y3 : OUT std_logic;
y4 : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--Outputs
SIGNAL g1 : std_logic_vector(1 downto 0);
SIGNAL g2 : std_logic_vector(1 downto 0);
SIGNAL g3 : std_logic_vector(1 downto 0);
SIGNAL g4 : std_logic_vector(1 downto 0);
SIGNAL r1 : std_logic;
SIGNAL r2 : std_logic;
SIGNAL r3 : std_logic;
SIGNAL r4 : std_logic;
SIGNAL y1 : std_logic;
SIGNAL y2 : std_logic;
SIGNAL y3 : std_logic;
SIGNAL y4 : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: tflc PORT MAP(
clk => clk,
rst => rst,
g1 => g1,
g2 => g2,
g3 => g3,
g4 => g4,
r1 => r1,
r2 => r2,
r3 => r3,

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 r4 => r4,
y1 => y1,
y2 => y2,
y3 => y3,
y4 => y4
);

tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 200ps;
END;

Simulation output:

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Synthesis RTL Schematic:

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Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 45 out of 3584 1%

Number of Slice Flip Flops: 50 out of 7168 0%
Number of 4 input LUTs: 64 out of 7168 0%
Number of bonded IOBs: 18 out of 97 18%
Number of GCLKs: 1 out of 8 12%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 50 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 6.698ns (Maximum Frequency: 149.305MHz)

Minimum input arrival time before clock: 5.509ns
Maximum output required time after clock: 6.280ns
Maximum combinational path delay: No path found

RESULT:

Thus the OUTPUT’s of Traffic Light Controller are verified by synthesizing and simulating the VHDL and
VERILOG code.

EXP NO: 16 DATE: 27-03-09

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 DESIGN OF MEMORIES

AIM:
To develop the source code for memories by using VHDL/VEILOG and obtain the simulation, place and
route and implementation into FPGA.

ALGORITHM:

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all the possible combinations of input using test bench.

BLOCK DIAGRAM:

VHDL SOURCE CODE

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 --Design : ROM
--Description : To implement ROM
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rom is
generic ( bits : integer := 8;
words : integer := 8);
Port ( adder : in integer range o to words-1;
data : out std_logic_vector(bits-1 downto 0));
end rom;
architecture Behavioral of rom is
type vector_array is array(0 to words-1) of std_logic_vector(bits-1 downto 0);
constant memory : vector_array := ("00000000",
"00000010",
"00000100",
"00001000",
"00010000",
"00100000",
"01000000",
"10000000");
begin
data <= memory(addr);
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module rom(addr, data_out);

input [2:0] addr;
output [7:0] data_out;
reg [7:0] data_out;
reg [7:0]mem [0:7];
initial
begin
mem[0]=8'b00000000;
mem[1]=8'b00000010;
mem[2]=8'b00000100;
mem[3]=8'b00001000;
mem[4]=8'b00010000;
mem[5]=8'b00100000;
mem[6]=8'b01000000;
mem[7]=8'b10000000;
end
always@(addr) begin
data_out=mem[addr];
end
endmodule

Simulation output:

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Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of Slices: 4 out of 3584 0%

Number of 4 input LUTs: 7 out of 7168 0%
Number of bonded IOBs: 11 out of 97 11%

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Timing Summary:

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---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.985ns

VHDL SOURCE CODE

--Design : RAM
--Description : To implement RAM
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram is
generic( bits:integer:=8;
words:integer:=16);
Port ( wr_ena : in std_logic;
clk : in std_logic;
addr : in integer range 0 to words-1;
data_in : in std_logic_vector(bits-1 downto 0);
data_out : out std_logic_vector(bits-1 downto 0));
end ram;
architecture Behavioral of ram is
type vector_array is array (0 to words-1) of std_logic_vector(bits-1 downto 0);
signal memory : vector_array;
begin
process(clk,wr_ena)
begin
if (clk='1' and clk'event) then
if (wr_ena='1') then
memory(addr)<=data_in;
else
data_out<=memory(addr);
end if;
end if;
end process;
end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module ram(clk, wr_en, data_in, addr, data_out);

input clk;
input wr_en;
input [7:0] data_in;
input [3:0] addr;
output [7:0] data_out;
reg [7:0] data_out;
reg [7:0]mem [0:15];

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 always@(posedge(clk),wr_en,data_in,addr)
if(clk)
begin
if(wr_en)
mem[addr]=data_in;
else
data_out=mem[addr];
end
endmodule

TEST BENCH(VERILOG):

module tst_v;
// Inputs
reg clk;
reg wr_en;
reg [7:0] data_in;
reg [3:0] addr;
// Outputs
wire [7:0] data_out;
// Instantiate the Unit Under Test (UUT)
ram uut (
.clk(clk),
.wr_en(wr_en),
.data_in(data_in),
.addr(addr),
.data_out(data_out)
);
always
#5 clk=~clk;
initial
begin
// Initialize Inputs
clk = 1'b1;
data_in = 8'ha0;
addr = 5'd0;
wr_en = 1'b1;
#10 wr_en=1'b0;
end
endmodule

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Simulation output:

Synthesis RTL Schematic:

Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------

Selected Device : 3s400tq144-5

Number of bonded IOBs: 22 out of 97 22%

Number of BRAMs: 1 out of 16 6%

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Number of GCLKs: 1 out of 8 12%
=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
-----------------------------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |1 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: 1.818ns
Maximum output required time after clock: 7.662ns
Maximum combinational path delay: No path found

RESULT:
Thus the OUTPUT’s of ROM and RAM are verified by synthesizing and simulating the VHDL and
VERILOG code.

EXP NO: 17 DATE: 01-04-09

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 DESIGN OF MAC UNIT
AIM
To develop the source code for MAC unit by using VHDL/VEILOG and obtain the simulation, place and
route and implementation into FPGA.

ALGORITHM

Step1: Define the specifications and initialize the design.

Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all the possible combinations of input using test bench.

BLOCK DIAGRAM:

VHDL SOURCE CODE

--Design : MAC
--Description : To implement MAC
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

Behavioral Modeling:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL

entity mac is
Port ( a : in integer range 0 to 7 ;

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 b : in integer range 0 to 7;
rst : in std_logic;
clk : in std_logic;
acc : out integer range 0 to 50);
end mac;

architecture Behavioral of mac is

signal prod:integer range 0 to 50;
signal areg,breg:integer range 0 to 7;
signal addr:integer range 0 to 50;

begin

process(rst,clk)
begin
if(rst='1') then
addr<=0;
elsif (clk='1' and clk'event) then
areg<=integer(a);
breg<=integer(b);
prod<=areg*breg;
addr<=addr + prod;
end if;
end process;
acc<=integer(addr);

end Behavioral;

VERILOG SOURCE CODE:

Behavioral Modeling:

module mac(a, b, clk, rst, acc);

input [7:0] a;
input [7:0] b;
input clk;
input rst;
output [15:0] acc;
reg [15:0] acc;
reg [15:0] pd;
reg [15:0] adder;
always @ (posedge(clk) or posedge(rst))
begin
if (rst==1'b1)
begin
adder=8'b00000000;
end
else
begin
pd=a*b;
adder=adder+pd;
end
acc=adder;
end
endmodule

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TEST BENCH(VHDL):

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testmac_vhd IS
END testmac_vhd;

ARCHITECTURE behavior OF testmac_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mac
PORT(
a : IN integer range 0 to 7;
b : IN integer range 0 to 7;
rst : IN std_logic;
clk : IN std_logic;
acc : OUT integer range 0 to 50
);
END COMPONENT;

--Inputs
SIGNAL rst : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL a : integer range 0 to 7;
SIGNAL b : integer range 0 to 7;

--Outputs
SIGNAL acc : integer range 0 to 50;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: mac PORT MAP(
a => a,
b => b,
rst => rst,
clk => clk,
acc => acc
);

tb : PROCESS
BEGIN
clk<='1'; wait for 5 ns;
clk<='0'; wait for 5 ns;
-- Wait 100 ns for global reset to finish
--wait for 100 ns;

-- Place stimulus here

--wait; -- will wait forever

END PROCESS;
rst<='1','0' after 1 ns;
a<=2,4 after 20 ns;
b<=3,5 after 40 ns;
END;

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Simulation output:

Synthesis RTL Schematic:

Synthesis report
=========================================================================
* Final Report *
=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s400pq208-5

Number of Slices: 6 out of 3584 0%

Number of Slice Flip Flops: 12 out of 7168 0%
Number of 4 input LUTs: 6 out of 7168 0%
Number of bonded IOBs: 14 out of 141 9%
Number of MULT18X18s: 1 out of 16 6%
Number of GCLKs: 1 out of 8 12%

=========================================================================

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TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 13 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

Minimum period: 3.942ns (Maximum Frequency: 253.688MHz)

Minimum input arrival time before clock: 3.530ns
Maximum output required time after clock: 6.280ns
Maximum combinational path delay: No path found

RESULT:
Thus the OUTPUT’s of MAC Unit are verified by synthesizing and simulating the VHDL and VERILOG
code.

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EXP NO: 18 DATE: 06-04-09

SWITCH LEVEL DESIGN

AIM:
To develop the source code for basic logic gates by using VERILOG in switch level design and obtain the
simulation.

ALGORITM:

Step1: Define the specifications and initialize the design.

Step2: Write the source code in VERILOG.
Step3: Check the syntax and debug the errors if found, verify and correct them.
Step4: Verify the output by simulating the source code.

INVERTER:

LOGIC DIAGRAM:

TRUTH TABLE:

A Y=A’
0 1
1 0

VERILOG SOURCE CODE:

--Design : INVERTER
--Description : To implement INVERTER
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module inv(in, out);

input in;
output out;
supply1 pwr;
supply0 gnd;
pmos(out,pwr,in);
nmos(out,gnd,in);
endmodule

Simulation output:

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NOR GATE:

LOGIC DIAGRAM:
TRUTH TABLE:

A B Y=(A+B)’
0 0 1
0 1 0
1 0 0
1 1 0

VERILOG SOURCE CODE:

--Design : NOR GATE
--Description : To implement NOR GATE
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module nor2(a, b, out);

input a;
input b;
output out;
wire c;
supply1 pwr;
supply0 gnd;
pmos(c,pwr,b);
pmos(out,c,a);
nmos(out,gnd,a);
nmos(out,gnd,b);
endmodule

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Simulation output:

OR GATE:

LOGIC DIAGRAM: TRUTH TABLE

A B Y=(A+B)
0 0 0
0 1 1
1 0 1
1 1 1

VERILOG SOURCE CODE:

--Design : OR GATE
--Description : To implement OR GATE
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module or2(a, b, out);

input a;
input b;
output out;
wire c,z;
supply1 pwr;
supply0 gnd;
pmos(c,pwr,b);
pmos(z,c,a);

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 pmos(out,pwr,z);
nmos(z,gnd,a);
nmos(z,gnd,b);
nmos(out,gnd,z);
endmodule

Simulation output:

NAND GATE:

LOGIC DIAGRAM:
TRUTH TABLE:

A B Y=(AB)’
0 0 1
0 1 1
1 0 1
1 1 0

VERILOG SOURCE CODE:

--Design : NAND GATE

--Description : To implement NAND GATE
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module nand2(a, b, out);

input a;
input b;
output out;
wire c;
supply1 pwr;
supply0 gnd;
pmos(out,pwr,a);
pmos(out,pwr,b);
nmos(c,gnd,b);

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 nmos(out,c,a);
endmodule

Simulation output:

AND GATE:

LOGIC DIAGRAM:
TRUTH TABLE:
A B Y=AB
0 0 0
0 1 0
1 0 0
1 1 1

VERILOG SOURCE CODE:

--Design : AND GATE

--Description : To implement AND GATE
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module and2(a, b, out);

input a;
input b;
output out;
wire c,z;
supply1 pwr;

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 supply0 gnd;
pmos(z,pwr,a);
pmos(z,pwr,b);
pmos(out,pwr,z);
nmos(c,gnd,b);
nmos(z,c,a);
nmos(out,gnd,z);
endmodule

Simulation output:

XOR GATE:

LOGIC DIAGRAM: TRUTH TABLE:

A B
0 0 0
0 1 1
1 0 1
1 1 0

VERILOG SOURCE CODE:

--Design : XOR GATE

--Description : To implement XOR GATE
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module xor2(a, b, out);

input a;
input b;
output out;

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 wire abar,bbar,x,y;
supply1 pwr;
supply0 gnd;
inv
n1(a,abar),
n2(b,bbar);
and2
a1(abar,b,x),
a2(a,bbar,y);
or2
o1(x,y,out);
endmodule

Simulation output:

HALF ADDER:

LOGIC DIAGRAM:
TRUTH TABLE:

A B SUM CARRY

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

VERILOG SOURCE CODE:

--Design : HALF ADDER

--Description : To implement HALF ADDER
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module ha(a, b, sum, carry);

input a;
input b;
output sum;
output carry;
supply1 pwr;

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 supply0 gnd;
xor2
x1(a,b,sum);
and2
a1(a,b,carry);
endmodule

Simulation output:

HALF SUBTRACTOR:

LOGIC DIAGRAM: TRUTH TABLE

A B DIFFERENCE BORROW

0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

VERILOG SOURCE CODE:

--Design : HALF SUBSTRACTOR

--Description : To implement HALF SUBSTRACTOR
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module hs(a, b, diff, borrow);

input a;
input b;
output diff;
output borrow;
wire abar;
supply1 pwr;
supply0 gnd;
inv
n1(a,abar);
xor2
x1(a,b,diff);
and2
a1(abar,b,borrow);
endmodule

Simulation output:

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FULL ADDER:

LOGIC DIAGRAM: TRUTH TABLE:

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

VERILOG SOURCE CODE:

--Design : FULL ADDER

--Description : To implement FULL ADDER
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module fa(a, b, c, sum, carry);

input a;
input b;
input c;
output sum;
output carry;
wire p,q,r,s,t;
supply1 pwr;
supply0 gnd;
xor2
x1(a,b,p),
x2(p,c,sum);
and2
a1(a,b,q),
a2(b,c,r),
a3(c,a,t);
or2
o1(q,r,s),
o2(s,t,carry);
endmodule

Simulation output:

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FULL SUBTRACTOR:

LOGIC DIAGRAM:

TRUTH TABLE:
A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

VERILOG SOURCE CODE:

--Design : FULL SUBSTRACTOR

--Description : To implement FULL SUBSTRACTOR
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i

module fs(a, b, c, diff, borrow);

input a;
input b;
input c;
output diff;
output borrow;
wire abar,p,q,r,s,t;
supply1 pwr;
supply0 gnd;
xor2
x1(a,b,p),
x2(p,c,diff);
inv
n1(a,abar);
and2
a1(abar,b,q),

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 a2(b,c,r),
a3(c,abar,t);
or2
o1(q,r,s),
o2(s,t,borrow);
endmodule

Simulation output:

RESULT:
Thus the OUTPUT’s of switchlevel design basic logic gates, adders and substractors are verified and
simulated using the VERILOG code.

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