Space Vector Modulation of Multi-Level and Multi-Module

Converters for High Power Applications

by

Maryam Saeedifard

A thesis submitted in conformity with the requirements

for the degree of Doctor of Philosophy
Graduate Department of Electrical and Computer Engineering
University of Toronto

c 2008 by Maryam Saeedifard

Copyright °
 Abstract

Space Vector Modulation of Multi-Level and Multi-Module Converters for High Power
Applications

Maryam Saeedifard
Doctor of Philosophy
Graduate Department of Electrical and Computer Engineering
University of Toronto
2008

This thesis presents and investigates Space Vector Modulation (SVM) switching

strategies for (i) a multi-level Diode-Clamped Converter (DCC) and (ii) a multi-module

Voltage-Sourced Converter (VSC) system in which each module is a conventional two-

level VSC. Although the SVM strategies are general and applicable for n-level DCC and

n-module VSC systems, this text only concentrates on five-level DCC and four-module

VSC systems.

For a five-level DCC, a computationally efficient SVM algorithm is proposed. The

algorithm, that is based on a classifier Neural Network (NN), reduces the computational

time for the SVM realization. Therefore, adequate saving of processor execution time,

in each sampling period of SVM, is provided to carry out other functions, e.g. the

calculations required for DC-capacitor voltage balancing task. The thesis also proposes

a DC-capacitor voltage balancing strategy to counteract the voltage drift phenomenon of

(i) a passive-front-end five-level DCC, and (ii) a back-to-back connected five-level DCC

system. The proposed balancing strategy, that is based on augmenting the proposed SVM

algorithm, takes advantage of the redundant switching states to minimize a quadratic cost

function associated with voltage deviations of the DC-capacitors. The salient features

of the proposed balancing strategy are (i) online calculation of SVM to select the best

switching states, (ii) minimization of switching frequency, (iii) minimization of the THD

content of the AC-side voltage, and (iv) no requirement for additional power circuitry.

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 For a four-module VSC system a sequential sampling SVM strategy is proposed. The

proposed strategy (i) provides harmonic cancellation/minimization at the net AC-side

voltage of the multi-module VSC system, and (ii) offers a low switching frequency for

each VSC module.

Technical feasibility of the proposed SVM strategies for a five-level DCC and a four-

module VSC system, as a STATCOM and a back-to-back HVDC system, are investigated

and presented. The studies are conducted in the time-domain, in the PSCAD/EMTDC

software environment.

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 Dedication
In the memory of my dear father

and

Dedicated to my loving mother

iv
 Acknowledgements
I would like to express my sincere gratitude to my supervisor, Professor Reza Iravani, for
his invaluable supervision, encouragement, and financial support throughout my Ph.D.
studies.
Furthermore, I should acknowledge great efforts of the entire Ph.D. exam committee:
Professor Richard Bonert, Professor Peter Lehn, and Professor Bin Wu for their review
of this thesis, discussions, and constructive comments.
I would also like to recognize the financial support of the University of Toronto and On-
tario Graduate Scholarships.

I would like to extend my appreciation to my friends in Toronto with whom I shared

great memories.
I cannot end without thanking my lovely family, on whose constant encouragement,
support, and love, I have relied throughout my life. Without their intense care and
compassionate support, I would have never been able to come this far.

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Contents

1 Introduction 1
1.1 Statement of the Problem . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 Multi-Level DCC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.2 Multi-Module VSC . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 SVM Switching Strategy for a Multi-Level DCC 9

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Principles of Operation of a Multi-Level DCC . . . . . . . . . . . . . . . 10
2.3 SVM for a n-level DCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.1 Space Vector Plane, Sectors, and Switching Vectors . . . . . . . . 11
2.3.2 Conventional SVM Algorithm . . . . . . . . . . . . . . . . . . . . 13
2.4 Proposed SVM Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 Fast SVM Algorithm Based on Kohonen’s Competitive NN . . . . 16
2.4.2 Determination of Reference Vector Location . . . . . . . . . . . . 19
2.4.3 Duty-Cycle Calculations . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.4 Determination of Switching States Corresponding to Switching Vec-
tors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.5 Study Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3 DC-Capacitor Voltage Control of a Five-Level DCC 32

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Five-Level DCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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 3.2.1 Fundamentals of Operation . . . . . . . . . . . . . . . . . . . . . 33
3.2.2 Theoretical Limits to Capacitors Voltage Balancing . . . . . . . . 34
3.2.3 DC-Capacitor Voltage Drift Phenomenon . . . . . . . . . . . . . . 35
3.3 SVM For a Five-Level DCC . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.1 Space Vector Plane, Sectors, and Switching Vectors . . . . . . . . 41
3.3.2 Effects of Different Switching States on DC-Intermediate Branch
Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4 DC-capacitor Voltages Balancing Based on Minimum Energy Property . 49
3.4.1 Space Vector Sequence and Switching Frequency . . . . . . . . . . 53
3.5 Study Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.5.1 Limits of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.5.2 Capacitor Voltages Balancing Under Balanced Linear Load Condi-
tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.5.3 Capacitor Voltages Balancing Under Unbalanced or Distorted AC-
side Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.6 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4 Modeling and Control of a Five-Level DCC-based STATCOM 64

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.2 System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.3.1 System Model in abc Frame . . . . . . . . . . . . . . . . . . . . . 66
4.3.2 System Model in dq Frame . . . . . . . . . . . . . . . . . . . . . . 68
4.4 System Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.4.1 AC-Side Current Control . . . . . . . . . . . . . . . . . . . . . . . 69
4.4.2 Net DC Voltage Controller . . . . . . . . . . . . . . . . . . . . . . 71
4.4.3 PCC Voltage Controller . . . . . . . . . . . . . . . . . . . . . . . 72
4.5 Case Studies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.5.1 Case-1: Load and STATCOM Energization . . . . . . . . . . . . . 74
4.5.2 Case-2: Reactive Power Control . . . . . . . . . . . . . . . . . . . 75
4.5.3 Case-3: Load Voltage Control . . . . . . . . . . . . . . . . . . . . 76
4.5.4 Case-4: Load Energization Under Unbalanced Source Conditions . 76
4.5.5 Case-5: Three-Phase Fault . . . . . . . . . . . . . . . . . . . . . . 77
4.6 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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5 Five-Level DCC-Based Back-to-Back HVDC System 85
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.2 Five-Level DCC-Based HVDC System Structure . . . . . . . . . . . . . . 86
5.3 Voltage Balancing of the DCC System . . . . . . . . . . . . . . . . . . . 87
5.3.1 Space Vector Sequence and Switching Frequency . . . . . . . . . . 90
5.4 Mathematical Model of the HVDC System . . . . . . . . . . . . . . . . . 92
5.4.1 System Model in abc Frame . . . . . . . . . . . . . . . . . . . . . 92
5.4.2 Expression of abc Model in dq-Frame . . . . . . . . . . . . . . . . 94
5.5 AC-Side Current Control of DCC System . . . . . . . . . . . . . . . . . . 95
5.6 DC-Bus Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.7 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.7.1 Study System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.7.2 Study Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.8 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6 A SVM-Based Multi-Module HVDC Converter System 109

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2 Multi-Module HVDC System Structure . . . . . . . . . . . . . . . . . . . 110
6.3 Proposed SVM Switching Strategy . . . . . . . . . . . . . . . . . . . . . 111
6.3.1 Sequential Sample and Hold Voltage Synthesis . . . . . . . . . . . 112
6.3.2 Sequential Sampling SVM Technique . . . . . . . . . . . . . . . . 114
6.3.3 SVM Switching Pattern . . . . . . . . . . . . . . . . . . . . . . . 115
6.4 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.4.1 System Model in abc Frame . . . . . . . . . . . . . . . . . . . . . 122
6.4.2 Transformation of abc Model to dq-Frame . . . . . . . . . . . . . 124
6.5 AC-Side Current Control of VSC Systems . . . . . . . . . . . . . . . . . 125
6.6 DC-Bus Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.7 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.7.1 Study System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.7.2 Study Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.8 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . 133

7 Conclusions 139
7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

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 7.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.3 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.4 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

A Harmonic Analysis of a SVM-Based N-Module VSC 144

A.1 Harmonic Analysis of one VSC module . . . . . . . . . . . . . . . . . . . 144
A.2 Harmonic Analysis of a N -Module VSC . . . . . . . . . . . . . . . . . . . 146

B Analysis of DC-Capacitor Voltage Drift Phenomenon of a SPWM-

Switched, Back-to-Back Connected Five-Level DCC System 148

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List of Figures

2.1 Circuit diagram of a three-phase n-level DCC . . . . . . . . . . . . . . . 10

2.2 A schematic representation of the n-level DCC of Fig. 2.1 based on n-pole
fictitious switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Representation of space voltage vectors of a n-level DCC in αβ plane . . 13
2.4 First sector corresponding to the space voltage vectors of an n-level DCC 14
2.5 Schematic diagram of the classification algorithm . . . . . . . . . . . . . 16
2.6 Representation of the reference vector and switching vectors of a 2-level
converter in the αβ plane: (a) all sectors, (b) the winners of the competition 17
2.7 Space vector representation of an n-level DCC in the first sector . . . . . 20
2.8 Schematic diagram of the classification algorithm for a multi-level DCC . 24
2.9 AC-side voltage waveform of a 3-level DCC; m = 0.8, fsw = 2880Hz. . . . 27
2.10 AC-side voltage waveform of a 3-level DCC; m = 0.6, fsw = 2880Hz. . . . 27
2.11 AC-side voltage waveform of a 3-level DCC; m = 0.4, fsw = 2880Hz. . . . 28
2.12 AC-side voltage waveform of a 4-level DCC; m = 0.8, fsw = 2880Hz. . . . 29
2.13 AC-side voltage waveform of a 4-level DCC; m = 0.6, fsw = 2880Hz. . . . 29
2.14 AC-side voltage waveform of a 4-level DCC; m = 0.4, fsw = 2880Hz. . . . 30
2.15 AC-side voltage waveform of a 5-level DCC; m = 0.8, fsw = 2880Hz. . . . 30
2.16 AC-side voltage waveform of a 5-level DCC; m = 0.6, fsw = 2880Hz. . . . 31
2.17 AC-side voltage waveform of a 5-level DCC; m = 0.4, fsw = 2880Hz. . . . 31

3.1 Schematic representation of passive-front-end five-level DCC . . . . . . . 33

3.2 SPWM waveforms of a five-level DCC . . . . . . . . . . . . . . . . . . . . 35
3.3 Voltage balancing region of a passive-front-end n-level DCC (n → ∞) . . 36
3.4 Schematic representation of the five-level DCC system of Fig. 3.1 based
on five-pole fictitious switches . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5 An equivalent circuit of the five-level DCC of Fig. 3.4 . . . . . . . . . . . 38

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3.6 Switching functions of phase-a of a SPWM-switched five-level DCC
solid lines: exact switching functions
dashed lines: continuous mathematical switching functions . . . . . . . . 39
3.7 Space voltage vectors for a five-level DCC . . . . . . . . . . . . . . . . . 42
3.8 Adjacent switching states of Vref in odd sectors . . . . . . . . . . . . . . 45
3.9 Adjacent switching states of Vref in even sectors . . . . . . . . . . . . . . 46
3.10 Mapping sectors II to VI to sector I such that shaded areas overlap . . . 47
3.11 Schematic diagram of the balancing strategy based on the augmented SVM
switching strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.12 Schematic representation of the system Fig. 3.1 including AC-side current
sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.13 Limits of the proposed SVM-based balancing method for a four-level and
a five-level passive-front-end DCCs
A: operating point corresponding to Fig. 3.14
B: operating point corresponding to Fig. 3.15
C: operating point corresponding to Fig. 3.16 . . . . . . . . . . . . . . . 57
3.14 Converter waveforms for operating condition of P F = 1 and m = 0.7: (a)
AC-side voltage, (b) AC-side currents, and (c) DC-capacitor voltages . . 61
3.15 DCC waveforms for operating condition of P F = 1 and m = 0.5: (a)
AC-side voltage, (b) AC-side currents, and (c) DC-capacitor voltages . . 62
3.16 DCC waveforms under balanced loading condition of P F = 0.35 and m =
0.9: (a) AC-side voltage, (b) three-phase AC-side currents, and (c) DC-
capacitor voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.17 DCC waveforms under unbalanced loading condition of P F = 0.35 and
m = 0.9: (a) AC-side voltage, (b) three-phase AC-side currents, and (c)
DC-capacitor voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.18 DCC waveforms under operating condition of P F = 0.35, m = 0.9, and
distorted AC-side currents: (a) AC-side voltage, (b) three-phase AC-side
currents, and (c) DC-capacitor voltages . . . . . . . . . . . . . . . . . . 63

4.1 Schematic diagram of a five-level DCC-based STATCOM connected to a

utility system at the load terminal . . . . . . . . . . . . . . . . . . . . . . 65
4.2 An equivalent circuit of the system of Fig. 4.1 based on the DCC equivalent
circuit of Fig. 3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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4.3 Simplified equivalent circuit of Fig. 4.2 . . . . . . . . . . . . . . . . . . . 67
4.4 Block diagram of the proposed current controller for the STATCOM of
Fig. 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.5 Block diagram of DC-bus voltage controller of the STATCOM of Fig. 4.1 72
4.6 Block diagram of the PCC voltage controller of STATCOM of Fig. 4.1 . . 72
4.7 A block diagram representation of the system of Fig. 4.1 including power
and control sub-systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.8 Block diagram of the overall controllers of the STATCOM . . . . . . . . 74
4.9 Dynamic behavior of the system of Fig. 4.7 to load and STATCOM en-
ergization: (a) STATCOM current, (b) load current, (c) STATCOM DC
voltage, (d) STATCOM line-to-line terminal voltage, (e) load voltage, and
(f) DC capacitor voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.10 Dynamic response of the system of Fig. 4.7 to a step change in reactive
power command: (a) STATCOM reactive current component, (b) STATCOM
DC voltage, (c) reactive current component of utility system current, (d,e)
load and STATCOM current, (f) magnitude of load voltage, (g) STAT-
COM terminal voltage and (h) capacitor voltages . . . . . . . . . . . . . 80
4.11 Control of load voltage in the system of Fig. 4.7: (a) load current, (b) magnitude
of load voltage, (c,d) STATCOM reactive and active current components,
(e) utility system reactive current components, (f) capacitor voltages . . 81
4.12 Control of load voltage in the system of Fig. 4.7 when the utility system
voltages are unbalanced: (a,b) three phase voltages of the utility system
and load, (c) load current, (d) magnitude of load voltage (e,f) STATCOM
and utility system reactive current components, (g) DC capacitor voltages 82
4.13 Transient response of the system of Fig. 4.7 to a three-phase fault: (a) STATCOM
current, (b) load voltage magnitude, (c) STATCOM DC voltage, (d,e) real and reactive
current components of STATCOM, and (f,g) real and reactive current com-
ponents of the utility system . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.14 Trajectory of the STATCOM operating point subsequent to the three-
phase fault scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.1 Schematic diagram of a five-level DCC-based HVDC converter system . . 86

5.2 An equivalent circuit of the HVDC system of Fig. 5.1 based on the DCC
equivalent circuit of Fig. 3.5 . . . . . . . . . . . . . . . . . . . . . . . . . 87

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5.3 Block diagram of DC-link balancing strategy for the converter system of
Fig. 5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.4 Simplified equivalent circuit of Fig. 5.2 . . . . . . . . . . . . . . . . . . . 92
5.5 Block diagram of the decoupled dq-frame current controllers . . . . . . . 96
5.6 Dynamic response of the system of Fig. 5.1 to a step change in the DC volt-
age reference when P1 = −P2 = −0.45 pu: (a) DC-link voltage, (b,c) real
current components of AC System-1 and AC System-2, (d,e) real power
components of AC System-1 and AC System-2, and (f) DC-capacitor volt-
ages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.7 Dynamic response of the system of Fig. 5.1 to step changes in real and
reactive power commands: (a,b) real and reactive current components of
AC System-1, (c,d) real and reactive power components of AC System-1,
(e,f) real and reactive current components of AC System-2, (g,h) real and
reactive power components of AC System-2, (i) net DC-link voltage, and
(k) DC-capacitor voltages . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.8 Dynamic response of the system of Fig. 5.1 to a real power reversal de-
mand: (a,b) real components of AC System-1 current and power, (c,d)
real components of AC System-2 current and power, (e,f) recative power
components of AC System-1 and AC System-2, (g,h) phase-a currents of
AC System-1 and AC System-2, (i,j) modulation indices of DCC-1 and
DCC-2, (k) net DC-link voltage, and (l) DC-capacitor voltages . . . . . . 107
5.9 Dynamic response of the system of Fig. 5.1 to step changes in real and
reactive power demands where the HVDC system interfaces a 50 Hz system
to a 60 Hz system: (a,b) real and reactive components of AC System-1
currents, (c,d) real and reactive power components of AC System-1, (e,f)
real and reactive components of AC System-2 currents, (g,h) real and
reactive power components of AC System-2, (i,j) phase-a currents of AC
System-1 and AC System-2, (k) net DC-link voltage, and (l) DC-capacitor
voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.1 Schematic diagram of a four-module back-to-back HVDC converter station 111

6.2 Schematic diagram of each VSC module . . . . . . . . . . . . . . . . . . 111
6.3 Principle of sequential sample and hold voltage synthesis technique . . . 112

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6.4 Output voltages of individual units and the resultant output voltage of
the proposed sequential sample and hold voltage synthesizer (ideal case) . 113
6.5 Schematic representation of the sequential sampling SVM technique . . . 114
6.6 Sequential sampling based SVM for the four VSC modules of Fig. 6.1 in
Sector I. As the reference voltage vector rotates in the αβ plane, each
modulator samples at a specified instant. . . . . . . . . . . . . . . . . . . 115
6.7 Proposed space vector switching pattern in Sector I and II . . . . . . . . 116
6.8 AC-side line voltage of one VSC module . . . . . . . . . . . . . . . . . . 117
6.9 Magnitudes and phase angles of harmonics versus sampling angle for m = 1
for the VSC modules of the four-module converter system of Fig. 6.1: (a)
magnitude, (b) phase angle . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.10 AC-side line voltage spectra of the four-module VSC system of Fig. 6.1
versus modulation index m . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.11 Harmonics as percentages of the fundamental component versus modula-
tion index for VSC modules of the four-module converter system of Fig. 6.1120
6.12 AC-side voltage of a four-module VSC that operates based on the proposed
sequential sample and hold VSC: (a) line voltage, and (b) line voltage
spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.13 AC-side voltage of an eight-module VSC that operates based on the pro-
posed sequential sample and hold VSC: (a) line voltage, and (b) line volt-
age spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.14 Block diagram of the decoupled dq-frame current controllers . . . . . . . 127
6.15 Steady state current and voltage waveforms of the four-module converter
system of Fig. 6.1: (a,b) line voltage of VSC-1 terminal and its spectrum,
(c,d) line voltage of top VSC module of VSC-1 and its spectrum, (e,f)
AC System-1 current and its spectrum, (g) net DC-link voltage, (h) per-
module DC-capacitor voltage . . . . . . . . . . . . . . . . . . . . . . . . 135
6.16 Dynamic response of the system of Fig. 6.1 to step changes in real and re-
active power demands: (a,b) real and reactive components of AC System-2
currents, (c,d) real and reactive power components of AC System-2, (e)
net DC-link voltage, (f,g) real and reactive components of AC System-1
currents, and (h,k) real and reactive power components of AC System-1 . 136

xiv
6.17 Dynamic response of the system of Fig. 6.1 to a real power reversal de-
mand: (a,b) real components of AC System-1 current and power, (c,d)
real components of AC System-2 current and power, (e,f) reactive current
components of AC System-1 and AC System-2, and (g,h) phase-a currents
of AC System-1 and AC System-2 . . . . . . . . . . . . . . . . . . . . . . 137
6.18 Transient response of the system of Fig. 6.1 to a temporary single-phase
to ground fault: (a) AC System-2 phase-a current, (b) DC-link voltage,
(c,d) real and reactive components of AC System-2 currents, and (e,f) real
and reactive components of AC System-1 currents . . . . . . . . . . . . . 138

A.1 Modulation function of SVM-based VSC module . . . . . . . . . . . . . . 145

xv
List of Tables

2.1 Switching states of a n-level DCC . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Switching states and corresponding space voltage vectors . . . . . . . . . 18
2.3 Relationship between switching states in sectors I to VI . . . . . . . . . . 23

3.1 Switching states of a five-level DCC . . . . . . . . . . . . . . . . . . . . . 33

3.2 Relationship between the DC-intermediate branch currents and AC-currents
for different switching states in Sector I . . . . . . . . . . . . . . . . . . . 44
3.3 Interchanging the AC-side currents for switching states in odd-numbered
sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4 Interchanging the AC-side currents for switching states in even-numbered
sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.5 Interchanging the AC-side currents for switching states in sectors I to VI 49
3.6 Interchanging the switching states in sectors I to VI . . . . . . . . . . . . 53
3.7 Parameters of the system of Fig. 3.12 . . . . . . . . . . . . . . . . . . . . 56

4.1 Parameters of the study system of Fig. 4.7 . . . . . . . . . . . . . . . . . 75

5.1 Parameters of the study system of Fig. 5.1 . . . . . . . . . . . . . . . . . 99

6.1 Parameters of the study system of Fig. 6.1 . . . . . . . . . . . . . . . . . 130

xvi
List of Abbreviations

VSC: Voltage-Sourced Converter

IGBT: Insulated Gate Bipolar Transistor
IGCT: Integrated Gate Commutated Thyristor
HVDC: High Voltage Direct Current
DCC: Diode-Clamped Converter
PWM: Pulse Width Modulation
SPWM: Sinusoidal Pulse Width Modulation
SVM: Space Vector Modulation
NN: Neural Network
THD: Total Harmonic Distortion
STATCOM: STATic COMpensator
PD: Phase Disposition
POD: Phase Opposition Disposition
APOD: Alternative Phase Opposition Disposition
SISO: Single-Input Single-Output
PI: Proportional-Integral
dq: direct-quadrature
PCC: Point of Common Coupling
PLL: Phase-Locked Loop

xvii
List of Symbols

S: switching function
d: duty cycle
e: error signal
fsw : switching frequency
fsampling : sampling frequency
i: current
s: Laplace transform variable
t: continuous time
v: voltage
θ: phase angle
ω: frequency

xviii
Chapter 1

Introduction

1.1 Statement of the Problem

The two-level, forced-commutated, Voltage-Sourced Converter (VSC) is the main build-
ing block for AC-DC and AC-DC-AC converter systems for low- and medium-power ap-
plications. Recent developments in semiconductor technology and commercial availability
of high power switches, e.g. Insulated Gate Bipolar Transistor (IGBT) and Integrated
Gate Commutated Thyristor (IGCT), have resulted in a widespread acceptance of the
two-level VSC for high-power applications as well. However, for some applications, e.g.
HVDC converters and FACTS controllers, the voltage ratings of power semiconductor
devices still are not sufficient to meet the required voltage levels by one single-module of
a two-level VSC. To meet high voltage/power levels, multi-level and multi-module VSC
configurations are the options [1]–[3]. The main features of these two configurations, as
compared with the two-level VSC, are their capabilities to reduce (i) harmonic distortion
of the AC-side waveforms, (ii) dv/dt switching stresses, and (iii) switching losses.
In the technical literature, three different types of multi-level topologies, i.e. the
Diode-Clamped Converter (DCC), the capacitor-clamped converter, and the cascaded
H-bridge converter with separated DC sources have been proposed [4]–[7]. Applications
of the capacitor-clamped converter are limited since the clamping capacitors result in
a bulky and expensive converter system. The cascaded H-bridge converter needs DC
sources and is more attractive for applications that include isolated DC sources, i.e.
fuel cells and photovoltaic energy sources. The multi-level DCC is the most promising
topology among the three, particularly for electric power transmission and distribution
applications. The multi-level DCC does not have the limitations associated with the

1
Chapter 1. Introduction 2

other two topologies [4]. However, the DC-side capacitor voltage drift phenomenon of an
n-level DCC, particularly for n > 3, is a challenging task under both steady-state and
transient conditions.
The existing Pulse-Width Modulation (PWM) strategies for a multi-level DCC are
based on (i) selective harmonic elimination techniques [8]–[10], (ii) Sinusoidal PWM
(SPWM) techniques [4], and (iii) Space Vector Modulation (SVM) techniques. Among
the PWM strategies, the SVM techniques are the preferred switching strategies for a
multi-level DCC, particularly in view of their inherent properties for digital implemen-
tation. However, in the context of a multi-level DCC, the existing SVM strategies do
not offer (i) computationally efficient algorithms for real-time implementation, (ii) ca-
pabilities to counteract DC-capacitor voltage drift phenomenon, and (iii) the minimum
switching frequency [11]–[14]. The first objective of this thesis is to propose and develop
a computationally efficient SVM strategy that (i) enables mitigation of the DC-capacitor
voltage drift phenomenon, and also (ii) provides minimum DCC switching frequency
(losses).
Multi-module VSC configurations, from the viewpoint of power circuitry and switch-
ing technique, are classified into two major categories [3], i.e. the multi-pulse VSC
system [3] and PWM-based multi-module VSC system [15]. A multi-pulse VSC offers (i)
higher degree of utilization of DC-side voltage, (ii) minimum switching losses, and (iii)
low order harmonic elimination capability [16]. The drawbacks of a multi-pulse VSC are
(i) the need for complicated phase-shifting transformer windings, and (ii) lack of modu-
larity since the transformers are not identical [3]. A PWM-based multi-module VSC can
overcome the limitations of a multi-pulse VSC. In this thesis we only consider “PWM-
based multi-module VSC” systems, and hereinafter we refer to them as “multi-module
VSC” systems.
In a multi-module VSC system, multiples of identical n-level VSC modules are con-
nected in series [15],[17],[18]. The existing multi-module VSC systems are based on either
two-level VSC units [15] or n-level (n ≥ 3) DCC units [11],[17],[18]. The AC-side voltages
of the VSC modules are added up through identical transformers to generate a multi-level
AC-side voltage waveform. A multi-module VSC system offers (i) full modular design
and scalability, and (ii) equal loss of semiconductor switches [3]. To minimize losses of a
multi-module VSC system, the switching frequency of the VSC modules has to be at the
lowest possible value. However, low switching frequency generates low-order harmonics
at the AC-side voltages of the individual modules. To avoid low-order harmonic filtering
Chapter 1. Introduction 3

and improve the AC-side voltage waveform of a multi-module VSC system, harmonic
cancellation/minimization strategies are required.
The existing PWM strategies that provide harmonic cancellation/minimization for a
multi-module VSC system are based on the phase shifted carrier SPWM techniques [15].
Although SVM switching strategies are conceptually the preferred PWM strategies for
a VSC module, they have neither been used nor considered for multi-module VSC sys-
tems since the existing SVM strategies cannot offer harmonic cancellation/minimization.
A SVM strategy with a low switching frequency and without any harmonic cancella-
tion/minimization capability deteriorates the AC-side voltage of a multi-module VSC
system and necessitates low-order filtering. A SVM switching strategy that (i) provides
a low switching frequency and, (ii) provides harmonic cancellation/minimization for a
multi-module VSC system has not been reported in the technical literature. This thesis
also provides a SVM switching strategy, for a multi-module VSC system composed of
two-level VSC units, with the capability to cancel/minimize low-order harmonics based
on a low switching frequency.

1.2 Thesis Objectives

The main objectives of this thesis are:

1. To propose a SVM-based DC-capacitor voltage balancing strategy that mitigates/

prevents the capacitor voltage drift phenomenon of (i) a passive-front-end DCC,
i.e. a DCC that is supplied by a single DC source, and (ii) a back-to-back con-
nected DCC system, without the need for external power circuitry. In addition,
since adequate saving of processor execution time, in each sampling period of the
SVM is required to perform DC-capacitor voltage balancing task, a computationally
efficient SVM strategy should also be developed.

2. To propose a SVM strategy for a multi-module VSC system to (i) maximize the
fundamental component of AC-side voltage, (ii) minimize harmonic distortions, and
(iii) minimize the switching frequency and consequently the switching losses.

Technical feasibilities of the proposed SVM strategies for a five-level DCC and a four-
module VSC system are investigated and validated in the context of STATCOM and
back-to-back HVDC system applications.
Chapter 1. Introduction 4

1.3 Background

1.3.1 Multi-Level DCC

The three-level DCC, also known as Neutral-Point Clamped (NPC) converter [19], has
been extensively investigated as an alternative to the conventional two-level VSC, for
industrial, transmission and distribution systems applications. Modeling, control and
analysis of the three-level DCC for such applications have been reported in the technical
literatures [11], [20]–[29]. Furthermore, the voltage drift phenomenon of DC-capacitors
of a three-level DCC has been extensively investigated, and correspondingly various re-
medial measures proposed/implemented to resolve the issue [20]–[28].
For high-power applications, a five-level DCC (or an n-level, n > 5) is more attractive
due to its capability to operate at a higher voltage level and to provide waveforms with
lower Total Harmonic Distortion (THD) contents. In addition, the five-level DCC obvi-
ates/minimizes the interface transformer. This unique feature reduces the overall system
volume and footprint which is of importance for some applications.
Despite merits of a five-level DCC for high power/voltage applications, its capacitor
voltage drift phenomenon has been neither comprehensively formulated/analyzed nor
the corresponding remedial measures fully developed. Unlike a three-level DCC, the DC
capacitor voltage drift phenomenon of a five-level DCC is application (load) dependent
and, thus, its mitigation/prevention not a straightforward task [30]–[32]. When the
DCC exchanges non-zero real power, the average values of the DC capacitor currents
are not zero values and lead to the voltage drift of the DC capacitors. The voltage drift
phenomenon deteriorates the AC-side voltage waveforms and consequently results in the
operational failure of the DCC, if not counteracted.
In the technical literature, the DC-capacitor voltage balancing of a n-level DCC
(n > 3) has been proposed based on the following approaches:

• The first approach proposes separate DC sources, one per capacitor, to maintain
the capacitor voltages [33]. The DC sources are usually provided by transformers
through diode bridge rectifiers. Such a supply system is large, heavy, inefficient,
expensive and potentially with adverse impacts on the power quality of the prime
power supply.

• The second approach is based on an auxiliary converter to inject current compo-

nents in the DC-side intermediate branches of the DCC to balance the DC-side
Chapter 1. Introduction 5

voltages [34]–[44]. The main shortcoming of this approach is the need for addi-
tional power hardware which adds to the system cost and complexity, particularly
at high voltage/power levels.

• The third approach proposes modification of the DCC switching pattern, according
to a control strategy, to balance and maintain the DC-capacitor voltages [14], [45],
[46]. Although this approach requires a more elaborate switching strategy/algorithm
as compared with the previous methods, it provides an economically viable ap-
proach to address the main technical issue of the DCC. However, the existing
approach for a five-level DCC is based on off-line calculations that need look-up
tables and practically may not be achievable or enforced. In this thesis, we propose
an on-line strategy, based on the modification of the DCC switching pattern, to
equalize the DC-capacitor voltages of a five-level DCC.

As compared with the multi-level PWM strategies [11], [47], the SVM methods pro-
vide flexibility to select and optimize switching patterns to (i) minimize harmonics, (ii)
modify the switching pattern to carry out DC-capacitor voltage balancing task with no
requirement for additional power circuitry, and (iii) minimize switching frequency for
high power applications. However, real-time implementation of the conventional SVM
strategies is faced with time limits due to the calculation overhead time. Therefore,
fast algorithms are required to overcome complexity of calculations. A fast SVM al-
gorithm can save the processor execution time to perform the required calculations of
DC-capacitor voltage balancing task.
Several SVM algorithms, with low computational burden and simplified calculations,
have been proposed and reported in the technical literature [48]–[51]. In [49] a new
coordinate system is constructed to simplify the calculations. However, the algorithm
has not been augmented with a voltage balancing strategy and it is not clear if it is able
to carry out the voltage balancing task over a reasonable SVM sampling period. Another
modified SVM algorithm for the three-level DCC is proposed in [50]. This algorithm
is based on decomposition of the SVM hexagon diagram of a three-level converter into
that of a two-level converter. Although, the decomposition method can be extended for
higher level DCCs, the computational cost is noticeably increased with the number of
levels [51].
A fast Neural Network (NN)-based SVM algorithm, based on a classification tech-
nique, for the conventional two-level converter is developed in [52]. The algorithm uses a
Chapter 1. Introduction 6

simple classifier NN to identify the switching vectors and calculate their duty cycles with
no requirement to trigonometric functions. In this thesis, we generalize the NN-based
SVM algorithm of [52] for a n-level DCC [53] to significantly reduce the computational
overhead time of the SVM algorithm. Furthermore, the generalize algorithm is aug-
mented with an online DC capacitor voltage balancing approach to prevent the voltage
drift phenomenon of both a passive-front-end DCC and a back-to-back connected DCC
system, with no requirement for additional power circuitry [54].
Applications of a n-level (n > 3) DCC for transformerless STATCOM systems [39],
[44], [55] and back-to-back connected DCC units for AC motor drives [34], [38], [56] have
been reported in the technical literature. Nevertheless, neither of them provides a com-
prehensive dynamic model nor a systematic approach to its control design. Furthermore,
a n-level DCC has neither been investigated nor studied as a back-to-back HVDC system.
In this thesis, the technical feasibility of the proposed SVM switching strategy and the
balancing approach is investigated for a five-level DCC in the context of a STATCOM [57]
and a back-to-back HVDC system [58]. The investigations also include development of
dynamic models of the corresponding study systems and design of controllers.

1.3.2 Multi-Module VSC

For very high-power applications, a multi-module VSC system is another alternative, and
potentially preferable, to a multi-level DCC [3]. A multi-module VSC is the preferred
potential candidate for HVDC system applications [15]. The most interesting aspect of a
multi-module HVDC system lies in its modularity and its potential for use in extra high-
power applications. Capability of a multi-module VSC to handle high power/voltage
indicates that a multi-module HVDC system can be an option to accommodate VSC-
based HVDC systems at ultra high power and voltage ratings, e.g. at the voltage level
of ±800 kV and power ratings above 3,000 MW [59]–[62].
The AC-side voltage waveform of a multi-module VSC system is a multi-level wave-
form with a low harmonic dostortion content provided that an appropriate harmonic can-
cellation/minimization technique is used. A harmonic cancellation/minimization tech-
nique introduces appropriate phase shifts among the same-order harmonics of individual
modules, while the fundamental voltage components of all modules are kept in phase.
Therefore, a set of harmonics are cancelled out/minimized when the module voltages
are added up by the interface transformers. Harmonic cancellation/minimization for a
Chapter 1. Introduction 7

multi-module VSC system is conventionally achieved based on the phase-shifted carrier

SPWM techniques [15], [18], [63]. The main feature of this strategy is its simplicity for
implementation. Its main drawbacks are that (i) practically it can be used, if the SPWM
frequency modulation index is larger than (or at least equal to) 9 which indicates a
relatively high switching frequencies and losses, and (ii) the SPWM inherent per-phase
switching nature results in redundant switchings that also results in switching losses.
The space vector modulation (SVM) is the preferred PWM strategy for low- and
medium-power three-phase VSC units, particularly in view of its inherent property for
digital implementation. However, the conventional SVM methods require relatively high
switching frequency, and thus are not the best option for high power applications. The
concept of a low switching frequency SVM strategy for a multi-module converter system
has been proposed in [64] and [65]. This thesis develops, applies and investigates the low
switching frequency SVM concept of [65] for a multimodule HVDC converter system [66].
The salient features of the proposed SVM strategy are as follows.

• It can operate at switching frequencies lower than that of a phase-shifted carrier

SPWM.

• It can provide appropriate phase shift among the corresponding harmonics of the
VSC modules of a converter for harmonic cancellation/minimization through the
use of identical transformers for the VSC modules, and thus eliminates the need for
complicated transformer windings and enhances modularity of the HVDC converter
structure.

• It guarantees maximum possible ac-side voltage by keeping the fundamental voltage

components of all the VSC modules inphase.

1.4 Thesis Outline

The next six chapters of the thesis are organized as follows:

• Chapter 2 proposes a computationally efficient SVM algorithm, based on a classifier

NN. The principle of the classifier NN for the implementation of SVM strategy of
a two-level VSC is explained and then, the algorithm is generalized for a n-level
DCC. Time-domain simulation results are presented to validate the features of the
proposed SVM strategy.
Chapter 1. Introduction 8

• Chapter 3 analyzes and formulates the voltage drift phenomenon of a passive-

front-end five-level DCC. Chapter 3 also proposes a SVM-based voltage balancing
strategy to counteract the voltage drift phenomenon of a five-level DCC. Capability
of the proposed SVM-based balancing strategy to maintain the capacitor voltages
equal, is evaluated based on time-domain simulation studies.

• Chapter 4 investigates a five-level DCC-based STATCOM that operates based on

the SVM-swiching strategy of Chapter 2 and the DC-capacitor voltage balancing
strategy of Chapter 3. A mathematical model of the STATCOM is developed.
Based on the developed model and the voltage balancing strategy of Chapter 3,
the AC-side current controllers, the DC-bus voltage controller, and the load voltage
controller are designed. Dynamic performance of the STATCOM under different
operating conditions, based on time-domain simulation studies, is also presented.

• Chapter 5 modifies the DC-capacitor voltage balancing strategy of Chapter 3 to bal-

ance the DC-capacitor voltages of a back-to-back, five-level DCC-based HVDC sys-
tem. Chapter 5 also develops a mathematical model for the HVDC system. Based
on the developed model, controllers are designed to control power flow and regulate
DC-bus voltage. Effectiveness of the voltage balancing strategy under steady-state
and dynamic conditions, based on digital time-domain simulation studies is pre-
sented.

• Chapter 6 proposes a SVM-based switching strategy, that is based on a sequential

sampling technique, for a multi-module VSC system. The proposed SVM strategy
is developed for a four-module VSC-based, back-to-back HVDC system which links
two AC systems. Chapter 6 also develops a dynamic model of the HVDC system,
and provides a comprehensive evaluation of the proposed SVM strategy for the
system.

• Chapter 7 concludes the thesis and highlights the contributions.

Chapter 2

SVM Switching Strategy for a

Multi-Level DCC

2.1 Introduction

This chapter proposes a classification algorithm for real-time implementation of a SVM

strategy for a n-level DCC. The proposed algorithm is based on a classifier NN which
provides a computationally efficient and a conceptually simple approach without the use
of trigonometric calculations or look-up tables to identify (i) location of the tip of a ref-
erence voltage vector, (ii) adjacent switching voltage vectors of the reference voltage, and
(iii) on-duration time intervals of the switching voltage vectors. The salient feature of
the proposed algorithm is that it reduces the computational overhead of the SVM. The
algorithm avoids trigonometric calculations for the SVM and the involved calculations
are performed by a NN through simple mathematical operations. Therefore, considerable
reduction in execution time is achieved to fit the entire processing time within a mod-
ulation period for real-time implementation. Thus, adequate time is provided for other
tasks, e.g. sensing control variables, performing command calculations, and achieving
DC-capacitor voltage balancing.

Feasibility of the proposed SVM algorithm is validated based on theoretical analysis

and time-domain simulation studies.

9
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 10

n 1
 V dc  S1
C n1
n 1
 n2 S2
V dc 
n 1
C n 2
 n3

Sn2
S n 1
Vdc

S1
S2

2
V dc 
C
n 1  1 2

V dc  S n2
n 1  C1 S n 1
 0

va vb vc

Figure 2.1: Circuit diagram of a three-phase n-level DCC

2.2 Principles of Operation of a Multi-Level DCC

Fig. 2.1 shows a schematic diagram of a three-phase n-level DCC in which the DC-link
consists of capacitors C1 , C2 , ..., Cn−2 , and Cn−1 [4]. Corresponding to the net DC-link
voltage of Vdc , voltage across each capacitor is ideally Vdc /(n − 1). Each leg of a n-level
DCC consists of 2n−2 switches. There are n−1 complimentary switch pairs in each phase.
For a complimentary switch pair, e.g. S1 and S̄1 , turning on one of the switches excludes
the other from being turned on. Using phase-a as an example, the four complementary
pairs are (S1 , S̄1 ), (S2 , S̄2 ), ..., (Sn−1 , S̄n−1 ). Gating signals S̄1 , S̄2 , ..., S̄n−2 , and S̄n−1 are
generated by inverting S1 , S2 , ..., Sn−2 , and Sn−1 respectively.
There are n switch combinations to synthesize n-level voltages at the AC-side termi-
nals. To synthesize each voltage level, out of 2n − 2 switches in each leg of the DCC of
Fig. 2.1, n − 1 contiguous switches must be in the on-state. Considering voltage of node
“0” as the reference voltage, the switching combinations to synthesize different voltage
levels are summarized in Table 2.1. A functional diagram of the DCC of Fig. 2.1 is shown
by Fig. 2.2 in which each phase is interfaced to the DC-link terminals through a fictitious
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 11

Table 2.1: Switching states of a n-level DCC

Switching S1 S2 ... Sn−2 Sn−1 S̄1 S¯2 ... S̄n−2 S̄n−1 Phase
States Voltage
I 1 1 ... 1 1 0 0 ... 0 0 Vdc
Vdc
II 0 1 ... 1 1 1 0 ... 0 0 (n − 2) n−1
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . .
Vdc
n−2 0 0 ... 0 1 1 1 ... 1 0 2 n−1
n−1 0 0 ... 0 0 1 1 ... 1 1 0

n-pole switch. Sij , i = a, b, c, j = 0, 1, ..., n − 1 is a switching function which denotes the

position of the fictitious n-pole switches. Sij is equal to one, if output i is connected
to voltage level j, otherwise it is zero. Considering the lower DC-side voltage level as
zero, “0” level in Fig. 2.2, the AC-side voltage is defined by a specific number of series
capacitor voltages and expressed as
n−1
X j
X
vi0 = (Sij VCp ), i = a, b, c. (2.1)
j=1 p=1

Ideally, when the DC-capacitor voltages are balanced (equal), (2.1) is simplified to
Vdc n−1
X
vi0 = (jSij ), i = a, b, c, (2.2)
n − 1 j=1
which denotes a staircase, i.e. an n-level, symmetric waveform.

2.3 SVM for a n-level DCC

2.3.1 Space Vector Plane, Sectors, and Switching Vectors

Since there are n distinct switching states for each phase of the converter of Fig. 2.2,
the total number of switching state vectors is n3 . Each switching state is represented
by (i, j, k) where i, j, k ² [0, 1, ..., n − 1], and defines appropriate connection of n-pole
switches of the three phases. For example switching state (n − 1, n − 2, 1) denotes the
state in which Sa(n−1)=1 , Sb(n−2)=1 and Sc1 = 1.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 12

n 1
 V dc 
C n1
n 1
 n2 Sa ( n2) S a ( n1)

V dc 
C n2
n 1
 n3 Sa 0

Sb ( n 2) Sb ( n 1)
V dc

Sb 0

2 Sc ( n2) S c ( n 1)
V dc
C2
n 1 
1
Sc 0
V dc 
C1
n 1 
 0

va vb vc

Figure 2.2: A schematic representation of the n-level DCC of Fig. 2.1 based on n-pole
fictitious switches

A set of balanced three-phase voltages in abc frame can be transformed into a two-
dimensional αβ complex frame by the following transformation [67]
  
 
vα 
1 −1/2 −1/2   va 
 = √ √  
vb  , (2.3)
  
vβ 0 3/2 − 3/2
vc
where va , vb , and vc are the three-phase voltages in the abc frame, and vα and vβ are
the corresponding voltages in the αβ plane. Applying the transformation to the output
phase voltages corresponding to the n3 switching states results in a set of switching
voltage vectors that form a (n − 1)-layer hexagon centered at the origin of the αβ plane,
and n zero voltage vectors located at the origin, Fig. 2.3. The hexagon is divided into
six 60◦ sectors specified by I to VI.
Projection of three-phase reference voltages into the αβ plane is a vector called the
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 13

vE
SectorII
Upper limit of linear
modulation (m=1)

SectorIII 4-level SectorI

3-level
V ref
2-level

T vD

SectorIV SectorVI

SectorV

Figure 2.3: Representation of space voltage vectors of a n-level DCC in αβ plane

reference voltage vector, Vref , with a constant magnitude. Vref rotates counterclockwise
with a constant angular frequency of ω as shown in Fig. 2.3. Fig. 2.4 shows sector I of
the hexagon. Each sector includes (n − 1)2 equilateral triangles.

2.3.2 Conventional SVM Algorithm

A SVM is a discrete type of modulation technique in which a sampled reference vector,

Vref , is synthesized by the time average of a number of appropriate switching state vectors.
When the reference voltage vector, Vref , is located in sector I, at any sampling instant the
tip of the voltage vector lies in a triangle formed by the three switching vectors adjacent
to it, Fig. 2.3, which constitute the best set of vectors to synthesize the reference voltage
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 14

vE (
Vdc 3Vdc
, )
2 2

(n  2)Vdc (n  2) 3Vdc
( , )
2( n  1) 2( n  1)

I
...

3Vdc 3 3Vdc
( , )
2(n  1) 2(n  1)

Vdc 3Vdc
( , )
(n  1) (n  1) p j,2

Vdc 3Vdc pj p j ,1
( , )
2(n  1) 2(n  1)

T vD
0 1
n 1
Vdc
2
n 1
V dc
3
n 1
Vdc
4
n 1
Vdc ... n2
n 1
Vdc Vdc

Figure 2.4: First sector corresponding to the space voltage vectors of an n-level DCC

vector based on

pj dj + pj,1 dj,1 + pj,2 dj,2 = Vref · T, dj + dj,1 + dj,2 = T, (2.4a)

Vref = |Vref |ejθ , θ = 6 Vref , (2.4b)
2 |Vref |
m= √ , (2.4c)
3 Vdc
where T is the switching period, m is the modulation index, pj , pj,1 and pj,2 are the
three switching vectors adjacent to the reference voltage vector, and dj , dj,1 and dj,2 are
the calculated duty cycles of the switching vectors, respectively. The same applies when
the tip of the reference voltage is in the other sectors. Based on Fig. 2.3, a reference
√
voltage magnitude of 3Vdc /2 corresponds to the maximum fundamental component of
the AC-side voltage obtained in the linear mode, that is m = 1.
In the conventional SVM strategy, the coordinates of each switching vector in the
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 15

cartesian coordinates system, i.e. vα and vβ , are calculated by

vb + vc
vα = (va − ), (2.5a)
√ 2
3
vβ = (vb − vc ). (2.5b)
2

The coordinates of space voltage vectors are shown in Fig. 2.4. Depending on the
position of the reference vector and the triangle in which the tip of the vector is lo-
cated within, Fig. 2.4, the on-duration time intervals of appropriate switching vectors
are calculated from the solution of (2.4).
Computational burden to synthesize a reference voltage is mostly associated with
trigonometric calculations for (i) identification of the sector and the triangle in which
the tip of the reference vector is located within, (ii) selection of appropriate switching
voltage vectors, and (iii) calculation of on-duration time intervals of switching voltage
vectors. Moreover, as the triangle in which the tip of the reference vector is located
within changes, the equations used for the calculations of the on-duration time intervals
are changed. Thus, in the conventional SVM strategy, each triangle has its own equa-
tions for calculation of the on-duration time intervals. Therefore, as the number of levels
of a DCC increases, the computational burden and the complexity of calculations sig-
nificantly increase. The following section shows that the aforementioned computational
requirement can be substantially reduced by means of a general classification technique.

2.4 Proposed SVM Algorithm

Reference [52] demonstrates that a SVM algorithm for a conventional two-level converter
can be developed by means of a classification algorithm based on Kohonen’s competitive
NN. Kohonen’s competitive NN classifies a group of input vectors into a number of class
vectors in its training mode, and assigns a class vector to an input vector in its recalling
mode [68]. Since a SVM is a deterministic process and all class vectors are known in
advance in the Kohonen’s competitive NN, there is no need to train the NN. This salient
feature is exploited to develop a fast and simple NN-based SVM algorithm. The following
section utilizes the advantage of this feature and presents a real-time computing approach,
based on a classification algorithm, to intelligently identify the desired switching voltage
vectors and calculate the corresponding on-duration time intervals.
 Chapter 2. SVM Switching Strategy for a Multi-Level DCC 16

Neurons

n1
1 1 i
Sector number

-0 -0.5
Decoder

.5
Inputs 0 .5
n2 i 1
0 .5
2
-1
varef -0.5
n3 Proposed
1
5
3
-0. Competitive
vbref 0.5
-1
n4 Neural
0.5 4
-0. Network
5
vcref -0.5
n5 ni
1
5
0.5
0.5
-1 ni1
n6
6

Figure 2.5: Schematic diagram of the classification algorithm

2.4.1 Fast SVM Algorithm Based on Kohonen’s Competitive

NN
Fig. 2.5 shows principles of the proposed classification algorithm to efficiently realize
a SVM algorithm for a 2-level converter [52]. A reference vector is applied to a NN
composed of six computational units, where each unit is associated with a predetermined
gain vector. The output of the kth unit is the inner product of the reference vector and
the kth switching state vector, Fig. 2.6(a), that is

nk = |Vref ||Vk | cos(6 Vref , Vk ), f or k = 1, 2, ..., 6. (2.6)

In a SVM algorithm for a 2-level converter, out of six class vectors, the two closest vectors
to Vref must be specified, therefore, the proposed competitive NN has two “winners”.
Without the loss of generality we can assume that all vectors are normalized and thus
inner product (2.6) can be rewritten as

nk = |Vref | cos(θk ). (2.7)

Equation (2.7) indicate that the closest Vk to Vref generates the largest nk . The largest
nk and the second largest nk uniquely specify the two space voltage vectors adjacent to
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 17

E
V3 V2

Vref
V7
V4 V1
T D
V8

V5 V6

(a)

Vi1

ni1
Vref
60 T
T Vi
ni

(b)

Figure 2.6: Representation of the reference vector and switching vectors of a 2-level
converter in the αβ plane: (a) all sectors, (b) the winners of the competition

Vref . Therefore, for example if reference vector Vref lies in the sector delimited by Vi and
Vi+1 , among all nk , k = 1, 2, ..., 6, ni and ni+1 have the largest positive values. Thus, if
the competitive NN selects the two largest nk ’s as its two winners, i.e. ni and ni+1 , the
two switching vectors which synthesize the output voltage are Vi and Vi+1 , Fig. 2.6(b).
The corresponding indices of ni and ni+1 , i.e. the class numbers i and i + 1, specify the
sector number in which the tip of Vref is located within.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 18

Equation (2.8) is a generalized matrix form of (2.7) for all switching states of a two-
level VSC
   
n
 1 
V
 1 
   
 n2   V2 
   
   
 n   V 
 3   3 
 = V , (2.8)
 n   V  ref
 4   4 
   
   
 n5   V5 
   
n6 V6

where Vk , k = 1, 2, ..., 6 for a two-level VSC is presented in Table 2.2. Substituting for

Table 2.2: Switching states and corresponding space voltage vectors

State(k) va vb vc Vk
1 Vdc 0 0 Vdc
√
2 Vdc Vdc 0 (1/2 + j 3/2)Vdc
√
3 0 Vdc 0 (−1/2 + j 3/2)Vdc
4 0 Vdc Vdc −Vdc
√
5 0 0 Vdc -(1/2 + j 3/2)Vdc
√
6 Vdc 0 Vdc (1/2 − j 3/2)Vdc
7 Vdc Vdc Vdc 0
8 0 0 0 0

Vk from Table 2.2 and Vref from (2.3) in (2.8), we deduce

   
n
 1  
1 −1/2 −1/2 
     
 n2   1/2 1/2 −1 
  V  
   aref   
 n     −1/2 1 −1/2 
 3   
 =W
 Vbref
,
 W = . (2.9)
 n     −1 1/2 1/2 
 4   
  Vcref  
  
 n5   −1/2 −1/2 1  
   
n6 1/2 −1 1/2

Matrix W is the predetermined gain vectors shown in NN of Fig. 2.5.

Based on the proposed classification technique, the inner product between reference
vector Vref and a switching class vector Vk is readily obtained by a linear combination of
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 19

the three input voltage references, Fig. 2.5. The outputs of the winner units, Fig. 2.6(b),
are
   
ni cos(θ)
  = |Vref |  . (2.10)
◦
ni+1 cos(60 − θ)
The terms cos θ and cos(60◦ − θ) of (2.10) can also be expressed as
    
cos(θ) 1 2 1 sin(60◦ − θ)
 = √   . (2.11)
cos(60 − θ) 3 1 2 sin(θ)
Substituting for cos θ and cos(60◦ − θ) from (2.10) in (2.11), and rewriting (2.11), we
deduce
    
sin(60◦ − θ) 1 2 −1 ni
 = √   . (2.12)
sin(θ) 3|Vref | −1 2 ni+1
In the following section, we show that the proposed classification algorithm can be ex-
tended to develop a universal fast SVM algorithm for a DCC with an arbitrary number of
levels. Equations (2.10) and (2.12) will be used to alternatively express the on-duration
time intervals of the switching state vectors in terms of the outputs of the competitive
neural network, ni and ni+1 .

2.4.2 Determination of Reference Vector Location

Location of a reference voltage vector is readily identified based on using the competitive
NN of Fig. 2.5. Based on ni and ni+1 from Fig. 2.5, the corresponding index of ni
(i) represents the sector number. For triangle identification, reference vector Vref is
projected on the axes of 60◦ coordinate system. The projected components are Vref (ni)
and Vref (ni+1) which are expressed by,
Vref
Vref cos(θ) − √
3
sin(θ)
Vref (ni) = , (2.13a)
Vdc /(n − 1)
Vref
Vref cos(60 − θ) − √
3
sin(60 − θ)
Vref (ni+1) = . (2.13b)
Vdc /(n − 1)
Substituting for trigonometric functions cos(θ), sin(θ), cos(60 − θ), and sin(60 − θ) in
(2.13) in terms of ni and ni+1 from (2.10) and (2.12), we deduce
2(n − 1)
Vref (ni) = (2ni − ni+1 ), (2.14a)
3Vdc
2(n − 1)
Vref (ni+1) = (−ni + 2ni+1 ). (2.14b)
3Vdc
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 20

vni1
(0,n-1)

(0,n-2) (1,n-2)

(2,n-3)

(0,5)

(0,4) (1,4) n 1 n 1
( , )
2 2

(0,3) (1,3) (2,3)

ni1
(1,2)
C D (3,2)
(0,2) (2,2) (n-3,2)
Vref ( ni1) Vref

(0,1) (1,1) (2,1) (3,1) (4,1) (n-2,1)

A B

(2,0) ni (5,0) (n-2,0) (n-1,0)

vni
(0,0) (1,0) Vref ( ni ) (3,0) (4,0)

Figure 2.7: Space vector representation of an n-level DCC in the first sector

Fig. 2.7 shows the projected space voltage vectors of sector I of Fig. 2.4 based on
(2.14). The tip of the reference vector lies in a parallelogram formed by vertices A, B, C,
and D in Fig. 2.7. We call

l1 = int(Vref (ni) ), (2.15a)

 Chapter 2. SVM Switching Strategy for a Multi-Level DCC 21

l2 = int(Vref (ni+1) ). (2.15b)

where int() is a lower rounded integer function.

Thus, coordinates of vertices A, B, C, and D are

(VA(ni) , VA(ni+1) ) = (l1 , l2 ), (2.16a)

(VB(ni) , VB(ni+1) ) = (l1 + 1, l2 ), (2.16b)
(VC(ni) , VC(ni+1) ) = (l1 , l2 + 1), (2.16c)
(VD(ni) , VD(ni+1) ) = (l1 + 1, l2 + 1). (2.16d)

The following criterion determines if the reference vector is located in a triangle formed
by either A, B, and C or B, C, and D vertices.

Vref is in ABC triangle if : Vref (ni) + Vref (ni+1) < l1 + l2 + 1 (2.17a)

Vref is in BCD triangle if : Vref (ni) + Vref (ni+1) ≥ l1 + l2 + 1 (2.17b)

2.4.3 Duty-Cycle Calculations

On-duration time intervals of the switching voltage vectors adjacent to the reference
voltage vector Vref of a n-level DCC are calculated as follows. If the tip of the reference
voltage vector lies in the ABC triangle, Fig. 2.7, according to (2.4) we have

VA dA + VB dB + VC dC = Vref T,
(2.18)
dA + dB + dC = T,

where dA , dB , and dC are the duty-cycles of switching vectors VA , VB , and VC , respectively.

Expressing (2.18) based on vni - and vni+1 -axis components in the 60◦ coordinates system,
Fig. 2.7, we deduce

VA(ni) dA + VB(ni) dB + VC(ni) dC = Vref (ni) T,

VA(ni+1) dA + VB(ni+1) dB + VC(ni+1) dC = Vref (ni+1) T, (2.19)
dA + dB + dC = T.

Substituting for vni - and vni+1 -axis components of VA , VB , and VC from (2.16) in (2.19),
the on-duration time intervals are

dB = (Vref (ni) − VA(ni) )T,

dC = (Vref (ni+1) − VA(ni+1) )T, (2.20)
dA = T − (dB + dC ).
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 22

Similarly, if the tip of the reference voltage vector lies in the BCD triangle, the duty
cycles of switching vectors VB , VD , and VC are

dB = (VA(ni+1) + 1 − Vref (ni+1) )T,

dC = (VA(ni) + 1 − Vref (ni) )T, (2.21)
dD = T − (dB + dC ).

The significant outcome of the proposed algorithm is its inherent simplicity. Unlike
the conventional SVM algorithm that requires solution of several sets of trigonometric
equations for calculation of on-duration time intervals, (2.20) and (2.21) only depend
on two sets of equations to determine the on-duration time intervals. Therefore, the
proposed SVM algorithm is much simpler and easier for digital implementation since it
reduces the hardware and software complexity and decreases the required computational
time.

2.4.4 Determination of Switching States Corresponding to Switch-

ing Vectors
The last step of the proposed algorithm is to identify switching states that correspond
to the already determined three adjacent voltage vectors, Section 2.4.2. The adjacent
switching vectors in the 60◦ coordinates system of Fig. 2.7 are the coordinates of the
vertices of the triangle in which the tip of Vref is located within. For a given adjacent
switching vector known by coordinates (vni , vni+1 ), the available switching states are
determined by

(i, j, k) = (h, h − vni , h − vni − vni+1 ) , (2.22)

where h, h − vni , h − vni − vni+1 ²{0, 1, 2, ..., n − 1}.

Based on (2.22), some of the switching vectors correspond to more than one state,
i.e. there exist redundant switching states. Redundant switching states can be used to
carry out DC-capacitor voltages balancing task for an n-level DCC which is the subject
of the next chapter.
As discussed in Section 2.4.2, the proposed SVM algorithm inherently maps all sectors
to the 60◦ coordinates system of sector I. Thus, the determined switching states are based
on the switching states of sector I. At any instant the number of sector in which the
reference vector is located within is identified by the output of the NN block of Fig. 2.5.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 23

Table 2.3: Relationship between switching states in sectors I to VI

Sector Phase A Phase B Phase C

I i j k
II −j + (n − 1) −k + (n − 1) −i + (n − 1)
III k i j
IV −i + (n − 1) −j + (n − 1) −k + (n − 1)
V j k i
VI −k + (n − 1) −i + (n − 1) −j + (n − 1)

Therefore, the corresponding switching states to switching vectors in other sectors are
determined simply by interchanging the switching states of sector I determined by (2.22).
Table 2.3 provides the corresponding switching states of the DCC in all sectors.
Unlike other fast NN-based algorithms [69], [70], sector identification is an inher-
ent feature of the proposed classification technique. This salient feature is particularly
advantageous for voltage balancing of DC-capacitors.
The implementation procedure of the proposed SVM algorithm is summarized in the
diagram of Fig. 2.8. To implement the SVM method the following steps are taken:

• According to (2.9), nk , k = 1, 2, ..., 6, is calculated.

• The two largest ni and ni+1 and their corresponding indices, i and i + 1 are deter-
mined by the competitive NN. This also specifies the sector number.

• The triangle in which the tip of Vref is located within, and also the three adjacent
two-dimensional space voltage vectors are determined by (2.11) to (2.17).

• The on-duration time intervals of the adjacent switching voltage vectors are calcu-
lated by either (2.20) or (2.21).

• The switching state combinations corresponding to the determined adjacent voltage

vectors are identified for the overall αβ plane, Section 2.4.4.
 Chapter 2. SVM Switching Strategy for a Multi-Level DCC 24

Neurons

n1 Sector identification
1 1 i

- 0 - 0 .5
Decoder

.5
Inputs 0 .5
n2 i 1
0.5
2
-1
varef -0.5
n3
1
5
3 Proposed
-0.
vbref 0.5
-1
n4
Competitive
0.5 4 Network Reference vectror
-0.
5 location identification
vcref -0.5
n5 ni
1
5 Mathematical
0.5
0.5
-1 ni1 Computations
n6 in (2.14) to (2.17)
6

Switching vector
Duty cycle Calculation
combinations based on
in (2.20) and (2.21)
(2.22) and Table 2.3

switching
pattern
generator

Gating Signals

Figure 2.8: Schematic diagram of the classification algorithm for a multi-level DCC

2.4.5 Study Results

To demonstrate feasibility of the proposed SVM algorithm, a set of MATLAB/SIMULINK

based simulation studies are conducted. To show that the proposed algorithm is feasible
for a DCC with an arbitrary number of levels, it is applied to a three-level, a four-level,
and a five-level DCC.
The simulation results of a three-level DCC for different values of modulation index,
m, and switching frequency of fsw = 2.88 kHz, are presented in Figs. 2.9 to 2.11. Each
figure depicts the AC-side voltage waveform normalized with respect to the DC-side
voltage, Vdc . Fig. 2.9 shows simulated waveform of the AC-side voltage for m = 0.8.
Fig. 2.9 indicates that the voltage has three distinct levels. The simulation waveforms
of Figs. 2.9 to 2.11 demonstrate feasibility of the proposed classification algorithm for
real-time implementation.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 25

Figs. 2.12 to 2.17 show the MATLAB/SIMULINK based simulation results for four-
and five-level DCCs, and for different modulation indices at the switching frequency of
fsw = 2.88 kHz. Figs. 2.12 to 2.14 show the AC-side voltage waveforms of a four-level
DCC for m = 0.8, m = 0.6, and m = 0.4, respectively, and Figs. 2.15 to 2.17 show
the corresponding waveforms of a five-level DCC. The multi-level voltage waveforms of
Figs. 2.12 to 2.17 show are consistent with the analytical waveforms and demonstrate
feasibility of the proposed algorithm for DCCs with different number of levels. The
improvement in the calculation overhead time is more significant as the number of levels
increases. The reason is that unlike the conventional algorithm, the proposed SVM
algorithm is independent of the number of DCC levels.

2.5 Summary and Conclusions

A classification algorithm for real-time implementation of a SVM strategy for a n-level
DCC is proposed in this chapter. The algorithm uses a simple classifier NN to (i) identify
the sector in which the tip of reference vector is located within, (ii) identify the adjacent
switching vectors and their corresponding switching states, and (iii) calculate their on-
duration time intervals. The principle of the classifier NN is explained and based on
that basis a generalized, computationally efficient algorithm is developed to simplify the
mathematical calculations of a SVM strategy for a n-level DCC. Although the proposed
algorithm is a NN-based algorithm, it does not need a training stage. The reason is that
a SVM algorithm is a deterministic process and therefore the weight coefficients of the
NN are known in advance.
The validity of mathematical analysis and the feasibility of the proposed algorithm
are verified by time-domain simulation studies in the MATLAB/SIMULINK environment
for a n-level (n = 3, 4, 5) DCC.
The following conclusions are obtained from the results:

• The proposed SVM switching strategy eliminates calculations of the time consum-
ing trigonometric functions that are required for the implementation of conventional
SVM switching strategies. Using the proposed SVM algorithm, the whole proce-
dure for implementation of the algorithm is carried out by simple mathematical
operations, i.e. “ + ”, “ − ”, “ × ”, and “ ÷ ”. Therefore, hardware and software
complexity of the SVM algorithm are substantially reduced.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 26

• The proposed algorithm improves the calculation overhead time of the SVM strat-
egy for real-time implementation and saves sufficient processor execution time to
carry out other time-consuming tasks, e.g. capacitor voltage balancing task. This
feature is of crucial importance in particular, for a n-level DCC (n > 3), e.g. a
five-level DCC, in which the number of redundant switching states are significant
and the task of capacitor voltage balancing requires considerable calculation time.

• The proposed algorithm is a general algorithm for an n-level DCC and does not
need any modification as the number of levels increases. This is a salient feature of
the algorithm that becomes more advantageous as the number of levels increases.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 27

0.8

0.6

0.4

Line voltage(pu)
0.2

−0.2

−0.4

−0.6

−0.8

−1
0 5 10 15 20 25 30 35 40

Figure 2.9: AC-side voltage waveform of a 3-level DCC; m = 0.8, fsw = 2880Hz.

0.8

0.6

0.4
Line voltage(pu)

0.2

−0.2

−0.4

−0.6

−0.8

−1
0 5 10 15 20 25 30 35 40

Figure 2.10: AC-side voltage waveform of a 3-level DCC; m = 0.6, fsw = 2880Hz.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 28

0.8

0.6

0.4
Line voltage(pu)

0.2

−0.2

−0.4

−0.6

−0.8

−1
0 5 10 15 20 25 30 35 40

Figure 2.11: AC-side voltage waveform of a 3-level DCC; m = 0.4, fsw = 2880Hz.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 29

0.8

0.6

0.4

Line voltage(pu)
0.2

−0.2

−0.4

−0.6

−0.8

−1
0 5 10 15 20 25 30 35 40

Figure 2.12: AC-side voltage waveform of a 4-level DCC; m = 0.8, fsw = 2880Hz.

0.8

0.6

0.4
Line voltage(pu)

0.2

−0.2

−0.4

−0.6

−0.8

−1
0 5 10 15 20 25 30 35 40

Figure 2.13: AC-side voltage waveform of a 4-level DCC; m = 0.6, fsw = 2880Hz.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 30

0.8

0.6

0.4
Line voltage(pu)
0.2

−0.2

−0.4

−0.6

−0.8

−1
0 5 10 15 20 25 30 35 40

Figure 2.14: AC-side voltage waveform of a 4-level DCC; m = 0.4, fsw = 2880Hz.

0.8

0.6

0.4
Line voltage(pu)

0.2

−0.2

−0.4

−0.6

−0.8

−1
0 5 10 15 20 25 30 35 40

Figure 2.15: AC-side voltage waveform of a 5-level DCC; m = 0.8, fsw = 2880Hz.
Chapter 2. SVM Switching Strategy for a Multi-Level DCC 31

0.8

0.6

0.4

Line voltage(pu) 0.2

−0.2

−0.4

−0.6

−0.8

−1
0 5 10 15 20 25 30 35 40

Figure 2.16: AC-side voltage waveform of a 5-level DCC; m = 0.6, fsw = 2880Hz.

0.8

0.6

0.4
Line Voltage (pu)

0.2

−0.2

−0.4

−0.6

−0.8

−1

0 5 10 15 20 25 30 35 40

Figure 2.17: AC-side voltage waveform of a 5-level DCC; m = 0.4, fsw = 2880Hz.
Chapter 3

DC-Capacitor Voltage Control of a

Five-Level DCC

3.1 Introduction

The phenomenon of DC-capacitor voltages drift is the main technical drawback of a

passive-front-end n-level (n > 3) DCC. This chapter:

• Analyzes and formulates the DC-capacitors voltage-drift phenomenon of a passive-

front-end, five-level DCC. The analysis shows (i) dependency of the voltage drift
phenomenon on modulation index and AC-side power factor of the SPWM-switched
DCC, and (ii) incapability of a SPWM switching strategy to balance the DC-
capacitor voltages.

• Proposes a SVM-based strategy, based on the switching strategy of chapter 2, to

counteract the voltage drift phenomenon of a five-level DCC. Based on the proposed
switching strategy, a theoretical basis for the SVM-based balancing strategy is
presented and the operational limits are specified.

Performance of a DCC under various operating conditions, based on time-domain sim-

ulation studies in the MATLAB/SIMULINK environment, is evaluated. The studies
demonstrate capability of the proposed SVM balancing strategy to control and maintain
voltage balance of DC capacitors within a specified range.

32
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 33

vC 4 C4
s1
3 s2

vC 3 C3 s3
s4
Vdc
2 v ta
v
vtctb
vC 2 C2 s1
s2
1

vC1 C1
s3
0
s4

Figure 3.1: Schematic representation of passive-front-end five-level DCC

Table 3.1: Switching states of a five-level DCC

Switching States S1 S2 S3 S4 S̄1 S¯2 S¯3 S¯4 Phase Voltage

I 1 1 1 1 0 0 0 0 Vdc
II 0 1 1 1 1 0 0 0 3Vdc /4
III 0 0 1 1 1 1 0 0 Vdc /2
IV 0 0 0 1 1 1 1 0 Vdc /4
V 0 0 0 0 1 1 1 1 0

3.2 Five-Level DCC

3.2.1 Fundamentals of Operation

Fig. 3.1 shows a schematic diagram of a three-phase, passive-front-end, five-level DCC in

which the DC-side consists of capacitors C1 , C2 , C3 and C4 . For a net DC-side voltage
of Vdc , each capacitor voltage is ideally vCj = 14 Vdc , j = 1, ..., 4, and each generated phase
voltage, e.g. vta , has five levels with respect to the voltage of node “0”, i.e. Vdc , 3Vdc /4,
Vdc /2, Vdc /4 and 0. The switching states and the corresponding phase voltages are listed
in Table 3.1, where state conditions 1 and 0 indicate on and off switch status, respectively.
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 34

There are four complimentary switch pairs in each phase. For a complimentary switch
pair, turning on one of the switches excludes the other from being turned on. Using
phase-a as an example, the four complementary pairs are (S1 , S¯1 ), (S2 , S¯2 ), (S3 , S¯3 ), and
(S4 , S¯4 ). Gating signals S¯1 , S¯2 , S¯3 , and S¯4 are generated by inverting S1 , S2 , S3 , and S4
respectively.
Multi-carrier SPWM techniques that have been proposed for a DCC include (i) Phase
Disposition (PD), (ii) Phase Opposition Disposition (POD), and (iii) Alternative Phase
Opposition Disposition (APOD) techniques [71]. The three methods generate similar AC-
side phase and line voltage waveforms. However, the PD technique generates a relatively
lower THD [71].
The PD technique requires four in-phase carrier waveforms displaced symmetrically
with respect to the zero axis [71]. Fig. 3.2 illustrates the SPWM waveforms of phase-a
of the five-level converter of Fig. 3.1. Gating signals S1 , S2 , S3 , and S4 are generated
by comparing the sinusoidal modulating waveform with four carrier waveforms as shown
in Fig. 3.2. The main drawback of a multi-carrier SPWM technique for a DCC is its
inherent incapability to balance DC-capacitor voltages as analyzed in the subsequent
section.

3.2.2 Theoretical Limits to Capacitors Voltage Balancing

DC-capacitor voltages of a DCC deviate from their ideal values and consequently there
is a need to actively balance the DC-capacitor voltages. Capacitor voltage deviations
depend upon the net real power exchange between AC and DC sides of the DCC [30].
Real power transfer leads to current injections through the DC-side intermediate branches
of the converter and causes divergence of capacitor voltages. It has been theoretically
shown that no PWM strategy can guarantee voltage balance of the capacitors of a passive-
front-end DCC with more than three levels, under all possible operating conditions [30].
The limit of the operational region which guarantees balanced capacitor voltage is reached
primarily due to a large modulation index and/or a high AC-side power factor. Fig. 3.3
shows the theoretical limits for which voltage balancing of the capacitors of a passive-
front-end, n-level DCC (n → ∞) can be achieved. Mathematically, the boundary is
defined by [30]
√
3
m= (3.1)
π|cos(φ)|
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 35

0.5

−0.5

−1
π/2 π 3π/2 2π

S1
0
π/2 π 3π/2 2π
1
S2

0
π/2 π 3π/2 2π
1
S3

0
π/2 π 3π/2 2π
1
S4

0
π/2 π 3π/2 2π
1
0.5
Vtab

0
−0.5
−1
π/2 π 3π/2 2π

Angle(rad.)

Figure 3.2: SPWM waveforms of a five-level DCC

where m is the DCC modulation index and cos(φ) is the AC-side power factor. The
shaded area in Fig. 3.3 shows the operating points for which capacitor voltage balancing
is possible. Fig. 3.3 also indicates that a passive-front-end DCC cannot provide voltage
balancing capability under real power conversion conditions, without de-rating the output
voltage, and therefore is more suitable for reactive power compensation.

3.2.3 DC-Capacitor Voltage Drift Phenomenon

The objective of this section is to formulate behaviors of DC-capacitor voltages of a five-

level DCC. An analysis of the five-level DCC of Fig. 3.1 is explained with reference to
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 36

0.9

Modulation Index, m
0.8

0.7

0.6

0.5 Stable Area

0.4
−150 −100 −50 0 50 100 150
Load Current Angle (degrees)

Figure 3.3: Voltage balancing region of a passive-front-end n-level DCC (n → ∞)

idc i4
iC 4
C4
i3 Sa3 Sa4
vta ia
iC 3 Sa2
Sa1 S
a0
C3 Sb3 Sb4
vtb ib
i2 Sb2
Vdc Sb1 S
b0
iC 2 Sc3 Sc4
vtc ic
C2 Sc2
Sc1 S
c0
i1
iC1
C1
i0

Figure 3.4: Schematic representation of the five-level DCC system of Fig. 3.1 based on
five-pole fictitious switches

Fig. 3.4 in which each AC phase is interfaced to the DC terminals through a fictitious
five-pole switch.
The switching functions of the DCC of Fig. 3.4, i.e. Sj0 to Sj4 , j = a, b, c, determine
the relationship between the AC- and DC-side variables. These relations are determined
by switch states of the DCC of Fig. 3.1 as shown in Fig. 3.2. For example for phase-a of
 Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 37

the DCC, we have

Sa4 = S1 S2 S3 S4 ,
Sa3 = S2 S3 S4 S¯1 ,
Sa2 = S3 S4 S¯1 S¯2 , (3.2)
Sa1 = S4 S¯1 S¯2 S¯3 ,
Sa0 = S¯1 S¯2 S¯3 S¯4 .

Voltages and currents of the AC-side of the DCC of Fig. 3.4 are governed by

vta0 = Sa4 (vc4 + vc3 + vc2 + vc1 ) + Sa3 (vc3 + vc2 + vc1 ) + Sa2 (vc2 + vc1 ) + Sa1 (vc1 ), (3.3a)
vtb0 = Sb4 (vc4 + vc3 + vc2 + vc1 ) + Sb3 (vc3 + vc2 + vc1 ) + Sb2 (vc2 + vc1 ) + Sb1 (vc1 ), (3.3b)
vtc0 = Sc4 (vc4 + vc3 + vc2 + vc1 ) + Sc3 (vc3 + vc2 + vc1 ) + Sc2 (vc2 + vc1 ) + Sc1 (vc1 ). (3.3c)

For the DC-side we deduce

i4 = Sa4 ia + Sb4 ib + Sc4 ic , (3.4a)

i3 = Sa3 ia + Sb3 ib + Sc3 ic , (3.4b)
i2 = Sa2 ia + Sb2 ib + Sc2 ic , (3.4c)
i1 = Sa1 ia + Sb1 ib + Sc1 ic , (3.4d)
i0 = Sa0 ia + Sb0 ib + Sc0 ic , (3.4e)
4
X
idc = ij . (3.4f)
j=0

Equations (3.3) and (3.4) demonstrate that the effects of the DCC switching functions on
the AC-side voltages and DC-intermediate branch currents can be expressed by voltage
and current sources, respectively. Therefore, a generalized equivalent circuit of the DCC,
based on (3.3) and (3.4), can be illustrated as that of Fig. 3.5. Based on the equivalent
circuit of Fig. 3.5 and (3.3) and (3.4), DC-intermediate branch currents, i1 , i2 , and i3 ,
and AC-side voltages are determined by the switching functions of the DCC. For proper
operation of the DCC, the switching functions should be modified to (i) enforce zero
average currents into the DC-intermediate branches, and (ii) generate sinusoidal AC-side
voltages.
For a SPWM-switched five-level DCC, the exact switching functions of Sj0 to Sj4 ,
j = a, b, c are deduced from multiplication of waveforms of Fig. 3.2 as given by (3.2).
The exact switching functions of phase-a are illustrated in Fig. 3.6 by solid lines. If the
carrier frequency is much larger than the frequency of the modulating signal, at any given
 Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 38

idc
vC 4 iCC 4 4 i4


 iC 3 vta i
vC 3 C3 i3  
a


vtb
Vdc
 iC 2  
ib
vC 2 C2 i2 vtc

 
ic
 iC1
vC1 C1 i1

0 i0

Figure 3.5: An equivalent circuit of the five-level DCC of Fig. 3.4

time the exact switching functions of Fig. 3.6 can be approximated by the instantaneous
value of the modulating signal. Thus, the switching functions of Fig. 3.6 also can be
mathematically expressed by equivalent continuous functions, Sba4 to Sba0 , as shown by
dashed lines in Fig. 3.6 as well. For an amplitude modulation index m, the modulating
waveform is M (θ) = m sin(θ) = m sin(ωt) and the continuous switching functions are


 2M (θ) − 1 1
sin−1 ( 2m 1
) ≤ θ ≤ π − sin−1 ( 2m ),


Sba4 = (3.5)



 0 otherwise,


 2M (θ) 1
0 ≤ θ ≤ sin−1 ( 2m ),




 2 − 2M (θ) 1
sin−1 ( 2m 1
) ≤ θ ≤ π − sin−1 ( 2m ),
Sba3 = (3.6)

 2M (θ) 1
π − sin−1 ( 2m ) ≤ θ ≤ π,




 0 otherwise,


 −2M (θ) + 1 1
0 ≤ θ ≤ sin−1 ( 2m ),





 0 1
sin−1 ( 2m 1
) ≤ θ ≤ π − sin−1 ( 2m ),




 −2M (θ) + 1 1
π − sin−1 ( 2m ) ≤ θ ≤ π,
Sba2 = (3.7)
 2M (θ) + 1
 1
π ≤ θ ≤ π + sin−1 ( 2m ),





 0 1
π + sin−1 ( 2m 1
) ≤ θ ≤ 2π − sin−1 ( 2m ),




 2M (θ) + 1 1
2π − sin−1 ( 2m ) ≤ θ ≤ 2π,


 −2M (θ) 1
π ≤ θ ≤ π + sin−1 ( 2m ),




 2 + 2M (θ) 1
π + sin−1 ( 2m 1
) ≤ θ ≤ 2π − sin−1 ( 2m ),
Sba1 = (3.8)

 −2M (θ) 1
2π − sin−1 ( 2m ) ≤ θ ≤ 2π,




 0 otherwise,
 Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 39

1 Sa4

ba4
S

0
π/2 π 3π/2 2π

1
Sa3

ba3
S

0
π/2 π 3π/2 2π

1
Sa2
ba2
S

0
π/2 π 3π/2 2π

1
Sa1
ba1
S

0
π/2 π 3π/2 2π

1
Sa0
ba0
S

0
π/2 π 3π/2 2π

Angle(rad.)

Figure 3.6: Switching functions of phase-a of a SPWM-switched five-level DCC

solid lines: exact switching functions
dashed lines: continuous mathematical switching functions


 −2M (θ) − 1 1
π + sin−1 ( 2m 1
) ≤ θ ≤ 2π − sin−1 ( 2m ),


Sba0 = (3.9)



 0 otherwise.

Analogous expressions can also be developed for the corresponding switching functions
of phases b and c. Consider the AC-side three-phase currents as

ia (θ) = Im sin(θ + φ), (3.10)

Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 40

ib (θ) = Im sin(θ + φ − 2π/3), (3.11)

ic (θ) = Im sin(θ + φ + 2π/3). (3.12)

Thus, current i4 , Fig. 3.4, is

i4 = Sba4 ia + Sbb4 ib + Sbc4 ic . (3.13)

The average value of i4 , i.e. ī4 , is obtained by averaging (3.13) over one cycle of the
modulating waveform. Considering switching functions (3.5) to (3.9), ī4 is
1 R 2π b b b
i4 = 2π 0 (Sa4 ia + Sb4 ib + Sc4 ic )dθ =
 q
4m2 −1



3
I cos(φ)(2mπ − 4m sin−1 ( 2m
1
)− ) 0.5 ≤ m ≤ 1,
 4π m m2
(3.14)




0 0 ≤ m ≤ 0.5.
Based on similar calculations
1 R 2π b b b
i3 = 2π 0 (Sa3 ia + Sb3 ib + Sc3 ic )dθ =
 q
4m2 −1



3
I cos(φ)(−mπ + 4m sin−1 ( 2m
1
)+ ), 0.5 ≤ m ≤ 1,
 2π m m2
(3.15)



 3
4
mIm cos(φ) 0 ≤ m ≤ 0.5,
1 Z 2π b
i2 = (Sa2 ia + Sbb2 ib + Sbc2 ic )dθ = 0, (3.16)
2π 0
1 R 2π b b b
i1 = 2π 0 (Sa1 ia + Sb1 ib + Sc1 ic )dθ =
 q
 3 −1 1 4m2 −1

 − I
2π m
cos(φ)(−mπ + 4m sin ( 2m
) + m2
) 0.5 ≤ m ≤ 1,
 (3.17)




− 43 mIm cos(φ) 0 ≤ m ≤ 0.5,
1 R 2π b b b
i0 = 2π 0 (Sa0 ia + Sb0 ib + Sc0 ic )dθ =
 q
 3 −1 1 4m2 −1

 − 4π
Im cos(φ)(2mπ − 4m sin ( 2m
) − m2
) 0.5 ≤ m ≤ 1,
 (3.18)




0 0 ≤ m ≤ 0.5.
Considering the power balance equation between DC-side and AC-side of the DCC, we
have

1 R 2π
Vdc īdc = 2π 0 (vta ia + vtb ib + vtc ic )dt. (3.19)

From (3.19), īdc in Fig. 3.5 is deduced as

1 3Vdc
īdc = Vdc 4
mIm cos(φ) = 34 mIm cos(φ). (3.20)
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 41

Based on (3.14) to (3.20), average values of capacitor currents are

q
3 −1 1 2
īC4 = īdc − ī4 = 4π Im cos(φ)(−mπ + 4m sin ( 2m ) + 4mm2−1 ),
q
2
īC3 = īC4 − ī3 = − 4π3
Im cos(φ)(−mπ + 4m sin−1 ( 2m 1
) + 4mm2−1 ),
q (3.21)
2
īC2 = īC3 − ī2 = − 4π3
Im cos(φ)(−mπ + 4m sin−1 ( 2m 1
) + 4mm2−1 ),
q
2
īC1 = īC2 − ī1 = 3
I
4π m
cos(φ)(−mπ + 4m sin−1 ( 2m
1
) + 4mm2−1 ).
Based on (3.21), average values of capacitor currents, i.e. īC1 to īC4 , are functions of the
modulation index and the AC-side power factor. When the DCC exchanges non-zero real
power, i.e. cos(φ) 6= 0, average values īC1 to īC4 are not zero. These non-zero current
components, based on (3.21), result in voltage deviations of DC-capacitors. Equations
(3.21) show that in a SPWM-switched five-level DCC, capacitors C4 and C1 ( C3 and C2 )
tend to be charged (discharged) and lead to operational failure of the DCC. Without the
use of auxiliary circuits, a SPWM technique is not able to maintain the DC-capacitor
voltages balanced. In contrast, a SVM switching strategy can exploit the redundant
switching vectors to prevent voltage drifts of DC-capacitors without a need for auxiliary
hardware. A SVM switching approach is capable of modifying the switching functions of
a DCC to enforce zero average current values into the DC-side intermediate braces. In
the next section a balancing strategy based on the SVM switching strategy of Chapter 2
is proposed and investigated.

3.3 SVM For a Five-Level DCC

3.3.1 Space Vector Plane, Sectors, and Switching Vectors

As there are five distinct permitted switching states for each phase of a five-level DCC,
there are 125 switching states in the abc frame. Application of transformation (2.3)
of Chapter 2 to all combinations of output voltages associated with the 125 switching
state vectors results in 60 non-zero voltage space vectors, Vk , k = 1, 2, ..., 60, where Vk
is the kth voltage space vector. Projection of vectors on a αβ coordinates forms a four-
layer hexagon centered at the origin of the αβ plane, Fig. 3.7. Zero voltage vectors are
located at the origin of the plane. The switching states are illustrated by 0, 1, 2, 3, and
4 which denote the corresponding switching states of Sj0 to Sj4 , j = a, b, c, Fig. 3.4.
Thus, the switching state 4 for phase-a corresponds to a state for which Sa4 = 1. The
methodology to synthesize the AC-side voltage is based on the fast SVM algorithm
presented in Chapter 2.
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 42

Sector II
β
040 140 240 340 440

7
041 141 241 341 441 430
030 130 230 330 6
Sector III Sector I
242 342 442 12 5
042 142 131 331 431 420
231
031 020 220 11 320 4
343 120 443
042
332 15 432 10 3
043 143 232 421 410
132 321
032 121 221 310
021
010 444 110 14 210 9 2
344
144
244
233
333 16 433
322 13
422 8
411
1 α
044 133 222 400
033 122 211 300
022 111
011 334 434 100
234 423
223 323 312 412 401
034 134 123
112 212 201 301
023 012
001 101
224 324 424
024 124 113 213 313 413 402
013 002 102 202 302 Sector VI
Sector IV
014 114 214 314 414 403
003 103 203 303

004 104 204 304 404

Sector V

Figure 3.7: Space voltage vectors for a five-level DCC

As it is shown in Fig. 3.7, all of the switching vectors except those that are located on
the outermost layer, have redundant switching states. The redundant switching states
corresponding to a switching vector generate the same AC-side voltage, however, currents
of DC-intermediate branches are different. Those switching vectors that have redundant
states provide flexibility for (i) switching frequency minimization, (ii) harmonic reduction,
and/or (iii) DC-capacitor voltage balancing task.

As was explained in Section 2.4.4, after determining the switching states correspond-
ing to Vref , the next step is to identify the best redundant switching states and generate
the switching pattern to control voltages of the capacitors. This requires knowledge
of phase currents and impacts of different switching states on DC-intermediate branch
currents and consequently capacitor voltages.
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 43

3.3.2 Effects of Different Switching States on DC-Intermediate

Branch Currents
To develop a mathematical model that describes the average current in the DC-intermediate
branches, the contributions of different switching states to the DC-intermediate branch
currents and the relationship between the DC-intermediate branch currents and the AC-
side currents for each switching state are required. Since the SVM algorithm of Chapter 2
intrinsically maps all sectors to sector I, only sector I is considered and then based on
minor adjustments, the analysis is generalized for all sectors. Effects of switching states
on DC-intermediate branch currents, i.e. i3 , i2 and i1 , and their relationship with AC-
side currents, i.e. ia , ib , and ic , in sector I are shown in Table 3.2. Effects of switching
states on i3 , i2 and i1 for other sectors also can be deduced from Table 3.2.
To determine i1 , i2 and i3 in terms of ia , ib , and ic , for various switching states of
sectors II to VI, we consider the following two cases.
Case 1) Tip of Vref is located in either sector III or V (odd-numbered sectors). With-
out the loss of generality, we assume that the tip of Vref is located within the shaded
triangle of sector III, as shown in Fig. 3.8. Based on Fig. 3.8, the adjacent switching
states of Vref are (144,033), (143,032), and (244,133,022). The shaded triangle in sector
III and the adjacent switching states, based on the SVM algorithm of Chapter 2, when
mapped to sector I, result in a shaded triangle shown in Fig. 3.8. Corresponding switch-
ing states in sector I that are adjacent to the shaded triangle are (441,330), (431,320),
and (442,331,220). Based on these switching states and the adjacent switching states of
Vref in sector III, we can observe the following co-relation.

SectorI : (441, 330), (431, 320), (442, 331, 220)

l l l l l l l
SectorIII : (144, 033), (143, 032), (244, 133, 022)

This observation also indicates that there is a shift in phase orders between each
state in sector I and its equivalent state in sector III. Therefore, if we specify the voltages
corresponding to a switching state of sector I by va , vb and vc , then by shifting the orders
to vc , va and vb , the equivalent switching state in sector III is deduced. This rule applies to
all corresponding switching states in sector I and sector III respectively. This relationship
between the switching states can be exploited also to deduce the relationships between
i1 , i2 and i3 and ia , ib , and ic . For example:
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 44

Table 3.2: Relationship between the DC-intermediate branch currents and AC-currents
for different switching states in Sector I

sector I i3 i2 i1
400 0 0 0
410 0 0 ib
420 0 ib 0
430 ib 0 0
440 0 0 0
411 0 0 −ia
300 ia 0 0
421 0 ib ic
310 ia 0 ib
431 ib 0 ic
320 ia ib 0
441 0 0 ic
330 −ic 0 0
422 0 −ia 0
311 ia 0 −ia
200 0 ia 0
432 ib ic 0
321 ia ib ic
210 0 ia ib
442 0 ic 0
331 −ic 0 ic
220 0 −ic 0
433 −ia 0 0
322 ia −ia 0
211 0 ia −ia
100 0 0 ia
443 ic 0 0
332 −ic ic 0
221 0 −ic ic
110 0 0 ic
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 45
Sector II

040 140 240 340 440

041 141 241 341 441 430

030 130 230 330
Sector III
242 342 442 Sector I
042 142 131 331 431 420
231
031 020 220 320
343 120 443
243 432
043 143 232 332 421 410
132 321
032 121 221 310
021 210
344 010 444 110 433
244 422
044 144 233 333 322 411 400
133 311
033 122 222 211 300
022 200
011 334 111 434 100
234 423
223 323 312 412 401
034 134 123
112 212 201 301
023 012
001 101
224 324 424
024 124 113 213 313 413 402
013 002 102 202 302
Sector IV Sector VI
014 114 214 314 414 403
003 103 203 303

004 104 204 304 404

Sector V
Figure 3.8: Adjacent switching states of Vref in odd sectors

Table 3.3: Interchanging the AC-side currents for switching states in odd-numbered
sectors

Sector I Sector III Sector V

ia ia → ib ia → ic
ib ib → ic ib → ia
ic ic → ia ic → ib

For state 431 in sector I: i3 = ib , i2 = 0, i1 = ic ,

For state 143 in sector III: i3 = ic , i2 = 0, i1 = ia .
This indicates that when i1 , i2 and i3 , as functions of ia , ib , and ic , are known in
sector I, i1 , i2 and i3 in sector III can be deduced simply by substituting

ia → ib , ib → ic , ic → ia

This is a general rule for all corresponding switching states of sector I and sector III.
Similar governing rule also exist between the switching state of sector I and sector V as
given in Table 3.3.
Case 2) Tip of Vref is located in either sector II, IV or VI (even-numbered sectors).
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 46

Sector II

040 140 240 340 440

041 141 241 341 441 430

030 130 230 330
Sector III Sector I
242 342 442
042 142 131 331 431 420
231
031 020 220 320
343 120 443
243 432
043 143 232 332 421 410
132 321
032 121 221 310
021 210
344 010 444 110 433
244 422
044 144 233 333 322 411 400
133 311
033 122 222 211 300
022 200
011 334 111 434 100
234 423
223 323 312 412 401
034 134 123
112 212 201 301
023 012
001 101
224 324 424
024 124 113 213 313 413 402
013 002 102 202 302 Sector VI
Sector IV
014 114 214 314 414 403
003 103 203 303

004 104 204 304 404

Sector V
Figure 3.9: Adjacent switching states of Vref in even sectors

Without the loss of generality, we assume that the tip of Vref is located within the shaded
triangle of sector II, as shown in Fig. 3.9. Based on Fig. 3.9, the adjacent switching states
of Vref are (141,030), (241,130), and (242,131,020). The shaded triangle in sector II and
the adjacent switching states, based on the SVM algorithm of Chapter 2, when mapped
to sector I, result in a shaded triangle shown in Fig. 3.9. The corresponding switching
states in sector I that are adjacent to the shaded triangle are (441,330), (431,320), and
(442,331,220). Based on these switching states and the adjacent switching states of Vref
in sector II, we observe the following co-relation.

SectorI : (441, 330), (431, 320), (442, 331, 220)

l l l l l l l
SectorII : (141, 030), (241, 130), (242, 131, 020)

The observation also indicates that there is no shift in phase orders between each state
in sector I and its equivalent state in sector II. Therefore, no specific relationship exists
to deduce the relationships between i1 , i2 and i3 and ia , ib , and ic .
To deduce i1 , i2 and i3 in sector II, when i1 , i2 and i3 as functions of ia , ib , and ic
are known in sector I, we need to modify the SVM algorithm of Chapter 2. If we change
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 47

Sector II
040 140 240 340 440

041 141 241 341 441 430

030 130 230 330
Sector III Sector I
242 342 442
042 142 131 331 431 420
231
031 020 220 320
343 120 443
042 432
043 143 232 332 421 410
132 321
032 121 221 310
021 210
344 010 444 110 433
244 333 422
044 144 233 322 411 400
113 222 311
033 122 211 300
022 111 200
011 334 000 434 100
234 423
223 323 312 412 401
034 134 123
112 212 201 301
023 012
001 101
224 324 424
124 113 213 313 413 402
024
013 002 102 202 302 Sector VI
Sector IV
014 114 214 314 414 403
003 103 203 303

004 104 204 304 404

Sector V

Figure 3.10: Mapping sectors II to VI to sector I such that shaded areas overlap

the SVM algorithm such that the shaded triangle in sector II, Fig. 3.9, is mapped on the
highlighted triangle in sector I, as shown in Fig. 3.9, then the mapped switching states
are (411,300), (421,310), and (422,311,200). In this case, based on these switching states
and the adjacent switching states of Vref in sector II, we observe the following co-relation.

SectorI : (411, 300), (421, 310), (422, 311, 200)

l l l l l l l
SectorII : (141, 030), (241, 130), (242, 131, 020)

This observation indicates that there is a shift in phase orders between each state in
sector I and its equivalent state in sector II. The shift in phase orders exist if a Vref of
sector II which is located in the first 30◦ region, i.e. white area of Fig. 3.10, is mapped
to the second 30◦ region of sector I, and if a Vref of sector II is located in its second 30◦
region, i.e. shaded area of Fig. 3.10, it is mapped to the first 30◦ region of sector I.
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 48

A Vref of sector II which is located in the first 30◦ region, Fig. 3.10, is mapped to
the second 30◦ region of sector I, simply by exchanging ni and ni+1 of Fig. 2.7. This
relationship exists due to the symmetry of (2.14) with respect to ni and ni+1 . Similarly
if a Vref of sector II is located in its second 30◦ region, it is mapped to the first 30◦ region
of sector I.
Therefore, if we specify voltages corresponding to a switching state of sector I by va ,
vb and vc , then by shifting the orders to vb , va and vc , the equivalent switching state in
sector II is deduced. This rule applies to all corresponding switching states in sector I and
sector II respectively. This relationship between the switching states can be exploited
also to deduce the relationships between i1 , i2 and i3 and ia , ib , and ic . For example:
For state 421 in sector I: i3 = 0, i2 = ib , i1 = ic ,
For state 241 in sector II: i3 = 0, i2 = ia , i1 = ic .
This indicates that when i1 , i2 and i3 as functions of ia , ib , and ic are known in sector
I, i1 , i2 and i3 in sector II can be deduced simply by substituting

ia → ib , ib → ia , ic → ic

This is a general rule for all corresponding switching states of sector I and sector II.
Similar procedures are applicable for sectors IV and VI. Generally, when the tip of Vref
is located in an even-numbered sector, the first 30◦ region of the sector is mapped on
the second 30◦ region of sector I, i.e. the white area of Fig. 3.10, and the second 30◦
region of the sector is mapped on the second 30◦ region of sector I, i.e. the shaded area
of Fig. 3.10. Exploiting this property for the SVM algorithm, and following a similar
procedure described for sector II, a general rule for interchanging ia , ib , and ic is attained
for even-numbered sectors, as given by Table 3.4. Table 3.5 summarizes the general rule
for interchanging ia , ib , and ic in sectors I to VI. Table 3.5 is used in the subsequent
section to calculate the average values of i1 , i2 , and i3 to carry out DC-capacitor voltages
balancing task.
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 49

Table 3.4: Interchanging the AC-side currents for switching states in even-numbered
sectors

Sector I Sector II Sector IV Sector VI

ia ia → ib ia → ic ia → ia
ib ib → ia ib → ib ib → ic
ic ic → ic ic → ia ic → ib

Table 3.5: Interchanging the AC-side currents for switching states in sectors I to VI

Sector I Sector II Sector III Sector IV Sector V Sector VI

ia ia → ib ia → ib ia → ic ia → ic ia → ia
ib ib → ia ib → ic ib → ib ib → ia ib → ic
ic ic → ic ic → ia ic → ia ic → ib ic → ib

3.4 DC-capacitor Voltages Balancing Based on Min-

imum Energy Property
In a n-level DCC, total energy E of (n − 1) DC capacitors is

1 n−1
X
2
E= Cj vCj , (3.22)
2 j=1

where
n−1
X
vCj − Vdc = 0. (3.23)
j=1

Assuming that all capacitors have equal capacitance, i.e. Cn−1 = ... = C1 = C, the total
V2
energy E reaches its minimum of 12 C n−1
dc
when all capacitor voltages are balanced [31].
This condition is called the minimum energy property of a balanced n-level DCC which
can be used as the basic principle for DC-capacitor voltage balancing and control. A
control method should minimize the cost function E and consequently achieve voltage
balancing. By a change of variable from vCj to (vCj − Vdc /(n − 1)) in (3.22), a positive-
definite cost function J is defined which reaches zero as the absolute minimum value,
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 50

i.e.
1 n−1
X Vdc 2
J= C (vCj − ). (3.24)
2 j=1 n−1

The proposed SVM-based DC-capacitor voltage balancing strategy uses cost function J
of (3.24) for selection of redundant switching states of a five-level DCC over a switching
period. The cost function of (3.24) can also be expressed as

4
1 X 2
J= C 4vCj , (3.25)
2 j=1

where 4vCj is voltage deviation of capacitor Cj , i.e. 4vCj = vCj − V4dc . Based on proper
selection of redundant vectors, J can be minimized (ideally reduced to zero), if capacitor
Vdc
voltages are maintained at voltage reference values of 4
. The mathematical condition
to minimize J is
X4 X4
dJ dvCj
=C 4vCj = 4vCj iCj ≤ 0, (3.26)
dt j=1 dt j=1

where iCj is the current through capacitor Cj . Current iCj , j = 1, 2, 3, 4, in (3.26) is

affected by the DC-side intermediate branch currents, i3 , i2 , and i1 , Fig. 3.4. Since i3 , i2 ,
and i1 can be calculated from the vectors used in the switching pattern and their duty
cycles, it is advantageous to express (3.26) in terms of i3 , i2 , and i1 . From Fig. 3.4, the
capacitor currents are expressed as

iC4 = i3 + iC3 , (3.27a)

iC3 = i2 + iC2 , (3.27b)
iC2 = i1 + iC1 . (3.27c)

Considering a constant net-link DC voltage

4
X dvCj
= 0, (3.28)
j=1 dt

and
dvCj
iCj = C , (3.29)
dt
we deduce
4
X
iCj = 0. (3.30)
j=1
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 51

The common current through all capacitors is not considered in the process since it does
not contribute to voltage drifts of capacitors. Solving (3.27) and (3.30), we deduce
1
iC1 = (i1 + 2i2 + 3i3 ) − (i1 + i2 + i3 ), (3.31a)
4
1
iC2 = (i1 + 2i2 + 3i3 ) − (i2 + i3 ), (3.31b)
4
1
iC3 = (i1 + 2i2 + 3i3 ) − i3 , (3.31c)
4
1
iC4 = (i1 + 2i2 + 3i3 ). (3.31d)
4
Equations (3.31a) to (3.31d) are condensly expressed by
3 3
1X X
iCj = xix − ix , j = 1, 2, 3, 4. (3.32)
4 x=1 x=j

Substituting for iCj from (3.32) into (3.26), the following condition to achieve voltage
balancing is deduced
4
X 3 3
1X X
4vCj ( xix − ix ) ≤ 0. (3.33)
j=1 4 x=1 x=j

Imposing
4
X
4vCj = 0, (3.34)
j=1

and substituting for 4vC4 in (3.33) from (3.34), we deduce

3
X 3
X
4vCj ( ix ) ≥ 0. (3.35)
j=1 x=j

Applying the averaging operator over one sampling period to (3.35) results in

1 Z (k+1)T X3 X3
4vCj ( ix )dt ≥ 0. (3.36)
T kT j=1 x=j

Assuming that sampling period T , compared to the time interval associate with the
dynamics of capacitor voltages, is adequately small, capacitor voltages can be assumed
as constant values over one sampling period and consequently (3.36) is simplified to
3
X 3
X 1 Z (k+1)T
4vCj (k)( ix )dt ≥ 0, (3.37)
j=1 x=j T kT

or
3
X 3
X
4vCj (k)( i¯x (k)) ≥ 0, (3.38)
j=1 x=j
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 52

where 4vCj (k) is the voltage drift of Cj at sampling period k, and īj (k) is the averaged
value of the jth DC-side intermediate branch current. Currents īx , x = 1, 2, 3 should
be computed for different combinations of adjacent redundant switching states over a
sampling period and the best combination which maximize (3.38) is selected.
When the tip of reference voltage vector Vref is located in sector I, the average values
of DC-side intermediate branch currents are
h iT h iT
i¯3 i¯2 i¯1 =D ia ib ic , (3.39)

where D is
 
a11 a12 a13
 
D= 
 a21 a22 a23  . (3.40)
 
a31 a32 a33
Elements of matrix D denote on-duration time intervals of the switching voltage vectors
of sector I and given by

a11 = d300 + d310 + d320 + d311 + d321 − d433 + d322 , (3.41a)

a12 = d430 + d431 + d432 , (3.41b)
a13 = d443 − d330 − d332 − d331 , (3.41c)
a21 = −d422 + d200 + d210 − d322 + d211 , (3.41d)
a22 = d321 + d420 + d421 + d320 , (3.41e)
a23 = d432 + d442 − d220 + d332 − d221 , (3.41f)
a31 = −d411 + d100 − d211 − d311 , (3.41g)
a32 = d410 + d310 + d210 , (3.41h)
a33 = d421 + d431 + d441 + d321 + d331 − d110 + d221 . (3.41i)

where dijk , i, j, k²{0, ..., 4} denotes the duty cycles of its corresponding switching vector
and is calculated based on the procedure in Section 2.4.3 of Chapter 2. Equation (3.39)
is only valid for calculation of ī1 , ī2 , and ī3 in sector I. To calculate ī1 , ī2 , and ī3 in all
sectors of Fig. 3.7, (3.39) is modified as
h iT h iT
i¯3 i¯2 i¯1 = DS ia ib ic , (3.42)

where
 
s1 + s6 s2 + s3 s4 + s5
 
S= 
 s2 + s5 s1 + s4 s3 + s6  , (3.43)
 
s3 + s4 s5 + s6 s1 + s2
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 53

Table 3.6: Interchanging the switching states in sectors I to VI

Sector I Sector II Sector III Sector IV Sector V Sector VI

a a→b a→c a→c a→b a→a
b b→a b→a b→b b→a b→c
c c→c c→b c→a c→b c→a

and si , i = 1, ..., 6, denotes the sector in which the tip of the reference vector is located
within. If the reference vector is in sector i, si = 1, otherwise si = 0. Matrix S is
deduced based on the relationship between the DC-intermediate branch currents and
AC-side currents of sector II to VI with sector I, as given by Table 3.5.
When currents ī1 , ī2 , and ī3 are calculated based on (3.42) for each set of switching
combinations, they are replaced in (3.38) and the best set that fulfills the condition is
selected.
Specifying the sector in which the tip of the reference vector is located within, the
corresponding switching vectors are simply determined by interchanging the switching
states of the output phases in accordance with their equivalents given in Table 3.6 to
generate the gating signals.
The implementation procedure of the voltage balancing strategy based on the aug-
mented SVM switching strategy of Chapter 2 is summarized in Fig. 3.11. The process
outlined in this section determines the desired switching states in the overall αβ plane
to carry out the voltage balancing task.

3.4.1 Space Vector Sequence and Switching Frequency

The space vector sequence in a SVM switching pattern determines the number of on-
off transitions of the switches and consequently reprsents a key parameter for high-
power applications. For a high power converter, e.g. a five-level DCC, low switching
frequency is more desirable since it reduces switching loss. Therefore, to meet the loss
and harmonic spectrum targets, the most appropriate space vector sequence should be
selected. To minimze the switching frequency, the sequence of the switching states is of
crucial importance.
Consider the case that the tip of Vref is located in sector I and the best switching
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 54

!
si ∈ {1,2,...,6}

ni
(
ni+1 % #

" #

ia vC1
$
ib " # vC 2
ic " vC 3
% & $ $'
vC 4

( # # " #
( (*
) $+

) " #

Figure 3.11: Schematic diagram of the balancing strategy based on the augmented SVM
switching strategy

states that fulfill (3.38) to meet voltage balancing criteria are 300, 410, and 421. However,
the switching sequence 300-421-410 is not desireable from the standpoint of switching fre-
quency since (i) transition from 300 to 421 requires three legs to be switched, and (ii)
phase b voltage level changes from 0 to 2, i.e. a two-step change. To the contrary, se-
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 55

^ vC 4 C4

^ vC 3 C3

a vta
Vdc o
b vtb
c vtc
^vC 2 C2
ia ib ic

^ vC1 C1

SVM Modulator & Gating

Signal Generator

m f

Figure 3.12: Schematic representation of the system Fig. 3.1 including AC-side current
sources

quence 300-410-421 leads to a lower switching frequency since it needs single-step voltage
changes for each state transition. These requirements are taken into account in the algo-
rithm of the SVM modulator to minimize the switching frequency to reduce power loss.

3.5 Study Results

This section evaluates performance of the five-level DCC system of Fig. 3.1 when it op-
erate under the proposed SVM switching strategy. The studies are conducted to demon-
strate effectiveness of the proposed SVM strategy to control and prevent DC capacitor
voltage drift. Fig. 3.12 shows a schematic block representation of the five-level DCC sys-
tem including the DC capacitor voltage control block. In this chapter, the performance
of proposed SVM-based balancing strategy is studied under ideal conditions, i.e. the
DC-side of the DCC is supplied by a constant DC source and the AC-side currents are
provided by a three-phase current source. Performance of the proposed strategy under
realistic scenarios will be studies in the next chapter where the five-level DCC is used as
a STATCOM. The reported studies in this section are carried out based on time-domain
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 56

Table 3.7: Parameters of the system of Fig. 3.12

Converter Parameters
Converter MVA 1.2 MVA
DC Capacitor, Cj , j=1,2,3,4 1000 µ F
Sampling frequency, fsampling 3 kHz
Nominal net DC voltage, Vdc 8000 V
AC-side Current, Irms 250 A
Frequency, f 50 Hz

simulation in the MATLAB/SIMULINK environment. The system parameters are given

in Table 3.7.

3.5.1 Limits of Operation

As discussed in Section 3.2.2, the existing PWM strategies cannot guarantee capacitor
voltage balance of a passive-front-end, five-level DCC under all possible operating condi-
tions. Limits of operation of any PWM-based balancing strategy, that takes advantage
of all available voltage levels, is within the theoretical limits of a n-level DCC (n → ∞),
i.e. the shaded area in Fig. 3.3 [30]. The solid line in Fig. 3.13 shows the boundary
under which the proposed SVM strategy can control and achieve balanced DC-capacitor
voltages. The limit shown in Fig. 3.13 is determined under sinusoidal AC-side currents,
and considered as the theoretical limit of the proposed voltage balancing method.
A n-level DCC (n > 3) is a potential candidate for transformerless reactive power
compensators, and in this context both four-level and five-level DCCs have been widely
considered [39], [57]. To demonstrate superiority of a five-level DCC over a four-level
DCC, in terms of capacitor voltage balancing limit, the limit of a four-level DCC is also
illustrated in Fig. 3.13, i.e. the dashed line [14]. Fig. 3.13 indicates that the area in which
the voltage balancing, based on the proposed SVM strategy, is guaranteed by a five-level
DCC is larger than that of a four-level DCC. This conclusion is also consistent with the
finding of [30]. The shaded area in Fig. 3.3 can be considered as the voltage balancing
limit of a n-level DCC when n → ∞ [30]. Fig. 3.3 shows that as the number of levels
of a DCC increases, the voltage balancing limit become closer to that of a n-level DCC
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 57

1
5−Level DCC
0.95 4−Level DCC

0.9 C

0.85
Modulation Index, m

0.8

0.75
A
0.7

0.65

0.6

0.55
B
0.5
−180 −150 −120 −90 −60 −30 0 30 60 90 120 150 180
AC−side Current Angle (deg.)

Figure 3.13: Limits of the proposed SVM-based balancing method for a four-level and a
five-level passive-front-end DCCs
A: operating point corresponding to Fig. 3.14
B: operating point corresponding to Fig. 3.15
C: operating point corresponding to Fig. 3.16

(n → ∞). The reason is that as the number of levels increases, the number of available
redundant switching states increases and provides higher degree of flexibility to balance
the DC-capacitor voltages.

3.5.2 Capacitor Voltages Balancing Under Balanced Linear Load

Conditions

This case study demonstrates effectiveness of the SVM switching strategy to prevent
voltage drifts of the DC-capacitors of the system of Fig. 3.12, under various balanced
linear load conditions. Initially the DC capacitors of the converter system of Fig. 3.12
have unequal voltage values at vC1 = 0.3 pu, vC2 = 0.2 pu, vC3 = 0.23 pu, and vC4 = 0.27
pu. Fig. 3.14 illustrates performance of the proposed voltage balancing strategy when
the converter operates at power factor of P F = 1.0 and modulation index of m = 0.7.
This operating point corresponds to “A” on Fig. 3.13 which is an unstable operating
point. Figs. 3.14(a), (b) and (c) show the normalized AC-side line voltage, vtab , AC-
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 58

side currents, ia , ib , ic , and DC-capacitor voltages, vC1 , vC2 , vC3 , and vC4 , respectively.
Consistent with the observations made from Fig. 3.13, Fig. 3.14(c) also shows that the
capacitor voltages cannot be controlled and consequently the AC-side voltage cannot be
maintained, Fig. 3.14(a).
Fig. 3.15 shows the converter waveforms at an AC-side operating point corresponding
to P F = 1.0 and m = 0.5, i.e. point “B” on Fig. 3.13. At this operating point,
Fig. 3.13 predicts a stable operation and balanced capacitor voltages. Figs. 3.15(a), (b)
and (c) show the normalized AC-side line voltage, AC-side currents, and DC-capacitor
voltages respectively. For this operating condition, the capacitor voltages converge to
their nominal values, i.e. 0.25 pu, Fig. 3.15(c). The AC-side line voltage waveform
shown in Fig. 3.15(a), due to a low modulation index, i.e. m = 0.5, has only five distinct
levels.
To demonstrate performance of the voltage balancing strategy at a high modulation
index and a low power factor, the system of Fig. 3.12 is operated at a stable operating
condition corresponding to P F = 0.35 and m = 0.9, i.e. point “C” on Fig. 3.13. The
converter waveforms are shown in Fig. 3.16. Fig. 3.16(a) shows a stable nine-level AC-
side line voltage. Fig. 3.16(b) shows the three-phase AC-side currents. Fig. 3.16(c)
shows that the DC-capacitor voltages converge to a steady-state value of 0.25 pu. The
low-frequency oscillations on the DC-capacitor voltages are due to the selected operating
condition. In general, at low power factors and large modulation indices, low-frequency
oscillations appear on the voltages of capacitors which in turn affect the AC-side voltage
of the converter.

3.5.3 Capacitor Voltages Balancing Under Unbalanced or Dis-

torted AC-side Conditions
This section explores effectiveness of the proposed SVM-based capacitor voltage balancing
strategy under unbalanced or distorted AC-side conditions.

Unbalanced Load Condition

The converter of Fig. 3.12 is subjected to an unbalanced AC-side condition by imposing

a negative-sequence set of currents, i.e. i−
abc = 5%, in addition to the positive sequence

currents, i.e. i+
abc = 100%. The initial voltages of DC capacitors of the converter system

are vC1 = 0.3 pu, vC2 = 0.2 pu, vC3 = 0.23 pu, and vC4 = 0.27 pu. The converter
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 59

operating point corresponds to P F = 0.35 and m = 0.9, i.e. point “C” on Fig. 3.13, which
is an stable operating point. Fig. 3.17(a) and (b) show the AC-side voltage and currents
of the converter, respectively. Fig. 3.17(c) shows the DC-capacitor voltages. Fig. 3.17(c)
indicates that the DC-side capacitor voltages converge to the final steady-state value of
0.25 pu. The study results of Fig. 3.17 show that when the converter operates under a
stable operating condition, the DC-capacitor balancing strategy maintains equal voltages
across the capacitors, despite the AC-side unbalanced condition.

Distorted AC-Side Currents

This case study investigates effectiveness of the SVM switching strategy to prevent volt-
age drift of the DC-capacitors of Fig. 3.12 under distorted AC-side currents which in
practice can be due to the presence of a nonlinear load. The AC-side distorted currents
are created by injecting 5% and 3% of 5th and 7th order harmonic currents respectively,
in addition to 100% fundamental current components.
The initial DC capacitor voltages are set at vC1 = 0.3 pu, vC2 = 0.2 pu, vC3 = 0.23
pu, and vC4 = 0.27 pu. The converter initially operates at P F = 0.35 and m = 0.9, i.e.
point “C” on Fig. 3.13. Fig. 3.18 shows the system response to the distorted AC-side
currents and illustrates the effect of current harmonics on the converter performance.
Figs. 3.18(a) and (b) show the AC-side voltage and distorted currents of the converter,
respectively. Fig. 3.18(c) illustrates fluctuations in DC-capacitor voltages. Fig. 3.18(c)
indicates that despite presence of harmonics in the AC-side currents, the DC-capacitor
voltages converge and remain stable. A comparison between Fig. 3.18(c) and Fig. 3.16(c),
shows that due to the distorted AC-side currents the final values of capacitor voltages in
Fig. 3.18(c) are not the same and have small deviations from their nominal values.

3.6 Summary and Conclusions

A mathematical model for the analysis of the DC-capacitor voltage drift phenomenon of
a passive-front-end, five-level DCC is presented in this chapter. Based on the developed
formulation, the capacitor voltage drift phenomenon of a SPWM-switched five-level DCC
is expressed in terms of the DCC operating point indices, i.e. the modulation index
and the AC-side power factor. It is also shown that a SPWM strategy is not able to
prevent/mitigate the voltage drift phenomenon.
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 60

This chapter also proposes a SVM-based balancing strategy that takes advantages
of redundant switching states to counteract the voltage drift phenomenon of a five-level
DCC. Based on the augmented SVM algorithm of chapter 2, a mathematical basis for
the balancing strategy is developed. A quadratic cost function, that is associated with
the voltage deviations of the DC capacitors, is used to select the best adjacent switching
states over each sampling period. The limits of the proposed SVM strategy to achieve
the DC-capacitor voltage balancing are explored and the theoretical limits are deduced.
Effectiveness of the SVM-balancing strategy under various operating conditions of a
five-level DCC, based on time-domain simulation studies in the MATLAB/SIMULINK
environment, is evaluated. The following conclusions can be made from the results:

• Without a proper balancing scheme, voltages of the DC-capacitors of a passive-

front-end, five-level DCC diverge from their nominal values under both transient
and steady-state conditions.

• A SPWM-switched five-level DCC is incapable of achieving DC-capacitor voltages

balancing. In contrast, a SVM-based switching strategy can exploit the redundancy
of switching states to carry out the balancing task without any additional power
circuitry.

• The proposed SVM-based balancing strategy is an online balancing method which

facilitates the balancing task without any requirement for look-up tables to pick up
the best set of switching states.

• The proposed SVM-based balancing strategy takes advantage of all available voltage
levels. Thus, THD content of the AC-side voltage is minimized.

• The proposed balancing strategy minimizes the switching frequency since, over each
sampling period, it uses the three adjacent switching states with minimum on-off
transitions.

• The studies indicate that a passive-front-end, five-level DCC cannot provide voltage
balancing capability under real power conversion conditions without de-rating the
output voltage. Therefore, it is a potential candidate for a transformerless reactive
power compensator.

• As the number of levels of a n-level DCC increases, the number of redundant

switching states increases which provides a higher degree of freedom to balance the
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 61

DC-capacitor voltages. Consequently, the m − P F area in which voltage balancing

based on the proposed SVM strategy can be achieved, becomes wider.

1
vtab(pu)

0.5
0
−0.5
−1
0 10 20 30 40 50 60 70 80 90 100

(a)
1 ia
0.5 ib
ia,b,c(pu)

ic
0
−0.5
−1
0 10 20 30 40 50 60 70 80 90 100

(b)
VC1
0.4
VC2
Voltage (pu)

0.3 VC3
0.2 VC4

0.1

0 10 20 30 40 50 60 70 80 90 100

Time(ms)
(c)

Figure 3.14: Converter waveforms for operating condition of P F = 1 and m = 0.7: (a)
AC-side voltage, (b) AC-side currents, and (c) DC-capacitor voltages
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 62

Voltage (pu)
0.5
0
−0.5
−1
0 10 20 30 40 50 60 70 80 90 100

(a)
1 ia
0.5 ib

ia,b,c(pu) 0
ic

−0.5
−1
0 10 20 30 40 50 60 70 80 90 100

(b)
0.35
VC1
Voltage (pu)

0.3
VC2
0.25
VC3
0.2 VC4
0.15
0 10 20 30 40 50 60 70 80 90 100

Time(ms)
(c)

Figure 3.15: DCC waveforms for operating condition of P F = 1 and m = 0.5: (a)
AC-side voltage, (b) AC-side currents, and (c) DC-capacitor voltages
1
vtab(pu)

0.5
0
−0.5
−1
400 420 440 460 480 500

(a)
1 ia
0.5 ib
ia,b,c(pu)

ic
0
−0.5
−1
0 10 20 30 40 50 60 70 80 90 100

(b)
0.3
VC1
Voltage (pu)

V
C2
0.25 VC3
VC4

0.2
400 420 440 460 480 500

Time(ms)
(c)

Figure 3.16: DCC waveforms under balanced loading condition of P F = 0.35 and m =
0.9: (a) AC-side voltage, (b) three-phase AC-side currents, and (c) DC-capacitor voltages
Chapter 3. DC-Capacitor Voltage Control of a Five-Level DCC 63
1

vtab(pu)
0.5
0
−0.5
−1
400 420 440 460 480 500

(a)
1 ia
0.5 ib

ia,b,c(pu)
ic
0
−0.5
−1
400 420 440 460 480 500

(b)
0.3
VC1
Voltage (pu)

VC2
0.25 VC3
VC4

0.2
400 420 440 460 480 500

Time(ms)
(c)

Figure 3.17: DCC waveforms under unbalanced loading condition of P F = 0.35 and
m = 0.9: (a) AC-side voltage, (b) three-phase AC-side currents, and (c) DC-capacitor
voltages
1
vtab(pu)

0.5
0
−0.5
−1
400 420 440 460 480 500

(a)
1 i
a
0.5 ib
ia,b,c(pu)

i
c
0
−0.5
−1
400 420 440 460 480 500

(b)
0.3
VC1
Voltage (pu)

VC2
0.25 VC3
VC4

0.2
400 420 440 460 480 500

Time(ms)
(c)

Figure 3.18: DCC waveforms under operating condition of P F = 0.35, m = 0.9, and
distorted AC-side currents: (a) AC-side voltage, (b) three-phase AC-side currents, and
(c) DC-capacitor voltages
Chapter 4

Modeling and Control of a

Five-Level DCC-based STATCOM

4.1 Introduction
This chapter presents a five-level DCC-based STATCOM, potentially as a transformerless
compensator for distribution system applications. The main advantage of a five-level
DCC over a two-level VSC and a three-level DCC, when applied as a STATCOM, is that
for the same AC-side voltage, the five-level DCC-based STATCOM can offer reduced
voltage THD content. However, the DC-capacitor voltage drift phenomenon of the five-
level DCC-based STATCOM needs to be prevented/mitigated under both steady-state
and transient conditions.
This chapter investigates the feasibility of the proposed SVM switching strategy of
Chapter 2 and the DC-capacitor voltage balancing strategy of Chapter 3 for application of
a five-level DCC as a STATCOM unit. In comparison with the existing five-level DCC-
based STATCOM systems [39], [40], the salient feature of the proposed STATCOM is
that the capacitor voltage balancing task is achieved with no requirements for additional
power circuitry.
In this chapter, first, a mathematical model of a five-level DCC-based STATCOM
is developed. Then, based on the developed model and the SVM switching strategy
of Chapter 3, the AC-side current controllers, the DC-bus voltage controller, and the
load voltage controller are designed to control reactive power flow, DC-bus voltage and
load voltage of the STATCOM respectively. Effectiveness of the proposed DC-balancing
strategy of Chapter 3 under both steady-state and transient conditions, and performance

64
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM65

Five-Level DCC

vC 4 C4
s1
s2
AC Power System
vC 3 C3 s3
Local Load Utility System
s4 vta ia R L val RS LS ias
Rp vtb ib ial vbl ibs
vtc ic ibl v cl ics
icl
vC 2 C2 s1 RL vcs vbs vas
s2 LL
n

vC1 C1
s3
o s4

Figure 4.1: Schematic diagram of a five-level DCC-based STATCOM connected to a

utility system at the load terminal

of the designed controllers are investigated based on time-domain simulation studies in

the PSCAD/EMTDC environment.

4.2 System Structure

Fig. 4.1 shows a STATCOM that is connected directly (without transformer) to a utility
power system. The power system is represented by a three-phase voltage source behind
series RL elements in each phase. The local load is a three-phase, passive RL load. The
DC-side resistor Rp , Fig. 4.1, represents an estimate of the STATCOM switching losses
and is not a physical component.

The STATCOM is used either to control power factor or regulate voltage at the load
terminal through reactive power exchange with the power system. The STATCOM also
regulates its DC bus voltage, Vdc , through real power exchange with the AC system. The
STATCOM operates based on the SVM switching strategy of Chapter 3.
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM66

vC 4 iCC 4 4 i4


 iC 3 vta i L RS LS
R val ias
vC 3 C3 i3 a


vtb i ial
Rp b vbl ibs
 iC 2
vC 2 C2 i2 vtc i
ibl
 c v cl ics
icl vcs vbs vas
 iC1
vC1 C1 i1 RL
 n
O i0 LL

Figure 4.2: An equivalent circuit of the system of Fig. 4.1 based on the DCC equivalent
circuit of Fig. 3.5

4.3 System Model

4.3.1 System Model in abc Frame

This section develops a fundamental-frequency dynamic model for the system of Fig. 4.1.
The mathematical procedures described by (3.3) and (3.4) and the equivalent circuit
of Fig. 3.5 are directly applicable to the STATCOM of Fig. 4.1. Thus, an equivalent
circuit of Fig. 4.1 can be represented by Fig. 4.2. Based on the DC-capacitor voltage
balancing strategy of Chapter 3, the following assumption for modeling the STATCOM
is applicable:

• The capacitor voltages are maintained balanced. Therefore, the DC-intermediate

branch currents are ignored and the DC-side capacitors can be assumed as four
identical series-connected capacitors.

Based on this assumption, a simplified equivalent circuit of the STATCOM of Fig. 4.1,
can be illustrated by Fig. 4.3. The mathematical equations which govern the behavior of
the AC-side voltages of Fig. 4.3 are
dia
vta = Ria + L + val , (4.1a)
dt
dib
vtb = Rib + L + vbl , (4.1b)
dt
dic
vtc = Ric + L + vcl . (4.1c)
dt
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM67

 iC
C4

vta i R L RS LS
a val ias
C3 ial
vtb i vbl
Rp Vdc idc b ibs
ibl
vtc i
C2 c v cl ics
icl vcs vbs vas
RL
C1 n
 LL
O

Figure 4.3: Simplified equivalent circuit of Fig. 4.2

The fundamental-frequency components of the STATCOM terminal voltages, i.e. vta , vtb
and vtc in (4.1) are expressed as
   
vta sin(θ)
  1  
   
 vtb  = √ mVdc  sin(θ − 2π )  , (4.2)
  3  3 
2π
vtc sin(θ + 3
)

where θ = ωt + α, m and α are the modulation index and phase-angle of the modulating
waveform respectively, and ω is the system frequency.
C
For the DC-side circuit of the STATCOM, let’s define Ceq = 4
, where C1 = C2 =
C3 = C4 = C. Then, from the equivalent circuit of Fig. 4.3 we have
dVdc Vdc
Ceq =− − idc . (4.3)
dt Rp
Based on the power balance equation of the STATCOM, idc is
1
idc = (vta ia + vtb ib + vtc ic ). (4.4)
Vdc
Substituting for vta , vtb , and vtc by their fundamental-frequency components from (4.2)
in (4.4), we deduce
1 2π 2π
idc = √ m(ia sin(θ) + ib sin(θ − ) + ic sin(θ + ). (4.5)
3 3 3
Equations (4.1) and (4.3) in conjunction with (4.2) and (4.5) represent a fundamental-
frequency model of the system of Fig. 4.1 in the abc frame.
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM68

4.3.2 System Model in dq Frame

Since three-phase power systems are conventionally modeled and controlled in the dq
coordinate system as opposed to the three-phase abc reference frame, therefore, we also
express the equations of the STATCOM in the dq coordinate system. There are two
motivations for the change of coordinates:

• The three variables of the original coordinate are mapped onto two variables.

• The two variables can be decoupled and thus analyzed and controlled independently.

Furthermore, the real and reactive components of the instantaneous power in the system
are defined in a more insightful manner in the dq coordinate system.
To transfer AC-side variables of the STATCOM to a dq frame, a transformation
matrix is selected in which the d and q components of the AC-side currents are decoupled.
Usually, the dq-frame is synchronized to, and aligned with the PCC voltage such that
vlq = 0. vlq is the q-axis voltage of the PCC. The converter AC-side variables are
transferred to the dq frame by [72]

fqdo = Kfabc , (4.6)

where the transformation matrix K is

 
2π 2π
cos(θ) cos(θ − 3
) cos(θ + 3
)
2
 2π 2π


K=  sin(θ) sin(θ − ) sin(θ + ) , (4.7)
3 3 3 
1 1 1
2 2 2

and Z t
θ= ωdt. (4.8)
0
Substituting abc variables from (4.2) and (4.6) in (4.1), the AC-side voltage equations in
the dq frame are
did
vtd = Rid + L − Lωiq + vld , (4.9a)
dt
diq
vtq = Riq + L + Lωid + vlq , (4.9b)
dt
where vld and vlq are the d- and d-axis components of the PCC voltage. vtd and vtq are
1
vtd = √ mVdc cos(α), (4.10a)
3
1
vtq = √ mVdc sin(α). (4.10b)
3
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM69

m and α are calculated as

√ q
3
m= (vtd )2 + (vtq )2 , (4.11a)
Vdc
vtq
α = tan−1 ( ). (4.11b)
vtd
Substituting for iabc from (4.6) in (4.5), we deduce
3
idc = √ m(iq sin α + id cos α). (4.12)
2 3
Substituting for idc from (4.12) in (4.3) yields
dVdc Vdc 3
Ceq =− − √ m(iq sin α + id cos α). (4.13)
dt Rp 2 3
Equations (4.9) and (4.13) express the dq model of the STATCOM that is used for design
of the DC- and AC-side controllers.

4.4 System Controls

4.4.1 AC-Side Current Control

Real and reactive power exchange between the STATCOM and the AC-side system,
Fig. 4.1, are controlled by regulating the d-axis and q-axis current components, i.e. id
and iq , respectively. The current controllers regulate id and iq independently with the
desired response times. In (4.9), vtd and vtq are the control variables and vld and vlq are
disturbance signals. Dynamics of the d- and q-axis current components can be decoupled
through the following change of variables

vtd = ud + Lωiq + vld , (4.14a)

vtq = uq − Lωid + vlq , (4.14b)

where ud and uq are the new control signals obtained from two independent PI-controllers.
Substituting for vtd and vtq from (4.14) into (4.9), we obtain:
did R 1
= − id + utd , (4.15a)
dt L L
diq R 1
= − iq + utq . (4.15b)
dt L L
vtd and vtq are then translated into phase and magnitude, based on (4.11), to produce the
modulating waveform. Equation (4.15) represents two first-order, decoupled subsystems.
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM70

vld
idref ed ud vtd
α

Calculateα and m based on (4.11)

+
−
id Lω

iq Lω
m
− vtq
iqref
+ eq uq
vlq
Figure 4.4: Block diagram of the proposed current controller for the STATCOM of Fig. 4.1

utd and utq are new control signals that are generated by two independent PI-controllers.
One PI-controller processes (idref −id ) to produce utd , and the other takes the same action
on (iqref − iq ) to produce utq . vld and vlq are two feed-forward terms added to the control
action, for providing a faster reaction to the AC source voltage disturbances. Since the
dq-frame is synchronized to the PCC voltage such that vlq = 0, the d-axis current and
the q-axis current correspond to the instantaneous real and reactive power components,
respectively. Phase-angle and magnitude of the converter modulating waveforms are
deduced from (4.11). The d-axis PI-controller is defined by:
Z t
utd = Kip ed + Kii ed dt, (4.16)
0

where ed = idref − id . Then the open-loop gain in the frequency domain becomes
Kii
Kip (s + Kip
) 1
L
l(s) = R . (4.17)
s s+ L
L R
Choosing Kip = τ
and Kii = τ
yields (4.18) and (4.19) for the open-loop and the
closed-loop systems, respectively.
1
l(s) = , (4.18)
τs
id (s) 1
Gi (s) = = . (4.19)
idref (s) τs + 1
Time constant τ determines the response time of the closed-loop system, and is usually
chosen between 3 ms to 5 ms . The q-axis current controller is designed in a similar
manner. Fig. 4.4 shows a block diagram of the proposed current controller.
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM71

4.4.2 Net DC Voltage Controller

The STATCOM net DC-side voltage, Vdc , is regulated by controlling real power exchange
between the STATCOM and the utility system. Multiplying both sides of (4.13) by (Vdc )
and substituting for vtd and vtd from (4.10), we deduce

d( 12 Ceq Vdc2 ) V2 3
= − dc − (vtd id + vtq iq ). (4.20)
dt Rp 2

Equation (4.20) indicates the instantaneous power balance between the DC-side and the
AC-side of the STATCOM. The left side of (4.20) is the rate of change of energy in Ceq .
2
Vdc
Rp
is the power dissipation in Rp . The term 32 (vtd id + vtq iq ) is the power delivered by the
STATCOM at AC-side terminals. Since vtd and vtq are dependent on id and iq , (4.20) is
linear with respect to Vdc2 ; but is multi-variable and nonlinear with respect to id and iq .
If the total instantaneous power of the interface reactors is neglected, then 23 (vtd id +
vtq iq ) = 23 vld id ; thus, (4.20) is reduced to a Single-Input, Single-Output (SISO) system
and described by (4.21)
d( 12 Ceq Vdc2 ) V2 3
= − dc − vld id , (4.21)
dt Rp 2
where Vdc and id are the output and the control input respectively. Equation (4.21) can
be re-arranged as:
Rp Ceq 3
( p + 1)Vdc2 = − Rp vld id , (4.22)
2 2
d
where p = dt
(.). Equation (4.22) can be written in a transfer function form, in the
Laplace domain, as:
3 1
Vdc2 (s) = − Rp vld Rp Ceq id (s), (4.23)
2 2
s + 1
Taking Vdc as the output signal, (4.23) can be linearized with respect to Vdc as

Vedc (s) = Gv (s)eid (s), (4.24a)

3Rp vld 1
Gv (s) = − Rp Ceq , (4.24b)
4Vdcss 2 s + 1

where superscript ∼ denotes small perturbations around the operating point. Vdcss is
a steady-state operating point and assumed to be a pre-specified constant value. The
DC-bus voltage controller determines the required d-axis current based on the following
control law:
Z t
idref = Kvp ev + Kvi ev dt, (4.25)
0
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM72

Vdcref ev K vp s  K vi idref id
Gi (s ) Gv (s ) Vdc
s

Figure 4.5: Block diagram of DC-bus voltage controller of the STATCOM of Fig. 4.1

where ev = Vdcref − Vdc . In (4.25), PI-controller gains Kvp and Kvi can be optimized
based on linear system control methods such as root-locus, Bode plots, etc, to achieve a
pre-specified performance, e.g. using MATLAB/SIMULINK software package. Fig. 4.5
shows a block diagram of the DC-bus voltage controller.

4.4.3 PCC Voltage Controller

PCC voltage vl is regulated by controlling reactive power exchange between the STAT-
COM and the utility system. To control the PCC voltage, a PI controller generates a ref-
erence signal for reactive current component of STATCOM, iqref , as shown in Fig. 4.6 [73].

Vs  jI l X s

el K lp s  K li iqref iq ' vl
vlref Gi (s ) Xs vl
s

Figure 4.6: Block diagram of the PCC voltage controller of STATCOM of Fig. 4.1

4.5 Case Studies

Fig. 4.7 shows a schematic block diagram of the system of Fig. 4.1 and its controllers.
The controllers, shown in Fig. 4.8, include (i) the PCC voltage controller, (ii) the net DC
voltage controller, and (iii) the AC-side current controller. Outputs of the control system
of Fig. 4.8 are m and α that generate switching signals for the converter. The capacitor
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM73

vC 4 s1
s2

vC 3 s3
s4 PCC
isabc vabcs
R L
iabc Rs Ls

ilabc
vC 2 s1
s2
Rl

s3 Ll
vC1
s4

iabc

vdcref iq vl
m D
  iqref 
vdc 
Controllers
 Load
Voltage
 vlref
Controller

Figure 4.7: A block diagram representation of the system of Fig. 4.1 including power and
control sub-systems

voltage balancing scheme is implicitly embedded in the SVM modulator. The studies
reported in this section are performed on the system of Fig. 4.7. The system parameters
are given in Table 4.1. The studies are conducted:

• To demonstrate performance of the proposed DC capacitor voltage balancing strat-

egy of Chapter 3 under transient conditions.

• To evaluate performance of the overall system of Fig. 4.7, including power and
control sub-systems, under various operating scenarios.
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM74

vC1 vC 2 vC 3 vC 4
Vdc vld
Vdcref + − idref vtd
+ α S1
− S1

calculate α and m
id Lω

iq Lω
m
vlref + iqref − vtq S12
S12
+
−
vl vlq
θ = ωt
ia ib ic

vla vlb vlc

Figure 4.8: Block diagram of the overall controllers of the STATCOM

4.5.1 Case-1: Load and STATCOM Energization

The load, Fig. 4.7, is energized at t = 0.1 s and the STATCOM initially exchanges no
reactive power with the system. At t = 0.3 s the STATCOM is commanded to supply
the load reactive power. Before the STATCOM is commanded, i.e. t = 0.3, the current
demand of the load is supplied by the utility system. Therefore, isq , the q-axis current
component of the utility system is equal to ilq . When the STATCOM is commanded, isq is
reduced to zero and the STATCOM supplies the load reactive power which consequently
results in unity power factor at the PCC. In this case, at t = 0.3 s and afterward, the
STATCOM is in the power factor correction mode.
Fig. 4.9 shows dynamic response of the system to the load energization and the
STATCOM reactive power command. Figs. 4.9(a) and (b) show the STATCOM and
the load currents, respectively. Fig. 4.9(c) shows variations of the net DC voltage of
the STATCOM, and illustrates that the voltage is tightly regulated by the controller
of Fig. 4.4 at the reference value. Figs. 4.9(d) and (e) show the STATCOM line-to-line
terminal voltage and the PCC voltage, respectively. The STATCOM line-to-line terminal
voltage of Fig. 4.9(d) that is normalized with respect to Vdc , shows the typical multi-level
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM75

Table 4.1: Parameters of the study system of Fig. 4.7

Parameters Values
STATCOM rated MVA 1.5 MVA
Rated voltage of STATCOM (and Vb ) 4.16 kV
AC system line voltage, vabs 1 pu
AC system Short Circuit Ratio (SCR) 5
Resistance, Rs 0.04 pu
Reactance, Xs 0.2 pu
Load rated power (and Sb ), Sl 3 MVA
Load power factor, P Fl 0.87
Inductor resistance, R 0.01 pu
Inductor reactance, X 0.1 pu
Line frequency , fs 60 Hz
Net DC voltage, Vdc 8 kV
DC Capacitor, Ci 4000 µF ±5%
Resistance, Rp 2 kΩ
Sampling frequency, fsampling 2880 Hz

waveform of a five-level DCC. Fig. 4.9(e) shows the PCC voltage that is almost regulated
at 1 pu after load energization and STATCOM commanding. Fig. 4.9(f) shows the
capacitor voltages that are normalized with respect to the Vdc . Fig. 4.9(f) illustrates
that the capacitor voltages are maintained equal under both steady-state conditions and
transients imposed by the STATCOM control command and the load energization.

4.5.2 Case-2: Reactive Power Control

Initially the system of Fig. 4.7 is in a steady-state condition. The STATCOM delivers
no reactive power. Fig. 4.10 shows dynamic response of the system of Fig. 4.7 to a
step change in reactive current component at t = 0.1 s. Figs. 4.10(a) and (b) show
dynamics of the reactive current component of the STATCOM and the net DC voltage
in response to the reference change, and illustrate that the variables faithfully track the
corresponding references. Fig. 4.10(c) show variation of reactive current component of
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM76

the utility system. The reactive current component of the load is provided by either the
utility system, Fig. 4.10(c), or the STATCOM, Fig. 4.10(a).
Dynamics of the load and the STATCOM currents are illustrated in Figs. 4.10(d) and
(e). The magnitude of load voltage is shown in Fig. 4.10(f). The load voltage is regulated
at almost 1 pu after the STATCOM reactive power command is activated. The STAT-
COM terminal voltage is shown in Fig. 4.10(g). Fig. 4.10(h) shows that the DC capacitor
voltages are maintained balanced by the proposed balancing strategy. Fig. 4.10 indicates
that the designed controllers, Fig. 4.4, effectively and rapidly regulate the system oper-
ating conditions in response to the step change in reactive power reference. Fig. 4.10
also indicates that the proposed SVM-based balancing strategy maintains the capacitor
voltages balanced under both steady-state and transient conditions.

4.5.3 Case-3: Load Voltage Control

The system of Fig. 4.7 is initially in a no-load, steady-state condition, and the PCC
voltage is at 1.0 pu. The load is energized at t = 0.1 s. Fig. 4.11 shows response of
the system to the load energization. Figs. 4.11(a) and (b) show dynamics of the load
current and magnitude of the load voltage. Fig. 4.11(b) illustrates that the STATCOM
regulates the load voltage at the reference value. Variations of reactive and real current
components of the STATCOM are shown in Figs. 4.11(c) and (d), respectively. The
reactive current component of the utility system is shown in Fig. 4.11(e). Figs. 4.11(c)
and (e) show that after the load energization, reactive component of STATCOM current,
iq , regulates the load voltage at the corresponding reference. Fig. 4.11(d) shows the real
current component of the STATCOM that is used for compensation of the STATCOM
switching losses and has a very small value. Fig. 4.11(f) shows that the DC-capacitor
voltages are properly maintained at their nominal values of 0.25 pu.

4.5.4 Case-4: Load Energization Under Unbalanced Source Con-

ditions

This case study investigates load energization of the system of Fig. 4.7 under the same
conditions described in case-3, except that the utility system voltage is not balanced.
Fig. 4.12(a) shows the three phase voltages of the utility system with the peak values of
0.95, 1.0 and 1.05 per unit. Fig. 4.12(b) shows the three phase voltages of the load which
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM77

are unbalanced. Figs. 4.12(c) and (d) show dynamics of the load current and magnitude
of the load voltage in response to load energization. Fig. 4.12(d) illustrates that the
load voltage is regulated at the corresponding reference by the STATCOM. Variations
of reactive current components of the STATCOM and the utility system are shown in
Figs. 4.12(e) and (f), respectively. Figs. 4.12(a) to (f) show that the designed controllers
effectively control the STATCOM current to regulate the load voltage at the pre-specified
reference of 1.0 pu. In comparison with Fig. 4.11, waveforms of Figs. 4.12(d) to (f) contain
low-frequency ripples that are due to voltage imbalance of the utility system. Fig. 4.12(g)
shows that the voltages of the capacitors are kept equal despite the unbalanced utility
source voltages.

4.5.5 Case-5: Three-Phase Fault

The system of Fig. 4.7 is initially in a steady-state operating condition. The load is
connected to the system and its voltage is regulated at 1 pu. The system is subjected to
a balanced, three-phase, line-to-ground fault at the middle of the utility line. The fault
resistance is Rf = 0.75 pu. The fault occurs at t = 0.1 s and lasts for 80 ms. Fig. 4.13
shows transient behavior of the system during and subsequent to the fault. Figs. 4.13(a)
and (b) show the STATCOM current and magnitude of the load voltage, and demonstrate
that the current is controlled to regulate the load voltage at the reference value during
and subsequent to the fault.
Figs. 4.13(c) and (d) show variations of DC voltage and real current component of
the STATCOM in response to the fault scenario. The real current component of the
STATCOM is adjusted to regulate the DC-bus voltage at its nominal value. Fig. 4.13(e)
shows reactive current component of the STATCOM in response to the three-phase fault.
Dynamics of real and reactive current components of the utility system are illustrated in
Figs. 4.13(f) and (g). The study results of Fig. 4.13 show that the STATCOM effectively
maintains the operating conditions of the load subsequent to the fault.
One particularly attractive feature of the proposed SVM-based strategy is to stabilize
the STATCOM DC-capacitor voltages when the trajectory of the operating indices, i.e.
the modulation index and AC-side power factor, temporarily passes through an unstable
region, Fig. 3.13. To demonstrate this feature, the corresponding modulation index and
the AC-side power factor of the STATCOM, under the three-phase fault scenario, are
shown in Fig. 4.14. The steady state operating point of the STATCOM subsequent to
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM78

the fault clearance settles to its prefault operating point. From the viewpoint of the DC-
capacitor voltage balancing strategy, the steady state operating point is a stable point
inside the stable region, Fig. 4.14. However, during the transient period, subsequent to
the fault, the STATCOM operating point passes through the region in which capacitor
voltage balancing is not guaranteed. However, the proposed SVM strategy is able to
maintain the DC-capacitor voltages equal after the operating point moves back to the
stable operating region.

4.6 Summary and Conclusions

This chapter investigates application of a passive-front-end, five-level DCC in the context
of a transformerless STATCOM. The five-level DCC-based STATCOM operates based
on the proposed SVM switching strategy of Chapter 2 and the DC-capacitor voltage
balancing strategy of Chapter 3. A fundamental-frequency mathematical model is devel-
oped for the STATCOM. Based on the developed model, the STATCOM controllers are
designed to control reactive power flow, DC-bus voltage and load voltage. Effectiveness
of the proposed DC-balancing strategy of Chapter 3, and performance of the designed
controllers are investigated. The study results conclude that:

• The DC-capacitor voltage balancing strategy effectively maintains the capacitor

voltages at the rated values (i) during steady-state conditions, and (ii) subsequent
to transients, e.g. load energization, grid faults and change in control reference
values.

• The DC-capacitor voltage balancing strategy also maitains the capacitor voltages
under unbalanced grid conditions.

• Although the m−P F trajectory of the DCC may cross the unstable zone of voltage
balancing operation, the final operating point can be a stable point.

• The passive-front-end, five-level DCC system can effectively perform its function
as a shunt reactive power compensator based on the switching strategy of Chapter
2 and voltage balancing method of Chapter 3.
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM79

1
0.5

ia(pu)
0
−0.5
−1
0 0.1 0.2 0.3 0.4 0.5

(a)
1
0.5
il(pu)

0
−0.5
−1
0 0.1 0.2 0.3 0.4 0.5

(b)
1.05
Vdc(pu)

0.95 V ref
dc
Vdc
0.9
0 0.1 0.2 0.3 0.4 0.5

(c)
1
0.5
v (pu)

0
tab

−0.5
−1
0 0.1 0.2 0.3 0.4 0.5

(d)
1.1

1
|vl|(pu)

0.9

0.8

0.7
0 0.1 0.2 0.3 0.4 0.5

(e)
0.3
Vcaps(pu)

0.25

0.2
0 0.1 0.2 0.3 0.4 0.5

Time(s)
(f)

Figure 4.9: Dynamic behavior of the system of Fig. 4.7 to load and STATCOM en-
ergization: (a) STATCOM current, (b) load current, (c) STATCOM DC voltage, (d)
STATCOM line-to-line terminal voltage, (e) load voltage, and (f) DC capacitor voltages
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM80

0.6

0.4

iq(pu)
0.2
i ref
q
0 iq

0 0.1 0.2 0.3 0.4 0.5

(a)
1.05

Vdc(pu)
1

0.95
0 0.1 0.2 0.3 0.4 0.5

(b)
0.6

0.4
iqs(pu)

0.2

0
0 0.1 0.2 0.3 0.4 0.5

(c)
1
0.5
il(pu)

0
−0.5
−1
0 0.1 0.2 0.3 0.4 0.5

(d)
1
0.5
ia(pu)

0
−0.5
−1
0 0.1 0.2 0.3 0.4 0.5

(e)
1.1

1
|vl|(pu)

0.9

0.8

0.7
0 0.1 0.2 0.3 0.4 0.5

(f)
1
vtab(pu)

0.5
0
−0.5
−1
0 0.1 0.2 0.3 0.4 0.5

(g)
0.28
Vcaps(pu)

0.26

0.24

0.22
0 0.1 0.2 0.3 0.4 0.5

Time(s)
(h)

Figure 4.10: Dynamic response of the system of Fig. 4.7 to a step change in reactive power
command: (a) STATCOM reactive current component, (b) STATCOM DC voltage, (c)
reactive current component of utility system current, (d,e) load and STATCOM current,
(f) magnitude of load voltage, (g) STATCOM terminal voltage and (h) capacitor voltages
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM81

1
0.5

il(pu)
0
−0.5
−1
0 0.1 0.2 0.3 0.4

(a)
1.05

1
|vl|(pu)

0.95

0.9

0.85
0 0.1 0.2 0.3 0.4

(b)
0.6
0.4
iq(pu)

0.2
ref
iq
0 iq
−0.2
0 0.1 0.2 0.3 0.4

(c)
0.5
id(pu)

−0.5
0 0.1 0.2 0.3 0.4

(d)
0.6
iqs(pu)

0.4

0.2

0
0 0.1 0.2 0.3 0.4

(e)
0.28
Vcaps(pu)

0.25

0.22
0 0.1 0.2 0.3 0.4 0.5

Time(s)
(f)

Figure 4.11: Control of load voltage in the system of Fig. 4.7: (a) load current,
(b) magnitude of load voltage, (c,d) STATCOM reactive and active current components,
(e) utility system reactive current components, (f) capacitor voltages
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM82

1 vas

vabcs(pu)
0.5 v
bs
0 vcs

−0.5
−1
0.35 0.36 0.37 0.38 0.39 0.4

(a)
1 val
vbl
vabcl(pu)
0.5
vcl
0
−0.5
−1
0.35 0.36 0.37 0.38 0.39 0.4

(b)
1

0.5
il(pu)

−0.5

−1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(c)
1.05

1
|vl|(pu)

0.95

0.9

0.85
0 0.1 0.2 0.3 0.4

(d)
0.6
0.4
iq(pu)

0.2
iqref
0 iq
−0.2
0 0.1 0.2 0.3 0.4

(e)
0.6
0.4
iqs(pu)

0.2
0
−0.2
0 0.1 0.2 0.3 0.4

(f)
0.27

0.26
(pu)

0.25
caps
V

0.24

0.23
0 0.1 0.2 0.3 0.4

Time(s)
(g)

Figure 4.12: Control of load voltage in the system of Fig. 4.7 when the utility system
voltages are unbalanced: (a,b) three phase voltages of the utility system and load, (c)
load current, (d) magnitude of load voltage (e,f) STATCOM and utility system reactive
current components, (g) DC capacitor voltages
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM83

2
1

ia(pu)
0
−1
−2
0 0.1 0.2 0.3 0.4 0.5

(a)
1.1

1.05
|vl|(pu)
1

0.95

0.9
0 0.1 0.2 0.3 0.4 0.5

(b)
1.1

1
Vdc(pu)

0.9 v ref
dc
vdc
0.8
0 0.1 0.2 0.3 0.4 0.5

(c)
0.4

0.2
id(pu)

−0.2

−0.4
0 0.1 0.2 0.3 0.4 0.5

(d)
1.2
iqref
1
iq
0.8
iq(pu)

0.6
0.4
0.2
0 0.1 0.2 0.3 0.4 0.5

(e)
2

1.5
i (pu)
ds

0.5
0 0.1 0.2 0.3 0.4 0.5

(f)
0.4
0.2
0
iqs(pu)

−0.2
−0.4
−0.6
0 0.1 0.2 0.3 0.4 0.5

Time(s)
(g)

Figure 4.13: Transient response of the system of Fig. 4.7 to a three-phase fault:
(a) STATCOM current, (b) load voltage magnitude, (c) STATCOM DC voltage,
(d,e) real and reactive current components of STATCOM, and (f,g) real and reactive
current components of the utility system
Chapter 4. Modeling and Control of a Five-Level DCC-based STATCOM84

0.95
steady−state
operating point
0.9
Modulation Index, m

0.85

0.8

0.75

0.7

0.65

0.6

0.55

0.5
0 20 40 60 80 100 120 140 160 180
AC−side Current Angle (deg.)

Figure 4.14: Trajectory of the STATCOM operating point subsequent to the three-phase
fault scenario
Chapter 5

Five-Level DCC-Based Back-to-Back

HVDC System

5.1 Introduction
This chapter presents a five-level DCC-based HVDC system which links two synchronous
or asynchronous AC systems. The five-level DCC-based HVDC converter system belongs
to the regulated power-flow converter systems, i.e. the converter regulates flow of a
pre-specified amount of real power, based on a controlled command, between the two
AC-sides.
Proper operation of a five-level DCC-based HVDC system requires that its DC-
capacitor voltages are maintained balanced during steady-state and dynamic regimes.
In Chapter 3, it is shown that the voltage balancing of a passive-front-end, five-level
DCC has practical limits when the DCC transfers non-zero real power. Back-to-back
connection of five-level DCC units facilitates the DC-capacitor voltage balancing task,
however, it remains an inevitable part of the control system of the converter.
In this chapter, the DC-capacitor voltage balancing strategy of Chapter 3 is modified
and adopted for the DC-capacitor voltage drift control of a five-level DCC-based HVDC
converter system. The modified balancing strategy is based on coordination between the
SVM modulators of the two DCC units [58].
This chapter also develops a mathematical model for a five-level DCC-based HVDC
system. Based on the developed model, a control system is designed to control the
power flow and regulate DC-bus voltage. The effectiveness of the voltage balancing SVM
strategy and the designed controllers are investigated by a number of case studies. The

85
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 86

DCC − 1 i41 i42 DCC − 2

vC 4 C4
i31 o i32
3

vC 3 C3

ia1 R1 L1 vta1 i21 oi22 vta 2 L2 R2 ia 2

ib 1 vtb1 2 vtb 2 ib 2
ic1 vtc1 vtc 2 ic 2
vC 2 C2

i11 oi12
1

vC1 C1
i01 i02
vas1 PCC − 1 PCC − 2 vas 2
vbs1 vbs 2
vcs1 vcs 2

Figure 5.1: Schematic diagram of a five-level DCC-based HVDC converter system

studies are performed in time-domain, using the PSCAD/EMTDC software tool.

5.2 Five-Level DCC-Based HVDC System Structure

Fig. 5.1 shows a schematic representation of a five-level DCC-based HVDC system. The
system comprises two back-to-back connected five-level DCC units. The DC-link is com-
posed of four nominally-identical capacitors. The two DCC units share the same DC-
capacitors and intermediate nodes o1 to o3 are common between DCC-1 and DCC-2. An
estimate of the total switching losses of the system is modelled by resistor Rp that is con-
nected in parallel with the DC-bus . Rp is not shown in Fig. 5.1. The AC-side terminal
of each DCC is connected to the corresponding AC system through a series connected R
and L and a three-phase transformer, Fig. 5.1. R represents the combined effect of the
on-state loss of the corresponding DCC switches and the internal resistance of L.

The capacitor voltage balancing task in the HVDC system of Fig. 5.1 is conceptually
based on the modified SVM balancing startegy of Chapter 3.
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 87

vC 4+ iCC 4 i42
i41 −
4

+ iC 3
i31 vC 3 C3 i32
−
2Rp 2Rp
L1 R1 ia1 vta1 + iC 2 vta 2 i R2 L2
i21 vC 2 C2 i22 a2

− vtb 2
ib1 vtb1 ib 2
+ iC1
vtc1 i11 vC1 C1 i12 vtc 2 i
ic1 − c2

vas1 PCC − 1 PCC − 2 vas 2

vbs1 vbs 2
vcs1 vcs 2

Figure 5.2: An equivalent circuit of the HVDC system of Fig. 5.1 based on the DCC
equivalent circuit of Fig. 3.5

5.3 Voltage Balancing of the DCC System

From Chapter 3, the mathematical procedures described for a passive-front-end five-level
DCC and the equivalent circuit are directly applicable to the back-to-back connected
DCC units of Fig. 5.1. Thus, an equivalent circuit of Fig. 5.1 can be represented by
Fig. 5.2. Based on the equivalent circuit of Fig. 5.2, to balance the capacitor voltages,
average values of DC-intermediate branch currents, i.e. i31 + i32 , i21 + i22 , and i11 + i12 ,
should be zero. Therefore, an active balancing scheme is required to force zero average
currents in the DC-intermediate branches of the back-to-back connected DCC units of
Fig. 5.1. The average values of the DC-intermediate branch currents of the SPWM-
switched, back-to-back connected DCC units are calculated and presented in Appendix B.

The voltage balancing strategy that is proposed in this section uses the minimum
energy property and cost function J of (3.25) in Chapter 3 for selection of redundant
switching states of the two DCC units over a switching period. From (3.25), we have

4
1 X 2
J= C 4vCj , (5.1)
2 j=1
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 88

where 4vCj is voltage deviation of capacitor Cj , i.e. 4vCj = vCj − V4dc . Based on proper
selection of redundant switching states of both DCC units, J can be minimized (ideally
Vdc
reduced to zero), if capacitor voltages are maintained at voltage reference values of 4
.
The mathematical condition to minimize J is
X4 X4
dJ dvCj
=C 4vCj = 4vCj iCj ≤ 0, (5.2)
dt j=1 dt j=1

where iCj is the current through capacitor Cj . iCj , j = 1, 2, 3, 4, in (5.2) is affected by

the DC-side intermediate branch currents, i.e. i32 , i22 , i12 , i31 , i21 , and i11 , Fig. 5.2. Since
DC-side intermediate branch currents can be calculated from the switching states and
their duty cycles, it is advantageous to express iCj in (5.2) in terms of i32 , i22 , i12 , i31 ,
i21 , and i11 . The capacitor currents are

iC4 = iC3 + (i31 + i32 ), (5.3a)

iC3 = iC2 + (i21 + i22 ), (5.3b)
iC2 = iC1 + (i11 + i12 ). (5.3c)

Considering a constant net DC-link voltage and rearranging (5.3) based on (3.28) to
(3.31), we deduce
3 3
1X X
iCj = x(ix1 + ix2 ) − (ix1 + ix2 ), j = 1, 2, 3, 4. (5.4)
4 x=1 x=j

Substituting for iCj from (5.4) into (5.2), the following condition to achieve voltage
balancing is deduced
4
X 3 3
1X X
4vCj ( x(ix1 + ix2 ) − (ix1 + ix2 )) ≤ 0. (5.5)
j=1 4 x=1 x=j

Imposing
4
X
4vCj = 0, (5.6)
j=1

and substituting for 4vC4 in (5.2) from (5.6), we deduce

3
X 3
X
4vCj ( (ix1 + ix2 )) ≥ 0. (5.7)
j=1 x=j

Applying the averaging operator over one sampling period to (5.7) results in

1 Z (k+1)T X3 X3
4vCj ( (ix1 + ix2 ))dt ≥ 0. (5.8)
T kT j=1 x=j
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 89

Assuming that both DCC units have the same sampling period T , and as compared
to the time interval associate with the dynamics of capacitor voltages T is adequately
small, capacitor voltages can be assumed as constant values over one sampling period
and consequently (3.36) is simplified to
3
X 3
X 1 Z (k+1)T
4vCj (k)( (ix1 + ix2 ))dt ≥ 0, (5.9)
j=1 x=j T kT

or
3
X 3
X
4vCj (k)( (īx1 (k) + īx2 (k)) ≥ 0, (5.10)
j=1 x=j

where 4vCj (k) is the voltage drift of Cj at sampling period k, and īj1 (k) + īj2 (k) is
the averaged value of the jth DC-side intermediate branch current. Currents compo-
nents īx1 + īx2 , x = 1, 2, 3 are computed for different combinations of adjacent redundant
switching states over a sampling period and the best combination which maximize (5.10)
is selected.
The average values of AC-side currents iak , ibk , and ick are
 
sk1 + sk6 sk2 + sk3 s4 + sk5
h iT   h iT
 
ī3k ī2k ī1k =  sk2 + sk5 sk1 + sk4 sk3 + sk6  Dk iak ibk ick , (5.11)
 
sk3 + sk4 sk5 + sk6 sk1 + sk2
where k = 1 for DCC-1 and k = 2 for DCC-2. Dk is
 
ak11 ak12 ak13
 
Dk =  
 ak21 ak22 ak23  . (5.12)
 
ak31 ak32 ak33
Elements of matrix Dk denote on-duration time intervals of the switching states of DCC-k
in sector I and given by

ak11 = dk300 + dk310 + dk320 + dk311 + dk321 − dk433 + dk322 , (5.13a)

ak12 = dk430 + dk431 + dk432 , (5.13b)
ak13 = dk443 − dk330 − dk332 − dk331 , (5.13c)
ak21 = −dk422 + dk200 + dk210 − dk322 + dk211 , (5.13d)
ak22 = dk321 + dk420 + dk421 + dk320 , (5.13e)
ak23 = dk432 + dk442 − dk220 + dk332 − dk221 , (5.13f)
ak31 = −dk411 + dk100 − dk211 − dk311 , (5.13g)
ak32 = dk410 + dk310 + dk210 , (5.13h)
ak33 = dk421 + dk431 + dk441 + dk321 + dk331 − dk110 + dk221 . (5.13i)
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 90

where dkijl , i, j, l²{0, ..., 4} denotes duty cycles of corresponding switching state and is
calculated based on Section 2.4.3 of Chapter 2. ski , i = 1, ..., 6, denotes the sector in
which the tip of the reference vector Vref k is located within. If Vref k is in sector ski .
ski = 1, otherwise ski = 0.
Based on (5.11), average values of i31 , i21 , and i11 for each set of redundant switching
state combinations of DCC-1 over a sampling period are calculated. Average values of
i32 , i22 , and i12 for each redundant switching state combinations of DCC-2 over the same
sampling period are also calculated. Based on (5.10), the best two sets of average current
components that fulfill the required condition, i.e. maximize the left-side of (5.10), are
selected. Based on (5.10), there is a coordination between the switching states of both
DCC units, and both units simultaneously contribute to DC-capacitor voltage balancing
task.
The implementation procedure of the voltage balancing strategy, for the system of
Fig. 5.1, is summarized in Fig. 5.3. The process outlined in Fig. 5.3 determines the
desired switching states of the two DCC units to carry out the voltage balancing task.

5.3.1 Space Vector Sequence and Switching Frequency

The space vector sequence in a SVM switching pattern determines the number of on-off
transitions of the switches and consequently is of significance for high-power applications.
For the HVDC converter system of Fig. 5.1, low switching frequency is more desirable
since it reduces switching loss. Therefore, to simultaneously meet the loss and harmonic
spectrum targets, the most appropriate space vector sequences for both DCC units should
be selected. To minimize the switching frequency, the sequence of the switching states is
of crucial importance.
Consider the case that the tips of Vref 1 and Vref 2 are located in sector I and the best
switching states that fulfill (5.10) to meet voltage balancing criteria are 300, 410, and
421 for DCC-1, and 300, 400, and 410 for DCC-2. However, for DCC-1, the switching
sequence 300-421-410 is not desirable since (i) transition from 300 to 421 requires three
legs to be switched, and (ii) phase b voltage level changes from 0 to 2, i.e. a two-step
change. To the contrary, sequence 300-410-421 leads to a lower switching frequency since
it needs single-step voltage changes for each state transition. Similarly, for DCC-2, the
switching sequence 300-400-410 leads to a lower switching frequency. These requirements
are taken into account in the algorithm of the SVM modulators of both DCC units to
 Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 91

Vref 1 Vref 2

SVM Modulator of DCC-1 SVM Modulator of DCC-2

(i) sector identification (i) sector identification
(ii) determination of adjacent switching vectors (ii) determination of adjacent switching vectors
(iii) duty-cycle calculation (iii) duty-cycle calculation
Based on Chapter 2 Based on Chapter 2

s1i p1 j p1( j ,1) p1( j,2) d d

1j
s
1( j ,1) d1( j , 2 ) 2 i
p2 j p2( j ,1)p2 ( j , 2) d 2 j d 2( j ,1) d 2( j , 2)

determination of determination of
redundant switching redundant switching
state combinations state combinations

... ...

ia1 ia 2
ib1 Calculation of average values of
i31, i21 and i11 for different switching combinations
Calculation of average values of
i32, i22 and i12 for different switching combinations
ib 2
ic1 ic 2
... ...

vC1
(5.10) is evaluated for different switching state combinations. vC 2
The best two set, one set from DCC-1 switching states and one set from DCC-2 switching
states that maximize the left-side of (5.10) are selected. vC 3
... vC 4

Gating Signals Generator of DCC-1 Gating Signals Generator of DCC-2

... ...
Gating Signals of DCC-1 Gating Signals of DCC-2

Figure 5.3: Block diagram of DC-link balancing strategy for the converter system of
Fig. 5.1

minimize the switching frequency and reduce power loss.

As it was discussed in Chapter 3, the DC-capacitor voltage balancing of a passive-
front-end five-level DCC is not possible for operating conditions in which the DCC ex-
changes non-zero real power and the modulation index is high. However, in the back-
to-back connection of Fig. 5.1, both DCC units contribute to the voltage balancing task
and non-zero real power exchange is possible under all operating conditions.
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 92

+ iC
C4

C3
idc1 Vdc idc 2
2R p vta 2
ia1 vta1
2Rp
L1 R1 ia 2 R2 L2
C2
ib1 vtb1 vtb 2 i
b2
C1
ic1 vtc1 −
vtc 2 i
c2

Figure 5.4: Simplified equivalent circuit of Fig. 5.2

5.4 Mathematical Model of the HVDC System

The dynamic model of the HVDC system is developed based on the following assump-
tions:

• Based on the DC-capacitor voltage balancing strategy of Section 5.3, the DC-
intermediate branch currents are negligible and assumed to be zero. Therefore, the
equivalent circuit of Fig. 5.2 is simplified to that of Fig. 5.4.

• Nominal voltage amplitudes of both AC Systems are the same. However, their
phases and frequencies are not required to be the same.

• The corresponding power switches, diodes and passive components of the two DCC
units are nominally identical.

Synchronization signals for control systems of DCC-1 and DCC-2 are extracted from the
low-voltage side of the transformers, Fig. 5.1.

5.4.1 System Model in abc Frame

To obtain the abc model of the system of Fig. 5.1, first the mathematical equations that
govern the AC sides of the DCC units are derived. Hereinafter, to avoid repetitions in
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 93

the formulation, the quantities of DCC-1 and AC System-1 are indexed by “1”, while
those of DCC-2 and AC System-2 are indexed by “2”.
Based on the simplified equivalent circuit of Fig. 5.4, the mathematical equations
which govern dynamic behavior of the AC-side voltages, are

diak
vtak = Rk iak + Lk + vask , (5.14a)
dt
dibk
vtbk = Rk ibk + Lk + vbsk , (5.14b)
dt
dick
vtck = Rk ick + Lk + vcsk . (5.14c)
dt

where k = 1 for AC System-1 and DCC-1 and k = 2 for AC System-2 and DCC-2.
Corresponding to the fundamental-frequency component of the AC-side voltages of the
DCC units, the DCC terminal voltages are
   
vtak sin(θk )
  1  
   
 vtbk  = √ mk Vdc  sin(θk − 2π ) , (5.15)
  3  3 
2π
vtck sin(θk + 3
)

where θk = ωk t + αk , mk and αk are respectively modulation index and phase-angle of

the modulating waveforms of DCC-k. ωk is the angular frequency of AC System-k.
For the DC-link circuit of Fig. 5.4, the DC-bus voltage dynamics can be described by

dVdcj 1
Ceq = − Vdc − (idc1 + idc2 ), (5.16)
dt Rp

C
where Ceq = 4
and is the equivalent capacitor seen by each DCC. Based on the power
balance equation of each DCC, we deduce

1
idck = (vtak iak + vtbk ibk + vtck ick ). (5.17)
Vdc

Substituting for vtak , vtbk , and vtck by their fundamental-frequency components from
(5.15) in (5.17), we deduce

1 2π 2π
idck = √ mk (iak sin(θk ) + ibk sin(θk − ) + ick sin(θk + )). (5.18)
3 3 3

Equations (5.14) and (5.16) in conjunction with equations (5.15) and (5.18) represent
a fundamental-frequency model of the HVDC system of Fig. 5.1 in the abc frame.
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 94

5.4.2 Expression of abc Model in dq-Frame

The AC System-k variables are transferred to a dq frame by [74]

fqdok = Kk fabck , (5.19)

Transformation matrix Kk is
 
2π 2π
cos θk cos(θk − 3
) cos(θk + 3
)
2
 2π 2π


Kk =  sin θk sin(θk − ) sin(θk + ) , (5.20)
3 3 3 
1 1 1
2 2 2

where Z t
θk (t) = ωk (t)dt. (5.21)
0
Transforming variables of AC System-k, as given by (5.14) and (5.15), based on (5.19),
we deduce
didk
vtdk = Rk idk + Lk − Lk ωk iqk + vsdk , (5.22a)
dt
diqk
vtqk = Rk iqk + Lk + Lk ωk idk + vsqk . (5.22b)
dt
In (5.22), idk and iqk are the d and q current components of AC System-k, and vtdk and
vtqk are given by
1
vtdk = √ mk Vdc cos(αk ), (5.23a)
3
1
vtqk = √ mk Vdc sin(αk ). (5.23b)
3
where mk and αk are
vtqk
αk = tan−1 ( ), (5.24a)
vtdk
√ q
2 2
3 vtdk + vtqk
mk = . (5.24b)
Vdc
Substituting for iabck from (5.19) in (5.18), we deduce
3
idck = √ mk (iqk sin αk + idk cos αk ). (5.25)
2 3
Substituting for idck from (5.25) in (5.16) yields
dVdc Vdc 3 3
Ceq =− − m1 (iq1 sin α1 + id1 cos α1 ) − m2 (iq2 sin α2 + id2 cos α2 ). (5.26)
dt Rp 2 2
Equations (5.22) and (5.26) represent a dq model of the HVDC system that is used for
design of the DC- and AC-side controllers.
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 95

5.5 AC-Side Current Control of DCC System

Control parameters of each DCC of Fig. 5.1 are its modulation index and phase angle
of the modulating waveform. d and q components of the terminal voltage of DCC units,
based on (5.22), are decoupled through the following change of variables

vtdk = udk − Lk ωk iqk + vsdk , (5.27a)

vtqk = uqk + Lk ωk idk + vsqk . (5.27b)

Substituting for vtdk and vtqk from (5.27) into (5.23), we obtain:

didk Rk 1
= − idk + udk , (5.28a)
dt Lk Lk
diqk Rk 1
= − iqk + uqk . (5.28b)
dt Lk Lk

Equation (5.28) represents two first-order, decoupled subsystems. udk and uqk are new
control signals that are generated by two independent PI-controllers. One PI-controller
processes (idref k −idk ) to produce udk , and the other takes the same action on (iqref k −iqk )
to produce uqk . vsdk and vsqk are two feed-forward terms added to the control action,
for providing a faster reaction to the AC System voltage disturbances. Usually, the dq-
frame is synchronized to, and aligned with the PCC-k such that vsqk = 0. vsdk is the
d-axis voltage of the node where the DCC-k is connected to the AC source. Phase and
the magnitude of the modulating waveform are then deduced from (5.24). The d-axis
PI-controller is defined by:
Z t
udk = Kipk edk + Kiik edk dt, (5.29)
0

where edk = idref k − idk . Then the open-loop gain in the frequency domain becomes
Kiik 1
Kipk (s + Kipk
) Lk
lk (s) = . (5.30)
s s +R k
Lk

Lk Rk
Choosing Kipk = τik
and Kiik = τik
yields (5.31) and (5.32) for the open-loop and the
closed-loop systems, respectively.

1
lk (s) = , (5.31)
τik s
idk (s) 1
Gi (s) = = . (5.32)
idref k (s) τik s + 1
 Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 96
v sa1 vsb1 v sc1 vsc2 vsb2vsa 2

θ1 = ω1t ia1 ib1 ic1 vC1 vC 2 vC 3 vC 4 ic2 ib2 ia2 θ 2 = ω2t

vsd 1 vsd 2
ed 1 ud 1 vtd 1 SVM Modulator 1 SVM Modulator 2 vtd 2 + ud 2 ed 2 +
idref 1 α1 α2 idref 2
+
− − − −
id 1 L2ω2 id2
L1ω1

iq1 L1ω1 L2ω2 i q2

m1 m2
iqref 1
− eq1 u q1 vtq1 Coordination Between
vtq2 uq2 eq2 − iqref 2
+ Swiching States

vsq1 vsq2

Gating Signals Gating Signals

of DCC - 1 of DCC - 2

Figure 5.5: Block diagram of the decoupled dq-frame current controllers

Time constant τik determines the response time of the closed-loop system, and is usually
chosen between 1.5 ms to 5 ms. The q-axis current controller is designed in a similar
manner. Fig. 5.5 shows a block diagram representation of the proposed current controller.

5.6 DC-Bus Voltage Control

To control Vdc , we use (5.26). Multiplying both sides of (5.26) by (Ceq Vdc ) yields

d( 12 Ceq Vdc2 )
=
dt
V2 3 3
− dc − √ (id1 m1 Vdc cos α1 + iq1 m1 Vdc sin α1 ) − √ (id2 m2 Vdc cos α2 + iq2 m2 Vdc sin α2 ).
Rp 2 3 2 3
(5.33)

Substituting for vtdk and vtdk from (5.23), into (5.33), we obtain

d( 12 Ceq Vdc2 ) V2 3 3
= − dc − (vtd1 id1 + vtq1 iq1 ) − (vtd2 id2 + vtq2 iq2 ). (5.34)
dt Rp 2 2
2
Vdc
The left side of (5.34) is the rate of energy variations in Ceq . Rp
is the power dissipation in
Rp . Terms 23 (vtd1 id1 + vtq1 iq1 ) and 32 (vtd2 id2 + vtq2 iq2 ) in (5.34) represent the instantaneous
outgoing powers at the AC-side terminals of DCC-1 and DCC-2, respectively.
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 97

If the total instantaneous power of the interface reactors are neglected, then 32 (vtd1 id1 +
vtq1 iq1 ) = 23 vsd1 id1 . Real and reactive power components delivered to each AC system are
given by
3
P2 = −P1 ≈ vsd iP xref , (5.35a)
2
3
Qk = − vsd iqref k . (5.35b)
2
Thus, (5.34) is reduced to a Single-Input Single-Output (SISO) system described by
(5.36)
d( 12 Ceq Vdc2 ) V2 3 3
= − dc − vsd1 id1 − vsd2 id2 . (5.36)
dt Rp 2 2
Assuming vsd = vsd1 = vsd2 , we have
d( 21 Ceq Vdc2 ) Vdc2 3
=− − vsd (id1 + id2 ). (5.37)
dt Rp 2
We define the d-axis current references idref 1 and idref 2 , as

idref 1 = −iP xref + iV cref , (5.38a)

idref 2 = iP xref + iV cref , (5.38b)

where iP xref is the current command corresponding to the desired power exchange be-
tween AC System-1 and AC System-2. A positive iP xref means a positive power flow
command from AC System-1 to AC System-2. iV cref commands the small real current
drawn from the both AS systems to compensate for the losses represented by Rp , and,
thus, to regulate the DC-bus voltage. Responses of the current controllers (5.32) to
commands (5.38) are:

id1 = −iP x + iV c , (5.39a)

id2 = iP x + iV c . (5.39b)

Substituting for id1 and id2 from (5.39) into (5.37), and re-arranging the result, we obtain
dVdc2 2 6vsd
+ Vdc2 = − iV dc . (5.40)
dt Rp Ceq Ceq
Equation (5.40) describes dynamics of the DC-bus voltage of the HVDC system of
Fig. 5.1. In (5.40), Vdc2 is the output signal and iV c is the control signal. In the Laplace
domain, (5.40) can be written as
3 1
Vdc2 (s) = − Rp vld Rp Ceq iVdc (s), (5.41)
2 2
s+1
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 98

where, based on (5.32) and (5.39),

iV dc (s) = Gi (s)iV dcref (s). (5.42a)

The transfer function from iV cref toVdc2 is given by:

3 1
Vdc2 (s) = − Rp vld Rp Ceq Gi (s)iV cref (s) = (5.43)
2 2
s+1
3 1
− Rp vld Rp Ceq iV cref (s).
2 ( 2 s + 1)(s + τ1i )
iV cref must be determined by a PI-controller for zero steady-state error. Thus, a DC-bus
voltage controller is suggested as
Kvp s + Kvi
iV cref (s) = ev (s), (5.44)
s
2
where ev = Vdcref − Vdc2 .
In (5.44), PI-controller gains Kvp and Kvi can be optimized based on linear system
methods such as root-locus, Bode plots, etc, to achieve a satisfactory system performance.

5.7 Performance Evaluation

5.7.1 Study System

The HVDC system of Fig. 5.1 that operates based on the proposed DC-capacitor voltage
balancing strategy, in conjunction with the control system of Fig. 5.5 is simulated in the
PSCAD/EMTDC environment. Table 5.1 provides parameters of the system of Fig. 5.1
used for the reported studies. The studies are conducted:

• To demonstrate performance of the proposed DC-capacitor voltage balancing strat-

egy.

• To evaluate performance of the overall HVDC system of Fig. 5.1, including power
and control sub-systems, under various dynamic operating scenarios.

5.7.2 Study Results

DC-Bus Voltage Change Under Loaded Condition

Initially, Vdcref is set to 83% pu and iP xref is adjusted corresponding to 0.45 pu real
power flow in the system from AC System-1 to AC System-2. Both DCC units operate
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 99

Table 5.1: Parameters of the study system of Fig. 5.1

Parameters of the Study System Value

Each DCC nominal power (and Sb ) 55 MVA
Each AC system nominal voltage (and Vb ) 138 kV
Each AC system Short Circuit Ratio (SCR) 5
Nominal Frequencies f1 and f2 60 Hz
Each transformer voltage ratio 138 kV/15 kV
R1 and R2 40 mΩ
L1 and L2 6 mH
Each transformer rating 55 MVA
Each transformer leakage reactance 10%
Nominal net DC voltage 28 kV
Resistance Rp 1.8 kΩ
DCC-1 sampling frequency fsampling1 2520 Hz
DCC-2 sampling frequency fsampling2 2520 Hz
DC-link Capacitor Cj , j = 1, ..., 4 2000 µ F
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 100

at unity power factor, i.e. iqref k = 0. At t = 0.1 s, Vdcref is subjected to a step change
from 83% pu to 100% pu. Fig. 5.6(a) shows the DC-bus voltage response. Figs. 5.6(b)
to (e) show variations of id1 , id2 , P1 , and P2 to the step change in the DC-bus voltage,
respectively. Since the system is in a loaded condition, iV c changes to adjust the DC-bus
voltage from 83% pu to 100% pu. However, change of iV c is small and as a result, the
steady-state values of id1 and id2 do not substantially change. This is the case also for P1
and P2 that are proportional to id1 and id2 , respectively. Fig. 5.6(f) shows the capacitor
voltages. As expected, the proposed DC-capacitor voltage balancing strategy maintains
the voltages balanced under the steady-state and also transient conditions subsequent to
the DC-bus voltage change.

Real/Reactive Power Control

Initially, the system is in a standby mode of operation and Vdcref is set to 1 pu. Both
DCC units operate at unity power factor. At t = 0.1 s, iP xref is changed as a step
corresponding to a power flow change from 0 to 0.45 pu, from AC System-1 to AC
System-2. At t = 0.3 s, reactive power demands of both AC systems are changed from 0
to 0.2 pu for AC System-1 and from 0 to -0.18 pu for AC System-2.
Fig. 5.7 shows dynamic response of the system to the step changes in real and re-
active power commands. Figs. 5.7(a) and (b) show corresponding changes to id1 and
iq1 , imposed by the controllers, due to the step changes in real and reactive power com-
mand. Figs. 5.7(c) and (d) show real and reactive power exchanged with AC System-1.
Figs. 5.7(a) and (b) demonstrate that the d− and q−axis current components of AC
System-1 are well decoupled.
Figs. 5.7(e) and (f) show changes in real and reactive current components of AC
System-2 to meet the real and reactive power components in response to changes in
iP xref and iqref 2 . Figs. 5.7(g) and (h) show that real and reactive power exchanged with
AC System-2 are proportional to real and reactive current components of Figs. 5.7(e)
and (f).
Fig. 5.7(i) shows the net DC-link voltage response. Fig. 5.7(i) demonstrates that the
net DC-link voltage, subsequent to the disturbances, is well regulated. Fig. 5.7(k) shows
the DC-capacitor voltages that are kept balanced under both transient and steady-state
conditions.
Fig. 5.7 shows that the control system properly tracks the specified signals to control
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 101

real and reactive power demands independently. Fig. 5.7 also illustrates that the control
system effectively controls the system operating conditions in response to step changes
in real and reactive power demands. Fig. 5.7 highlights effectiveness of the proposed
DC-capacitor voltages balancing strategy to carry out the balancing task, under both
transient and steady-state conditions.

Real-Power Flow Reversal

Initially, 0.45 pu power is flowing from AC System-1 to AC System-2 and Vdcref is set to
1 pu. Both DCC-1 and DCC-2 are operating at unity power factor. At t = 0.1 s, iP xref
is ramped from 0.55 pu to −0.55 pu within 12.5 ms. This change corresponds to a power
flow reversal from 0.45 pu to −0.45 pu, from AC System-1 to AC System-2.

Fig. 5.8 shows dynamic response of the system to the step change in real power
reversal command. Figs. 5.8(a) and (b) show changes in id1 and P1 due to the real power
reversal command. Figs. 5.8(c) and (d) show the corresponding changes in id2 and P2 ,
respectively. As Figs. 5.8(a) to (d) show, real current components of both AC systems
and consequently real power components are reversed as the real power reversal command
is activated. Reactive power components of both AC systems are shown in Figs. 5.8(e)
and (f), respectively. Figs. 5.8(g) and (h) show phase-a currents of AC System-1 and
AC System-2, respectively. Figs. 5.8(g) and (h) show that the currents change their
phases during the power flow reversal period. Modulation indices of DCC-1 and DCC-2
are shown in Figs. 5.8(i) and (j). As Figs. 5.8(i) and (j) show that both DCC units are
operating at high modulation indices. Fig. 5.8(k) shows the net DC-link voltage response.
Fig. 5.8(k) demonstrates that the net DC-link voltage, subsequent to real power reversal
command, is well regulated. Fig. 5.8(l) shows that the DC-capacitor voltages are kept
balanced under both transient and steady-state conditions.

Fig. 5.8 shows that the control system properly track the power reversal command and
the operating conditions are well controlled in response to the power demand. Although
both DCC units are operating with high modulation indices and unity power factors, i.e.
the worst case scenario to carry out voltage balancing task, the DC-capacitor voltage
balancing is achieved successfully.
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 102

Frequency Conversion

The HVDC system of Fig. 5.1 is capable to interface the two AC systems with different
nominal frequencies and maintain DC-voltage balance. To demonstrate this capability,
dynamic response of the system of Fig. 5.1 to step changes in real and reactive power
demands is considered. The nominal frequencies of AC System-1 and AC System-2 of
Fig. 5.1 are 50 Hz and 60 Hz, respectively.

Initially, the system is in a standby mode of operation, while Vdcref is set to 1 pu.
Both DCC units operate at unity power factor. At t = 0.1 s, iP xref is step changed
corresponding to a power flow change from 0 to 0.45 pu, from AC System-1 to AC
System-2. Reactive power demands of both AC systems are changed; from 0 to -0.18 pu
at t = 0.3 s for AC System-2, and from 0 to 0.2 pu at t = 0.5 s for AC System-1.

Fig. 5.9 shows dynamic response of the system to the step changes in real and re-
active power demands of the HVDC system. Figs. 5.9(a) and (b) show that real and
reactive current components of AC System-1 are regulated at the corresponding refer-
ences. Figs. 5.9(c) and (d) show that real and reactive power components of AC System-1
are proportional to id1 and iq1 , respectively. Figs. 5.9(a) to (d) show that id1 and iq1 , and
consequently P1 and Q1 are well decoupled from each other. Real and reactive current
components of AC System-2 are shown in Figs. 5.9(e) and (f). Figs. 5.9(g) and (h) show
real and reactive power components of AC System-2 that are proportional to real and
reactive current components of Figs. 5.9(e) and (f). Figs. 5.9(e) to (h) show that id2 and
iq2 , and consequently P2 and Q2 are well decupled from each other. Figs. 5.9(i) and (j)
show phase-a currents of AC System-1 and AC System-2. As the real power flow com-
mand, i.e. iP xref , is activated, non-zero currents, ia1 and ia2 that are at the frequencies of
50 Hz and 60 Hz, respectively, flow in both AC-sides. Fig. 5.9(k) shows that the DC-bus
voltage is well regulated at 1 pu in response to the change of reference signals. Fig. 5.9(l)
demonstrates that capacitor voltages are kept balanced subsequent to change of power
demands and transients.

The study results of Fig. 5.9 demonstrate that the proposed voltage balancing strategy
and the designed control system operate properly under different frequencies of the AC-
side systems.
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 103

5.8 Summary and Conclusions

This chapter proposes a SVM-based DC-capacitor voltage balancing strategy for back-
to-back connected five-level DCC units. The proposed strategy is developed based on
the modified methodology presented in Chapter 3 which is intended for a passive-front-
end DCC. A quadratic cost function, associated with the voltage deviations of the DC
capacitors, is used to select the best adjacent switching states of the DCC units over
each sampling period. The modified balancing strategy is based on coordination between
the SVM modulators of the two DCC units, and both DCC units contribute to carry
out the balancing task. This chapter also investigates application of the back-to-back
connected Five-level DCC units as an HVDC converter system. The chapter develops a
fundamental-frequency mathematical model for the HVDC system, and utilizes the model
to develop controllers to control power flow and regulate the net DC-bus voltage. The
capability of the voltage balancing SVM strategy, performance of the designed controllers,
and also the overall performance of the HVDC system are investigated based on time-
domain simulation studies, in the PSCAD/EMTDC environment. This chapter concludes
that:

• There is a need for active DC-capacitor voltage equalization of a back-to-back con-

nected DCC system. Without a balancing scheme, the capacitor voltages diverge
from their nominal values, under both steady-state and transient conditions.

• In contrast to the passive-front-end DCC configuration of Chapter 3, where only

the DC-capacitor voltage balancing was effective for a sub-set of the DCC operating
points, DC-capacitor voltage balancing can be achieved for all operating points of
the back-to-back connected DCC system.

• Effectiveness of the proposed SVM-based voltage balancing strategy is demon-

strated under various operational scenarios and controls of a back-to-back con-
nected DCC system which operates as a HVDC system. The balancing strategy
prevents the voltage drift phenomenon of the DC-link capacitor of the HVDC sys-
tem, even for the worst case scenario, i.e. real power flow revesral in which both
DCC units operate at unity power factors and high modulation indices.

• The study results concluded that the proposed SVM strategy and its embedded DC-
capacitor voltage balancing method provide a technically viable switching strategy
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 104

for a five-level DCC-based back-to-back HVDC configuration. The inherent low-

switching propert of the SVM method also minimizes switching losses of the HVDC
configuration. This feature is of significant importance for high-power applications.
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 105

1.4
1.2

Vdc(pu)
1
0.8
0.6
0 0.1 0.2 0.3 0.4
(a)
1
id1(pu) 0.5
0
−0.5
−1
0 0.1 0.2 0.3 0.4

(b)
1
0.5
id2(pu)

0
−0.5
−1
0 0.1 0.2 0.3 0.4

(c)
−0.4
−0.45
P1(pu)

−0.5
−0.55
−0.6
0 0.1 0.2 0.3 0.4

(d)
0.6
0.55
P2(pu)

0.5
0.45
0.4
0 0.1 0.2 0.3 0.4

(e)
0.4
VCaps(pu)

0.3

0.2

0.1
0 0.1 0.2 0.3 0.4

(f) Time(s)

Figure 5.6: Dynamic response of the system of Fig. 5.1 to a step change in the DC voltage
reference when P1 = −P2 = −0.45 pu: (a) DC-link voltage, (b,c) real current components
of AC System-1 and AC System-2, (d,e) real power components of AC System-1 and AC
System-2, and (f) DC-capacitor voltages
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 106

0.2 0.2
0
0

iq1(pu)
−0.2
id1(pu)

−0.4 −0.2
−0.6
−0.4
−0.8
−1 −0.6
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
(a) (b)
0.2 0.3

0 0.2

Q1(pu)
P1(pu)

−0.2 0.1

−0.4 0

−0.1
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
(c) (d)
1 0.4
0.8
0.6 0.2

i (pu)
id2(pu)

0.4
0.2 q2 0
0
−0.2 −0.2
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
(e) (f)
0.6 0.1
0.4 0
P (pu)

Q2(pu)

0.2 −0.1
2

0 −0.2

−0.2
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
(g) (h)
1.2 0.3
V (pu)

1
VCaps(pu)
dc

0.25
0.8

0.6 0.2
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
(i) (k)
Time(s) Time(s)

Figure 5.7: Dynamic response of the system of Fig. 5.1 to step changes in real and
reactive power commands: (a,b) real and reactive current components of AC System-1,
(c,d) real and reactive power components of AC System-1, (e,f) real and reactive current
components of AC System-2, (g,h) real and reactive power components of AC System-2,
(i) net DC-link voltage, and (k) DC-capacitor voltages
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 107

1 0.6
0.4
0.5

P1(pu)
id1(pu) 0.2
0 0
−0.2
−0.5
−0.4
−1
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
(a) (b)
1 0.6
0.4
0.5

P2(pu)
0.2
id2(pu)

0 0
−0.2
−0.5
−0.4
−1
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
(c) (d)
0.1 0.1

0.05 0.05

Q2(pu)
Q1(pu)

0 0

−0.05 −0.05

−0.1 −0.1
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
(e) (f)
1 1

0.5 0.5
ia1(pu)

ia2(pu)

0 0

−0.5 −0.5

−1 −1
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
(g) (h)
1 1

0.9 0.9
m1

m2

0.8 0.8

0.7 0.7

0.6 0.6
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
(i) (j)
1.2 0.3
V (pu)

1.1
VCaps(pu)
dc

1 0.25
0.9

0.8 0.2
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
(k) (l)
Time(s) Time(s)

Figure 5.8: Dynamic response of the system of Fig. 5.1 to a real power reversal demand:
(a,b) real components of AC System-1 current and power, (c,d) real components of AC
System-2 current and power, (e,f) recative power components of AC System-1 and AC
System-2, (g,h) phase-a currents of AC System-1 and AC System-2, (i,j) modulation
indices of DCC-1 and DCC-2, (k) net DC-link voltage, and (l) DC-capacitor voltages
Chapter 5. Five-Level DCC-Based Back-to-Back HVDC System 108

0.2 0.1
0 0

iq1(pu)
−0.2
id1(pu) −0.1
−0.4
−0.2
−0.6
−0.8 −0.3
−1 −0.4
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8
(a) (b)
0.2 0.4

0
0.2

Q (pu)
P1(pu)

−0.2

1
0
−0.4

−0.6 −0.2
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8
(c) (d)
0.8
0.6 0.3
id2(pu)

i (pu)
0.4 0.2

q2
0.2 0.1
0 0
−0.2 −0.1
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8
(e) (f)
0.1
0.4 0
Q2(pu)
P2(pu)

0.2 −0.1

0 −0.2

−0.2
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8
(g) (h)
1 1

0.5 0.5
ia1(pu)

ia2(pu)

0 0

−0.5 −0.5

−1 −1
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8
(i) (j)
1.2 0.3
1.1
V (pu)

VCaps(pu)

1 0.25
dc

0.9

0.8 0.2
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8
(k) (l)
Time(s) Time(s)
Figure 5.9: Dynamic response of the system of Fig. 5.1 to step changes in real and reactive
power demands where the HVDC system interfaces a 50 Hz system to a 60 Hz system:
(a,b) real and reactive components of AC System-1 currents, (c,d) real and reactive power
components of AC System-1, (e,f) real and reactive components of AC System-2 currents,
(g,h) real and reactive power components of AC System-2, (i,j) phase-a currents of AC
System-1 and AC System-2, (k) net DC-link voltage, and (l) DC-capacitor voltages
Chapter 6

A SVM-Based Multi-Module HVDC

Converter System

6.1 Introduction
Chapter 4 and Chapter 5 investigate a five-level DCC topology for STATCOM and HVDC
applications. However, the requirement to economically meet voltage levels, both at AC
and DC sides of a HVDC converter system, e.g. over 132-kV AC and 150-MW, may
necessitate the use of a multi-module VSC configuration. Furthermore, the unequal loss
of semiconductor switches of a multi-level DCC can be a limiting factor for its selection
for extra high power applications [75],[76]. A multi-module VSC system is an alternative
to overcome this disadvantage. In a multi-module VSC, multiples of n-level VSC modules
are connected in series to achieve the required voltage. In this context, one necessary
requirement for the use of a multi-module VSC is the reduction of switching losses and
net harmonic distortion.
This chapter presents a sequential sampling SVM strategy for a multi-module con-
verter system that utilizes two-level VSC modules. The proposed SVM strategy (i)
enables low switching frequency, (ii) eliminates/minimizes AC-side voltage harmonics,
particularly low-order harmonics, and (iii) provides maximum AC-side fundamental volt-
age component. The SVM provides harmonic cancellation/minimization by introducing
appropriate phase-shifts for the corresponding voltage harmonics of the series connected
VSC modules, while maintaining the fundamental voltage components of modules in-
phase to obtain maximum AC-side voltage. The SVM strategy eliminates the need for
complicated (zig-zag) transformer arrangements for harmonic reduction [1], and thus

109
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 110

provides high degree of modularity by utilization of identical transformers for the VSC
modules. The proposed SVM-based multi-module VSC can be used for both SVC and
HVDC applications. The number of VSC modules are selected based on the voltage
requirement of a given application.
This chapter also develops a mathematical model for a four-module VSC-based HVDC
system which links two AC systems. Based on the developed mathematical model, a
control system is designed to control power flow and regulate DC-bus voltage. Harmonics
of the proposed sequential sampling SVM strategy and effectiveness of the controllers are
investigated based on a number of case studies. The studies are performed in time-
domain, using the PSCAD/EMTDC software tool.

6.2 Multi-Module HVDC System Structure

Fig. 6.1 shows a schematic representation of a four-module back-to-back HVDC converter
station. It should be noted that developments presented hereinafter are also conceptually
applicable to a n-module VSC where n > 4. Each converter system, i.e. either VSC-1 or
VSC-2, is composed of four two-level VSC modules which are connected in series with
respect to the AC- and DC-side. Each VSC module is shown in Fig. 6.2. Configuration
of Fig. 6.1 provides a high degree of modularity since all VSC modules, the corresponding
DC-side capacitors, and the AC-side transformers are nominally identical. In the system
of Fig. 6.1, the DC-sides of the two VSC systems are in parallel. It should be noted
that the proposed SVM switching strategy, modeling approach, and the conclusions of
the chapter are equally valid, if VSC-1 and VSC-2 have a common DC-side capacitor
arrangement. Resistor Rp in Fig. 6.1 is not a physical component and represents the
total switching loss of the system. Each AC-side terminal of each VSC system, i.e.
VSC-1 and VSC-2, is connected to the corresponding AC system through a series filter
specified by R and L.
To maximize DC to AC voltage transfer ratio of each four-module VSC, AC-side fun-
damental components of all VSC modules are generated at the same phase-angle. How-
ever, each low-order, AC-side, voltage harmonic is appropriately phase shifted to be can-
celled/minimized when AC-side voltages of modules are added up by the interface trans-
formers. This chapter proposes a SVM based switching strategy, based on a sequential
sampling technique, to provide the required phase shifts for minimization/cancellation
of low-order, AC-side harmonics. In comparison with a SPWM switching strategy, the
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 111

Transformers VSC-1 VSC-2 Transformers

PCC1 PCC 2
ia1 R1 L1 iD11 iD 21 L2 R2 ia 2
vtab11 vtab12
ib1 vtab1 vta1 vdc11 C C vdc 21
vta 2 vtab 2
ib 2
ic1 ic 2
vdc12 C C vdc 22
vas1 vbs1 vcs1 vcs 2 vbs 2 vas 2
Rp Vdc
Ls1 Ls 2

Rs1
vdc13 C C vdc 23 Rs 2

AC System-1 vdc14 AC System-2

C C vdc 24

Figure 6.1: Schematic diagram of a four-module back-to-back HVDC converter station

i D1 j
S a1 j S b1 j S c1 j
iCj
+
v a1 j
vb1 j vdcj
C
v c1 j
-
S a1 j S b1 j Sc1 j

Figure 6.2: Schematic diagram of each VSC module

proposed SVM (i) generates a larger fundamental component of the AC-side voltage, and
(ii) requires a lower switching frequency for each VSC module that in turn results in a
lower switching loss.

6.3 Proposed SVM Switching Strategy

For a high power converter system, e.g. the four-module VSC system of Fig. 6.1, a low
switching frequency SVM scheme is more desirable since it reduces switching loss. The
existing SVM strategies for a two-level VSC module are suitable for low and medium
power applications. Therefore, to meet the switching loss and the harmonic spectrum
targets, the SVM switching strategy of Chapter 2 cannot be directly applied to each VSC
module of VSC systems of Fig. 6.1. To resolve this problem, a low switching frequency
SVM strategy, based on a sequential sample and hold technique is introduced in the
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 112
Samplers Zero Order Hold Units

T 0q ,60q ,120q ,...

V1

60q 60q 60q

T ,  60q ,  120q ,...
N N N
A
V2
Sinusoidal d N
Reference
Signal . d Vout ¦V
i 1
i

. e
. r
( N  1)60 q ( N  1)60 q ( N  1)60 q
T ,  60 q ,  120 q ,...
N N N

VN

Figure 6.3: Principle of sequential sample and hold voltage synthesis technique

following section.

6.3.1 Sequential Sample and Hold Voltage Synthesis

Fig. 6.3 shows a schematic representation of a sequential sample and hold voltage synthe-
sis technique. There are N ideal samplers that sample a sinusoidal reference voltage with
the period of Tref with a sampling period of T . Each sampler samples once in each 60◦
Tref
of the reference voltage, i.e. T = 6
, which results in 6 samples per Tref . The samplers
are followed by N hold units which hold each sampled value during one sampling period.
The output voltages of the individual hold units are added up by an adder. The resultant
output voltage has a harmonic content equivalent to that of a single sample and hold
T
unit with a sampling period of N
, if

• all samplers employ the same sampling rate,

T
• the sampling time of each sample and hold unit has a delay of N
second with
respect to its contiguous sample and hold units, i.e. the units sample the reference
T
voltage sequentially by a delay time of N
.

The output voltages of the units and the resultant output voltage of four sequentially
sample and hold units are illustrated in Fig. 6.4. As Fig. 6.4 shows, the output voltages
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 113

1 Module I
V1(pu) output voltage
0
Reference
−1
0 5 10 15 20 25 30 35 40
1 Module II
V2(pu)

output voltage
0
Reference
−1
0 5 10 15 20 25 30 35 40
1 Module III
output voltage
V3(pu)

0
Reference
−1
0 5 10 15 20 25 30 35 40
1 Module IV
V4(pu)

output voltage
0
Reference
−1
0 5 10 15 20 25 30 35 40
5
output voltage
Vout(pu)

−5
0 5 10 15 20 25 30 35 40

T ime(ms)

Figure 6.4: Output voltages of individual units and the resultant output voltage of the
proposed sequential sample and hold voltage synthesizer (ideal case)

of the individual hold units are not sinusoidal. However, when added up through an
adder, they synthesize a nearly sinusoidal voltage waveform.

Practically, a VSC module can continuously hold a sampled reference value only if the
sampled voltage coincides with one of the switching states of the VSC module (six-pulse
operation). Since, the output voltages of individual units shown in Fig. 6.4 cannot be
generated by a VSC module, therefore, the aforementioned sequential sample and hold
voltage synthesis technique can not be applied to a VSC module. However, the proposed
sequential sample and hold technique can be used in conjunction with the conventional
SVM switching strategy to synthesize a sinusoidal reference voltage of a VSC module as
described in the following section.
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 114

SVM Modulators

Sampling at +
C
t = 0, T, ...

Sampling at
C
t = T/4, 5T/4, ...
Reference vdc
Signals
Sampling at
C
t = 2T/4, 6T/4, ...

Sampling at
C
t = 3T/4, 7T/4, ... -

Figure 6.5: Schematic representation of the sequential sampling SVM technique

6.3.2 Sequential Sampling SVM Technique

In a conventional SVM strategy, a sampled reference vector (for a modulation index
of less than or equal to one) is synthesized during one sampling period, based on the
time average of the two adjacent switching vectors and one zero vector. If the switching
frequency of the SVM switching strategy is low, low-order harmonics appear in its AC-side
voltage waveform. Harmonic minimization/reduction, while maintaining low switching
frequency, in a SVM-based multi-module VSC, can be obtained using the concept of
sequential sample and hold technique as explained in the previous section.
Fig. 6.5 shows a schematic block diagram for implementation of the proposed sequen-
tial sampling SVM technique for each four-module VSC system of Fig. 6.1. The SVM
strategy adopts the same reference vector, Vref , for SVM modulators of all four VSC
modules within each converter system, e.g. VSC-1, of Fig. 6.5. All SVM modulators use
T
the same sampling rate; but sampling instants are delayed by 4
second corresponding
to 15 electrical degrees, Fig. 6.6. Since Vref is the same for all VSC modules of VSC-
1, the corresponding AC-side fundamental-frequency voltage components are in-phase.
However, as a result of the sequential sampling technique, harmonic components are
phase-shifted. The phase-shifts, as shown in the next section, are used for harmonic
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 115

`
VSC #1 VSC #2

V2 V2

V t T /4
V ref ref
t 0
V1 T 15q V1

VSC #3 VSC #4

V2 V2
V
ref

V t 3T / 4
ref t 2T / 4

T 30q T 45q V1
V1

Figure 6.6: Sequential sampling based SVM for the four VSC modules of Fig. 6.1 in
Sector I. As the reference voltage vector rotates in the αβ plane, each modulator samples
at a specified instant.

cancelation at the AC-side of the four-module converter system.

In contrast to a phase-shifted carrier SPWM technique [15], [63], the proposed sequen-
tial sampling SVM generates switching patterns on a three-phase basis which permits a
lower switching frequency. Since the SVM strategy synthesizes Vref based on differ-
ent combinations of switching vectors, as compared with a carrier SPWM technique, it
provides a higher degree of flexibility to (i) minimize the switching frequency, and (ii)
minimize/cancel low-frequency harmonics.

6.3.3 SVM Switching Pattern

In a conventional SVM switching strategy, the sampling rate and switching pattern de-
termine the switching frequency. In the proposed low switching frequency SVM, which
is preferable for high power applications, the sampling rate must be an integer multiple
of 6 to synchronize the PWM and prevent generation of sub-harmonics. Therefore, to
attain a low switching frequency based on the proposed sequential sampling technique,
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 116

sampling sampling sampling

in Sector I in Sector II in Sector III

... V8 V2 V1 V7 V7 V3 V2 V8 ...

T T

Figure 6.7: Proposed space vector switching pattern in Sector I and II

each SVM modulator samples the reference vector at the lowest possible rate of once per
sector (every 60◦ ). Since the switching pattern also affects the switching frequency, it
should (i) have the lowest possible switching frequency to minimize switching losses, and
(ii) provide appropriate phase-shifts for harmonics, up to the order of the first dominant
harmonic, to minimize them when superimposed by the interface transformers. Fig. 6.7
shows a space vector pattern that satisfies these features. As Fig. 6.7 shows, the zero
switching vector is divided into two equal intervals and its two corresponding switching
states are placed at the beginning and end of the switching pattern. One period of the
line voltage of one VSC module is demonstrated in Fig. 6.8. The periodic waveform of
Fig. 6.8 is represented by a Fourier series as
∞
X
f (θ) = an cos(θ) + bn sin(θ). (6.1)
n=1

For the waveform of Fig. 6.8, an and bn are

1
an = ( )(1 − cos(nπ)) ×
nπ
nπ mnπ π mnπ nπ mnπ π
[sin( − sin( + θ) + sin(θ)) − sin( − sin( + θ))
6 6 3 3 6 6 3
nπ mnπ π nπ mnπ π
+ sin( + sin( )) − sin( − sin( + θ))
2 6 3 2 6 3
5nπ mnπ π 5nπ mnπ π mnπ
+ sin( − sin( + θ)) − sin( − sin( + θ) + sin(θ))], (6.2)
6 6 3 6 6 3 3

1
bn = ( )(1 − cos(nπ)) ×
nπ
nπ mnπ π mnπ nπ mnπ π
[cos( − sin( + θ) + sin(θ)) − cos( − sin( + θ))
6 6 3 3 6 6 3
nπ mnπ π nπ mnπ π
+ cos( + sin( + θ)) − cos(( − sin( + θ))
2 6 3 2 6 3
5nπ mnπ π 5nπ mnπ π mnπ
+ cos( + sin( + θ)) − cos( − sin( + θ) + sin(θ))]. (6.3)
6 6 3 6 6 3 3
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 117

Based on the space vector pattern of Fig. 6.7, magnitudes and phase-angles of the fun-
damental, the fifth and the seventh components, as functions of sampling angle θ, are
shown in Fig. 6.9. Based on the sequential sampling SVM, the sampling angles of the
four corresponding VSC modules are θk = k · 15◦ , k = 0, 1, 2, 3. Fig. 6.9 shows that har-
monic phase-angles sharply change from negative to positive in the vicinity of θ = 30◦ .
For four VSC modules, the corresponding harmonics that appear at the AC-sides of the
modules are in almost phase opposition. Thus, superposition of the low-order voltage
harmonics, through the transformers, Fig. 6.1, cancels/minimizes harmonic amplitudes.
To get a better harmonic performance, each sampling period of the SVM Strategy is
divided into two intervals and the switching pattern of the first-half period is repeated
at the second-half period. This results in a switching frequency of fsw = 360 Hz for each
VSC module.

0 2S
sin(  T )

sin(  T )
sin(  T )
sin(  T )
sin(T )

sin(T )

3
3

3
3
S

S
S
S
mS

mS
3

3
sin(  T ) 

sin(  T ) 

5S mS
mS
mS

mS

6
6
6






2
2
6

S
S
S

3
S

6
S mS

5S mS
6

6



6

Figure 6.8: AC-side line voltage of one VSC module

The proposed SVM switching pattern offers the following salient features:

• The switching frequency of each switching device is fsw = 360 Hz, since there is one
sample per each sector for each VSC module. Effective modulation frequency ratio
of a four-module converter system is 4×6=24. Thus, the first group of dominant
harmonic components at the system-side of each four-module converter system are
of order 23 and 25, as illustrated in Fig. 6.10.
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 118
1.5
Fundamental
5th harmonic
7th harmonic

Magnitude (pu)
1

0.5

0
0 10 20 30 40 50 60
Sampling angle θ (deg)

(a)
200
Fundamental
150 5th harmonic
7th harmonic
100
Phase (deg)

50

−50

−100

−150

−200
0 10 20 30 40 50 60
Sampling angle θ (deg)

(b)

Figure 6.9: Magnitudes and phase angles of harmonics versus sampling angle for m = 1
for the VSC modules of the four-module converter system of Fig. 6.1: (a) magnitude, (b)
phase angle

Based on Fig. 6.9 and the harmonic analysis presented in Appendix A, (i) the fun-
damental component of the AC-side voltage varies linearly as a function of modu-
lation index, and (ii) for the whole linear range of modulation, the first dominant
harmonic is of order 23. However, as shown in Fig. 6.9(a), the magnitude of the
fundamental component of the module that samples at θ = 30◦ is reduced. The
reason is that at sampling instant t = T /2, i.e. θ = 30◦ and for m = 1, the on-
duration time of zero voltage vector, based on (2.20), becomes zero. This condition
only applies when m = 1 and results in the amplitude of fundamental component
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 119

to decrease and the amplitudes of the fifth and seventh harmonics to increase.

• In general, for a N-module VSC system that employs the sequential sampling SVM
technique, the effective switching frequency is N · fsw . The mathematical proof is
presented in Appendix A.

• For the whole range of voltage control, magnitudes of harmonics up to order 23 are
significantly reduced, although not completely canceled out. The reason is that in
the sequential sampling SVM for which the number of modules is not too large,
low-order harmonics are not exactly in phase opposition and do not completely
cancel out. Therefore, as shown in Fig. 6.10, residual low-order harmonics appear
in the AC-side voltage spectra of the four-module VSC system of Fig. 6.1.

• For the whole range of voltage control, magnitudes of low order harmonics, i.e. 5th,
7th, and the first group of dominant harmonics, i.e. 23th and 25th are shown in
Fig. 6.11. As Fig. 6.11 shows, amplitudes of 5th and 7th harmonics for a practical
range of modulation index, i.e. m > 0.7, do not exceed 3%.

• In general, the AC-side line voltage of a N -module VSC system has a (2N + 1)-level
waveform. Increasing the number of VSC modules practically eliminates the low-
order harmonics and reduces amplitudes of higher-order harmonics in the vicinity of
frequency N · fsw . Fig. 6.12 shows the simulated AC-side voltage and its spectrum
for one four-module VSC system of Fig. 6.1 that operates based on the proposed
sequential SVM strategy. As shown in Fig. 6.12, the AC-side line voltage has a
nine-level waveform that is analogous to that of a five-level DCC. Fig. 6.13 shows
the simulated AC-side voltage and its spectrum for an eight-module VSC system.
As shown in Fig. 6.13, the AC-side line voltage has a seventeen-level waveform that
is analogous to that of a nine-level DCC. The waveforms of Fig. 6.12 and Fig. 6.13
are normalized with respect to their corresponding DC-bus voltages, i.e. 4vdc and
8vdc , respectively. Therefore, the physical fundamental component of the AC-side
voltage of an eight-module VSC system is twice of that of the four-module VSC
system. In comparison with Fig. 6.12, Fig. 6.13 shows that the harmonic spectrum
is significantly improved.

• Due to equal switching frequency of the devices, the switching loss is equal for all
switches. Compared with a multi-level DCC topology, this is a salient feature for
application of a multi-module VSC configuration for extra high power cases.
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 120

Amplitude (pu) 0.8

0.6

0.4

0.2

0
1
0.9
0.8 25
Mo 0.7 20
dul 0.6 p )
u
atio 0.5 15
qu e ncy (
n in 0.4 10 Fre
dex 0.3 5
0.2 0

Figure 6.10: AC-side line voltage spectra of the four-module VSC system of Fig. 6.1
versus modulation index m

120
23th
25th
100 5th
7th

80
1
100xV /V
h

60

40

20

0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Modulation index

Figure 6.11: Harmonics as percentages of the fundamental component versus modulation

index for VSC modules of the four-module converter system of Fig. 6.1
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 121

0.5

V (pu)
0

tab
−0.5

−1
0 5 10 15 20 25 30
Time (msec)

(a)
1
Harmonics (pu)

0.8
0.6
0.4
0.2
0
0 5 10 15 20 25 30 35 40 45 50
Frequency (pu)

(b)

Figure 6.12: AC-side voltage of a four-module VSC that operates based on the proposed
sequential sample and hold VSC: (a) line voltage, and (b) line voltage spectrum

0.5
V (pu)

0
tab

−0.5

−1
0 5 10 15 20 25 30
Time (msec)

(a)
1
Harmonics (pu)

0.8
0.6
0.4
0.2
0
0 5 10 15 20 25 30 35 40 45 50
Frequency (pu)

(b)

Figure 6.13: AC-side voltage of an eight-module VSC that operates based on the proposed
sequential sample and hold VSC: (a) line voltage, and (b) line voltage spectrum
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 122

6.4 System Model

This section presents a fundamental-frequency model for each four-module converter
system of Fig. 6.1 to design the converter system controllers and evaluate harmonics and
dynamic performance of the overall HVDC system under the proposed SVM switching
strategy.
First, the fundamental-frequency models of the VSC systems, in abc frames, are
developed. Then, the models are transferred to dq frames to deduce a fundamental-
frequency dq model for the overall system. The dynamic model of the HVDC system is
developed based on the following assumptions:

• Nominal voltages of both AC Systems are the same, however, frequencies need not
be the same.

• The corresponding power switches, diodes and passive components of the VSC
modules are identical.

Synchronization signals of the control systems of VSC-1 and VSC-2 are deduced from
PCC1 and PCC2, Fig. 6.1, respectively.

6.4.1 System Model in abc Frame

To obtain an abc model of the system of Fig. 6.1, first the mathematical equations that
govern the AC sides of VSC-1 and VSC-2 are derived. Phase-a terminal voltage of VSC
module j of VSC-1, Fig. 6.1, is

vta1j (t) = vdcj Sa1j , j = 1, 2, 3, 4 (6.4)

where Sa1j is the switching function of the switch that connects phase-a terminal of mod-
ule j to its corresponding positive DC-capacitor terminal, and vdcj is the DC-capacitor
voltage of module j. Substituting for Sa1j in terms of its Fourier series components in
(6.4)
∞
X
vta1j (t) = √1 m1 vdcj [sin(ω1 t + α1+) a(6q±1)j sin((6q ± 1)ω1 t + δ(6q±1)j )], (6.5)
3
q=1

where m1 and α1 are respectively the modulation index and the phase-angle of the ref-
erence voltage waveform which are the same for all VSC modules, and ω1 is the angular
frequency of the switching functions of the module. a(6q±1)j and δ(6q±1)j (in degrees) are
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 123

amplitude and phase angle of harmonic order (6q ± 1) of the AC-side voltage of module
j. As discussed in the previous section, amplitudes of voltage harmonics of each VSC
module are considerable. However, since harmonics with the same order have almost
opposite phases, they are cancelled/minimized when added up in the four-module VSC
configuration of Fig. 6.1.
The net terminal voltage of VSC-1, Fig. 6.1, is the sum of terminal voltages of the
corresponding four VSC modules, through the interface transformers, i.e.
4
X
vta1 (t) = vta1j (t). (6.6)
j=1

Substituting for vta1j (t) from (6.5) in (6.6), and considering only the fundamental-frequency
component of vta1 (t), we deduce
1
vta1 (t) = √ m1 Vdc sin(w1 t + α1 ). (6.7)
3
Analogous to (6.7), voltage equations of VSC-2 of Fig. 6.1 are
1
vta2 (t) = √ m2 Vdc sin(w2 t + α2 ), (6.8)
3
where ω2 , m2 and α2 are respectively angular frequency of the switching functions, mod-
ulation index and phase-angle of the modulating waveforms of VSC-2. The three-phase
voltage equations corresponding to AC System-1 of Fig. 6.1 are
dia1
vta1 = R1 ia1 + L1 + vas1 , (6.9a)
dt
dib1
vtb1 = R1 ib1 + L1 + vbs2 , (6.9b)
dt
dic1
vtc1 = R1 ic1 + L1 + vcs2 . (6.9c)
dt
Analogous to (6.9), voltage equations of AC System-2 of Fig. 6.1 are
dia2
vta2 = R2 ia2 + L2 + vas2 , (6.10a)
dt
dib2
vtb2 = R2 ib2 + L2 + vbs2 , (6.10b)
dt
dic2
vtc2 = R2 ic2 + L2 + vcs2 . (6.10c)
dt
For the DC-link circuit of Fig. 6.1, the DC-bus voltage dynamics can be described as
dvdc11 dvdc21 1
C +C = − Vdc − (iD11 + iD21 ), (6.11)
dt dt Rp
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 124

where
iD11 (t) = Sa11 ia1 (t) + Sb11 ib1 (t) + Sc11 ic1 (t), (6.12)
iD21 (t) = Sa21 ia2 (t) + Sb21 ib2 (t) + Sc21 ic2 (t), (6.13)
iD11 and iD21 are the DC-link currents of module 1 of VSC-1 and VSC-2, respectively,
and Sa21 , Sb21 and Sc21 represent switching functions of the AC sides of VSC-1 and VSC-
2, respectively. Since all modules are identical, for the DC-link arrangement of Fig. 6.1
Vdc
vdc1j = vdc2j = 4
. Thus, substitution for vdc11 and vdc21 in terms of Vdc in (6.11) yields
dVdc Vdc
Ceq =− − (iD11 + iD21 ), (6.14)
dt Rp
C
where Ceq = 2
is the equivalent capacitor seen by each VSC module. Switching functions
Sa11 , Sb11 and Sc11 are represented by the corresponding fundamental components as
   
Sa11 (t) sin(ω1 t + α1 )
  1  
   
 Sb11 (t)  = √ m1  sin(ω1 t + α1 − 2π ) . (6.15)
  3  3 
2π
Sc11 (t) sin(ω1 t + α1 + 3
)
Substituting for Sa11 , Sb11 and Sc11 from (6.15) in (6.12) , we deduce
1 2π 2π
iD11 (t) = √ m1 (sin(ω1 t + α1 )ia1 + sin(ω1 t + α1 − )ib1 + sin(ω1 t + α1 + )ic1 ). (6.16)
3 3 3
Analogous to (6.16), for iD2j (t) of Fig. 6.1, we can deduce
1 2π 2π
iD21 (t) = √ m2 (sin(ω2 t + α2 )ia1 + sin(ω2 t + α2 − )ib2 + sin(ω2 t + α2 + )ic2 ). (6.17)
3 3 3
Substituting for iD11 (t) from (6.16) and iD21 (t) from (6.16) in (6.14), we have
2
dVdc Vdc 1 X 2π 2π
Ceq = − −√ mk (sin(ωk t+αk )ia1 +sin(ωk t+αk − )ib2 +sin(ωk t+αk + )ic2 ).
dt Rp 3 k=1 3 3
(6.18)
Equations (6.9), (6.10) and (6.18) represent a fundamental-frequency model of the HVDC
system of Fig. 6.1 in the abc frame.

6.4.2 Transformation of abc Model to dq-Frame

Hereinafter, to avoid unnecessary repetitions in the formulation, the quantities associated
with VSC-1 and AC System-1 are indexed by “1”, while those of VSC-2 and AC System-
2 are indexed by “2”. The AC System-k k = 1, 2, variables are transferred to the
corresponding dq frame by [74]
fqdok = Kk fabck , (6.19)
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 125

where transformation matrix Kk is

 
2π 2π
cos θk cos(θk − 3
) cos(θk + 3
)
2
 2π 2π


Kk =  sin θk sin(θk − ) sin(θk + ) , (6.20)
3 3 3 
1 1 1
2 2 2

Z t
θk (t) = ωk (t)dt. (6.21)
0

Transforming variables of AC System-k as given by (6.9) and (6.10), based on (6.19), we

deduce

didk
vtdk = Rk idk + Lk − Lk ωk iqk + vsdk , (6.22a)
dt
diqk
vtqk = Rk iqk + Lk + Lk ωk idk + vsqk , (6.22b)
dt

where vtdk and vtqk are

1
vtdk = √ mk Vdc cos(αk ), (6.23a)
3
1
vtqk = √ mk Vdc sin(αk ). (6.23b)
3
mk and αk are calculated as

vtqk
αk = tan−1 ( ), (6.24a)
vtdk
√ q
2 2
3 vtdk + vtqk
mk = . (6.24b)
Vdc

By substituting (6.19) into (6.18), we deduce

dVdc Vdc 3 3
Ceq =− − √ m1 (iq1 sin α1 + id1 cos α1 ) − √ m2 (iq2 sin α2 + id2 cos α2 ). (6.25)
dt Rp 2 3 2 3

Equations (6.22) and (6.25) represent a fundamental-frequency dq model of the HVDC

system of Fig. 6.1.

6.5 AC-Side Current Control of VSC Systems

Control parameters of each VSC module of Fig. 6.1 are the corresponding modulation
indices and phase-angles of the reference voltage waveforms. Direct- and quadratic-axis
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 126

terminal voltage components of each four-module VSC system, based on (6.22), are
decoupled through the following change of variables

vtdk = udk − Lk ωk iqk + vsdk , (6.26a)

vtqk = uqk + Lk ωk idk + vsqk . (6.26b)

Substituting for vtdk and vtqk from (6.26) in (6.22), we obtain:

didk Rk 1
= − idk + udk , (6.27a)
dt Lk Lk
diqk Rk 1
= − iqk + uqk . (6.27b)
dt Lk Lk
Equation (6.27) represents two first-order, decoupled subsystems where udk and uqk are
new control signals that are generated by two independent PI-controllers. One PI-
controller processes (idref k − idk ) to produce udk , and the other takes the same action on
(iqref k −iqk ) to produce uqk . vsdk and vsqk are two feed-forward terms added to the control
action, for a faster response to the AC system voltage disturbances. Each dq-frame is
synchronized to, and aligned with the corresponding PCC voltage such that vsqk = 0.
vsdk is the d-axis voltage of the bus where the VSC-k is connected to the AC source.
Phase and magnitude of the modulating waveform are then deduced from (6.24). The
d-axis PI-controller is defined by:
Z t
udk = Kipk edk + Kiik edk dt, (6.28)
0

where edk = idref k − idk . Thus, the open-loop gain in the frequency domain becomes
Kiik 1
Kipk (s + Kipk
) Lk
lk (s) = . (6.29)
s s +R k
Lk

Lk Rk
Choosing Kipk = τik
and Kiik = τik
yields (6.30) and (6.31) for the open-loop and the
closed-loop systems, respectively,
1
lk (s) = , (6.30)
τik s
idk (s) 1
Gi (s) = = . (6.31)
idref k (s) τik s + 1

Time constant τik determines response time of the closed-loop system, and is usually cho-
sen between 1.5 ms to 5 ms. The q-axis current controller is designed in a similar manner.
Fig. 6.14 shows a block diagram representation of the proposed current controller.
 Chapter 6. A SVM-Based Multi-Module HVDC Converter System 127

vsdk S a1k

idrefk edk udk vtdk S b1k

+ αk Sc1k
−
idk Lk ω k
Sa2k
Sb2k
Sc 2 k
S a 3k
iqk Lk ω k S b 3k
− eqk u qk vtqk
mk Sc 3k
iqrefk +
S a 4k
Sb 4 k
Sc4k
vsqk θ k = ωk t

vsak vsbk vsck

Figure 6.14: Block diagram of the decoupled dq-frame current controllers

6.6 DC-Bus Voltage Control

To control Vdc , we manipulate (6.25) to become more tractable for control design. Mul-
tiplying both sides of (6.25) by (Vdc ), we obtain

d( 21 Ceq Vdc2 )
=
dt
V2 3 3
− dc − √ (id1 m1 Vdc cos α1 + iq1 m1 Vdc sin α1 ) − √ (id2 m2 Vdc cos α2 + iq2 m2 Vdc sin α2 ).
Rp 2 3 2 3
(6.32)

Substituting for vtdk and vtdk from (6.23), into (6.32), we obtain

d( 12 Ceq Vdc2 ) V2 3 3
= − dc − (vtd1 id1 + vtq1 iq1 ) − (vtd2 id2 + vtq2 iq2 ). (6.33)
dt Rp 2 2
2
Vdc
The left side of (6.32) is the rate of energy variations in Ceq . Term Rp
is the power
dissipation in Rp . Terms 32 (vtd1 id1 + vtq1 iq1 ) and 23 (vtd2 id2 + vtq2 iq2 ) in (6.33) represent
instantaneous outgoing power at the AC-side terminals of VSC-1 and VSC-2, respectively.
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 128

If the total instantaneous power of the interface reactors are neglected, then 32 (vtd1 id1 +
vtq1 iq1 ) = 23 vsd1 id1 . Real and reactive power components delivered to each AC system are
also given by
3
P2 = −P1 ≈ vsd iP xref , (6.34a)
2
3
Qk = − vsd iqref k . (6.34b)
2
Thus, (6.33) is reduced to a Single-Input Single-Output (SISO) system as described by
(6.35)
d( 12 Ceq Vdc2 ) V2 3 3
= − dc − vsd1 id1 − vsd2 id2 . (6.35)
dt Rp 2 2
Assuming vsd = vsd1 = vsd2 , we have
d( 21 Ceq Vdc2 ) Vdc2 3
=− − vsd (id1 + id2 ). (6.36)
dt Rp 2
Let us define the d-axis current references idref 1 and idref 2 , as

idref 1 = −iP xref + iV cref , (6.37a)

idref 2 = iP xref + iV cref , (6.37b)

where iP xref is the current command corresponding to the desired power exchange be-
tween AC System-1 and AC System-2. A positive iP xref means a positive power flow
command from AC System-1 to AC System-2, and vice versa. iV cref commands small
real current drawn from both grids to compensate for the losses represented by Rp , and
to regulate the DC-bus voltage . Responses of current controllers (6.31) to the command
(6.37) are:

id1 = −iP x + iV c , (6.38a)

id2 = iP x + iV c , (6.38b)

Substituting for id1 and id2 from (6.38) into (6.36), and re-arranging the result, we obtain
dVdc2 2 6vsd
+ Vdc2 = − iV dc . (6.39)
dt Rp Ceq Ceq
Equation (6.39) describes dynamics of the DC-bus voltage of the HVDC system of
Fig. 6.1. In (6.39), Vdc2 is the output signal and iV c is the control signal. In the Laplace
domain, (6.39) can be written as
3 1
Vdc2 (s) = − Rp vld Rp Ceq iV c (s). (6.40)
2 2
s+1
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 129

The transfer function from iV cref to Vdc2 is

3 1
Vdc2 (s) = − Rp vld Rp Ceq Gi (s)iV cref (s) = (6.41)
2 2
s + 1
3 1
− Rp vld Rp Ceq iV cref (s).
2 ( 2 s + 1)(s + τ1i )

iV cref is determined by a PI-controller for zero steady-state error. Thus, a DC-bus voltage
controller is suggested as
Kvp s + Kvi
iV cref (s) = ev (s), (6.42)
s
2
where ev = Vdcref − Vdc2 .
In (6.42), PI-controller gains Kvp and Kvi can be optimized based on linear system
methods such as root-locus, Bode plots, etc, to achieve a satisfactory system performance.

6.7 Performance Evaluation

6.7.1 Study System

The HVDC system of Fig. 6.1 that operates based on the proposed sequential sampling
SVM technique, in conjunction with the control system of Fig. 6.14, is simulated in the
PSCAD/EMTDC environment. Table 6.1 shows parameters of the system of Fig. 6.1
used for the reported studies. The studies are conducted:

• To demonstrate harmonic performance of the proposed sequential sampling SVM

technique.

• To evaluate dynamic performance of the overall HVDC system of Fig. 6.1, including
power circuitry and control sub-systems, under various operating scenarios.

6.7.2 Study Results

Harmonics

Initially, both VSC-1 and VSC-2 are operating at unity power factor, i.e. iqref k = 0, and
0.9 pu power is flowing from VSC-1 to VSC-2. Since both VSC-1 and VSC-2 operate
based on the same sequential sampling technique and similar voltage and current values,
only the waveforms corresponding to VSC-1 are presented. Figs. 6.15(a) and (c) show
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 130

Table 6.1: Parameters of the study system of Fig. 6.1

Parameters of the Study System Value

Each VSC nominal power (and Sb ) 300 MVA
Each AC system nominal voltage (and Vb ) 500 kV
Each AC system Short Circuit Ratio (SCR) 5
Nominal Frequencies f1 and f2 60 Hz
R1 and R2 0.001 pu
X1 and X2 0.01 pu
Rs1 and Rs2 0.04 pu
Xs1 and Xs2 0.2 pu
Each transformer voltage rating 125 kV/30 kV
Each transformer MVA rating 75
Transformer leakage inductance 5%
Nominal net DC voltage 240 kV
Resistance Rp 10 kΩ
VSC-1 switching frequency fsw1 360 Hz
VSC-2 switching frequency fsw2 360 Hz
DC-link Capacitor C 5000 µ F
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 131

instantaneous line voltage of VSC-1 terminal and its top VSC module, respectively.
Comparison of the corresponding harmonic spectra, i.e. Figs. 6.15(b) and (d), shows
that all harmonic components of VSC-1, and in particular the low frequency components,
are effectively minimized by the proposed SVM strategy. The first group of dominant
harmonics of the four-module VSC system are of order 23 and 25, as shown in Fig. 6.15(b).
However, as explained in Section 6.3.3, residual low-order harmonics do exist in the
vicinity of the first group of dominant harmonics. As Fig. 6.15(b) shows, magnitudes of
individual harmonics of the VSC-1 terminal voltage exceed 1%, however, the resultant
current distortion meets the IEEE-519 standard limits.
Fig. 6.15(e) shows line current of phase ’a’ of AC System-1, and Fig. 6.15(f) shows the
corresponding current harmonic spectrum. Fig. 6.15(f) indicates that even without any
shunt filter, harmonic content of the current is well within the acceptable limits, and low-
order harmonic components are practically canceled out and negligible. Figs. 6.15(g) and
(h) show the net and per module DC-voltage waveforms. Figs. 6.15(g) and (h) indicate
that the DC-voltage ripple is less than 2%.

Real/Reactive Power Control

The system is initially under a steady-state operating condition. Vdcref is set to its
nominal value, i.e. 1 pu, and iP xref is set to zero corresponding to zero real power flow
in the system. Both VSC systems exchange no reactive power with the corresponding
AC systems. At t = 0.05 s, reactive current component of AC System-2 is changed
corresponding to 0.4 pu reactive power delivery to AC System-2. At t = 0.2 s, real power
flow from AC System-1 to AC System-2 , i.e. iP xref = 0.6 pu, is commanded. Fig. 6.16
shows dynamic response of the system to the step changes in power demand.
Figs. 6.16(a) and (b) show corresponding changes to id2 and iq2 , imposed by the
controllers, due to the step changes in real and reactive power demands. Figs. 6.16(a)
and (b) demonstrate that the d- and q-axis current components of AC System-2 are
well decoupled. Figs. 6.16(c) and (d) show real and reactive power exchanged with AC
System-2. Fig. 6.16(e) shows the net DC-link voltage response and demonstrates that
the net DC-link voltage, subsequent to the disturbances, is well regulated.
Figs. 6.16(f) and (g) show changes in real and reactive current components of AC
System-1 to meet real power demand in response to changes in iP xref and iqref 1 . Figs. 6.16(h)
and (k) show that real and reactive power exchanged with AC System-1 are proportional
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 132

to real and reactive current components of Figs. 6.16(f) and (g).

Fig. 6.16 shows that the control system properly tracks the specified signals. Fig. 6.16
also illustrates that the control system effectively regulates the system operating condi-
tions in response to step changes in real and reactive power demands.

Real-Power Flow Reversal

Initially, 0.58 pu real power is flowing from AC System-1 to AC System-2 and Vdcref is
set to 1 pu. Both VSC-1 and VSC-2 are operating at unity power factor. At t = 0.1 s,
iP xref is ramped from 0.73 pu to −0.73 pu within 10 ms. This change is corresponding
to a power flow reversal from 0.58 pu to −0.58 pu, from AC System-1 to AC System-2.
Fig. 6.17 shows dynamic response of the system to the real power reversal command.
Figs. 6.17(a) and (b) show change in id1 and P1 due to the real power reversal command.
Figs. 6.17(c) and (d) show the corresponding changes in id2 and P2 , respectively. As
Figs. 6.17(a) to (d) show, real current components of both AC systems and consequently
real power components are reversed as the real power reversal command is activated.
Reactive current components of both AC Systems are shown in Figs. 6.17(e) and (f).
Figs. 6.17(g) and (h) show phase-a currents of AC System-1 and AC System-1, respec-
tively. Figs. 6.17(g) and (h) show that the currents change their phases during the power
flow reversal period. Fig. 6.17 show that the control system properly tracks the power
reversal command and the operating conditions are well regulated in response to the
power demand.

Disturbance Rejection Capability

Initially, Both VSC-1 and VSC-2 operate at unity power factor, i.e. iqref k = 0, and
iP xref = 0.6 pu. The system is subjected to a single-phase to ground fault, with fault
resistance of R = 0.36 pu, at the middle of the line of AC System-2. The fault occurs
at t = 0.05 s and is self-cleared at t = 0.2 s. Fig. 6.18 shows transient behavior of the
system during and subsequent to the fault. Fig. 6.18(a) shows current waveform of the
faulty line of AC System-2. Fig. 6.18(b) shows that the net DC voltage is maintained
at the corresponding reference during and subsequent to the fault. Figs. 6.18(c) and (d)
show that real and reactive current components of AC System-2 contain double frequency
components due to the unbalanced fault condition. Figs. 6.18(e) and (f) show real and
reactive current components of AC System-1. The study results of Fig. 6.18 illustrate
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 133

disturbance rejection capability of the control system, in that it effectively maintains the
operating conditions of the system during and subsequent to the fault.

Discussions

The study results presented in previous sections are carried out based on the assumption
that the AC systems are adequately stiff and vsdk , k = 1, 2, are fairly constant at their
nominal values; therefore, the assumption of vsd1 = vsd2 is plausible. If the AC systems of
Fig. 6.1 are not adequately stiff, i.e. SCR < 5, then, the corresponding PCC voltages and
vsdk strongly and nonlinearly influenced by the corresponding reactive power components
exchanged by VSC-1 and VSC-2. When the exchanged reactive power components of AC
systems are not identical, the assumption of vsd1 = vsd2 is not precise and (6.36) yields
a poor approximation. In this case, the disturbance rejection and reference tracking of
DC-bus voltage controller require longer time to regulate the DC-bus voltage at its pre-
disturbance and reference value. Nevertheless, the patterns of responses of the HVDC
system variables for different case studies are fairly similar to the case when the AC
systems ate stiff.

6.8 Summary and Conclusions

This chapter proposes a SVM-based switching strategy for a multi-module VSC system
in which each module is a two-level VSC unit. The proposed SVM strategy is based
on a sequential sampling technique that provides (i) in-phase fundamental components
at the AC-side voltages of individual modules, (ii) harmonic cancellation/minimization
at the AC-side voltages of the individual modules, and (iii) a low switching frequency.
Harmonic cancellation/minimization at the net AC-side voltage of the VSC system is
included in the switching strategy of individual modules and superposition of module
voltages through the AC-side transformers.
This chapter also proposes application of a N -module VSC (N = 4) as the building
block for a back-to-back HVDC converter system. The multi-module VSC-based HVDC
system is that it provides modularity and scalability for use in extra high-power appli-
cation. A fundamental-frequency mathematical model of the HVDC system that links
two asynchronous AC systems is developed. The developed model is used to design the
HVDC converter system controllers to control real power flow and regulate the DC-bus
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 134

voltage. Performance of the HVDC system, based on the developed controllers and the
proposed SVM switching strategy is investigated. The time domain simulation studies
conclude that:

• Based on a 360 Hz switching frequency of each VSC module, the four-module

configuration can eliminate/minimize low-order harmonics and the first group of
dominant voltage harmonics are of order 23 and 25.

• Based on the proposed SVM strategy, the effective modulation frequency, in terms
of AC-side voltage harmonics is 6 × 4 = 24, although the switching frequency of
each module is 360 Hz.

• The study results also indicate that proposed SVM switching strategy performs
satisfactorily under various transient scenarios of the HVDC system.

• Based on the proposed sequential sampling technique, the multi-module VSC sys-
tem meets the requirements imposed by IEEE standard 519, in terms of line current
and voltage distortions.
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 135

1
0.5

vab1(pu)
0
−0.5
−1
0.35 0.36 0.37 0.38 0.39 0.4

(a) Time(s)
0.05
0.04

v (pu)
0.03

ab1h 0.02
0.01
0
0 5 10 15 20 25 30 35 40 45 50

(b) f(pu)
0.5
vtab11(pu)

−0.5
0.35 0.36 0.37 0.38 0.39 0.4

(c) Time(s)
0.2

0.15
vab11(pu)

0.1

0.05

0
0 5 10 15 20 25 30 35 40 45 50

(d) f(pu)
1
0.5
ia1(pu)

0
−0.5
−1
0.35 0.36 0.37 0.38 0.39 0.4

(e) Time(s)
0.01
i (pu)

0.005
a1h

0
0 5 10 15 20 25 30 35 40 45 50

(f) f(pu)
1.05
vdc(pu)

0.95
0.35 0.36 0.37 0.38 0.39 0.4

(g) Time(s)
0.3
vdc1(pu)

0.25

0.2
0.35 0.36 0.37 0.38 0.39 0.4

(h) Time(s)

Figure 6.15: Steady state current and voltage waveforms of the four-module converter
system of Fig. 6.1: (a,b) line voltage of VSC-1 terminal and its spectrum, (c,d) line
voltage of top VSC module of VSC-1 and its spectrum, (e,f) AC System-1 current and
its spectrum, (g) net DC-link voltage, (h) per-module DC-capacitor voltage
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 136
1

0.5

id2(pu)
0

−0.5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(a)
0.5

iq2(pu)
0

−0.5

−1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(b)
0.8
0.6
P2(pu)

0.4
0.2
0
−0.2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(c)
0.6

0.4
Q2(pu)

0.2

−0.2
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(d)
1.1

1
Vdc(pu)

0.9

0.8

0.7
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(e)
0.5
id1(pu)

−0.5

−1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(f)
0.5
iq1(pu)

−0.5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(g)
0.2

0
P1(pu)

−0.2

−0.4

−0.6
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(h)
1

0.5
Q1(pu)

−0.5

−1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

(k) Time(s)

Figure 6.16: Dynamic response of the system of Fig. 6.1 to step changes in real and
reactive power demands: (a,b) real and reactive components of AC System-2 currents,
(c,d) real and reactive power components of AC System-2, (e) net DC-link voltage, (f,g)
real and reactive components of AC System-1 currents, and (h,k) real and reactive power
components of AC System-1
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 137

0.5

id1(pu)
0

−0.5

−1
0 0.1 0.2 0.3 0.4

(a)
0.6
0.4
0.2

P1(pu)
0
−0.2
−0.4
−0.6
0 0.1 0.2 0.3 0.4

(b)
1

0.5
id2(pu)

−0.5

−1
0 0.1 0.2 0.3 0.4

(c)
0.6
0.4
P2(pu)

0.2
0
−0.2
−0.4
−0.6
0 0.1 0.2 0.3 0.4

(d)
0.1

0.05
iq1(pu)

−0.05

−0.1
0 0.1 0.2 0.3 0.4

(e)
0.1

0.05
iq2(pu)

−0.05

−0.1
0 0.1 0.2 0.3 0.4

(f)
1

0.5
ia1(pu)

−0.5

−1
0 0.1 0.2 0.3 0.4

(g)
1

0.5
ia2(pu)

−0.5

−1
0 0.1 0.2 0.3 0.4

(h) Time(s)

Figure 6.17: Dynamic response of the system of Fig. 6.1 to a real power reversal demand:
(a,b) real components of AC System-1 current and power, (c,d) real components of AC
System-2 current and power, (e,f) reactive current components of AC System-1 and AC
System-2, and (g,h) phase-a currents of AC System-1 and AC System-2
Chapter 6. A SVM-Based Multi-Module HVDC Converter System 138

0.5

ia2(pu)
0

−0.5

−1
0 0.1 0.2 0.3 0.4

(a)
1.1

1.05
Vdc(pu)

0.95

0.9
0 0.1 0.2 0.3 0.4

(b)
1

0.8
id2(pu)

0.6

0.4

0.2
0 0.1 0.2 0.3 0.4

(c)
0.4
iref
q2
0.2 i
iq2(pu)

q2

−0.2
0 0.1 0.2 0.3 0.4

(d)
−0.2
−0.4
i (pu)

−0.6
d1

−0.8
−1
0 0.1 0.2 0.3 0.4

(e)
0.4
ref
iq1
i
0.2
iq1(pu)

q1

−0.2
0 0.1 0.2 0.3 0.4

(f) Time(s)

Figure 6.18: Transient response of the system of Fig. 6.1 to a temporary single-phase
to ground fault: (a) AC System-2 phase-a current, (b) DC-link voltage, (c,d) real and
reactive components of AC System-2 currents, and (e,f) real and reactive components of
AC System-1 currents
Chapter 7

Conclusions

7.1 Summary
This thesis develops two Space Vector Modulation (SVM) switching strategies for high-
power Voltage Sourced Converter (VSC) configurations. The first SVM strategy is devel-
oped for a n-level Diode-Clamped Converter (DCC) (n > 3) configuration. The second
one is for a multi-module VSC in which each module is a conventional two-level VSC.
This thesis mainly concentrates on the five-level DCC and the four-module VSC system,
although the developments are conceptually applicable to the n-level and the N -module
configurations.
For a multi-level DCC:

• A computationally efficient SVM algorithm, based on a classifier Neural Network

(NN), is proposed. The proposed SVM strategy facilitates real-time implementa-
tion of the SVM switching strategy of the n-level DCCs by eliminating the time-
consuming calculations. Therefore, adequate processor execution time is saved to
carry out other functions, e.g. the calculations required for DC-capacitor voltage
balancing task.

• The DC-capacitor voltage drift phenomenon of the passive-front-end, five-level

DCC is analyzed and formulated in terms of the DCC operating indices, i.e. modu-
lation index and AC-side power factor. To counteract the voltage drift phenomenon,
a voltage balancing strategy is proposed. The proposed balancing strategy is based
on augmenting the proposed SVM algorithm and taking advantage of the redun-
dant switching states to minimize a quadratic cost function associated with the

139
Chapter 7. Conclusions 140

voltage deviations of the DC-capacitors.

• A DC-capacitor voltage balancing strategy for a back-to-back connected five-level

DCC system is also proposed. The strategy is a modified version of the DC-voltage
balancing strategy of the passive-front-end DCC. The modified strategy is based
on coordination between the SVM modulators of the two back-to-back connected
DCC units.

For a four-module VSC system:

• A SVM switching strategy, based on a sequential sampling technique, is pro-

posed and evaluated. The proposed SVM strategy provides harmonic cancella-
tion/minimization at the net AC-side voltage of the four-module VSC system, by
introducing appropriate phase-shifts among the same-order voltage harmonics of
the corresponding VSC modules, while the fundamental voltage components of the
VSC modules are kept in-phase to obtain the maximum net AC-side voltage.

7.2 Conclusions
The general conclusions of this thesis are:

• Proper operation of a passive-front-end five-level DCC requires equal voltages across

the DC-side capacitors. Without an active voltage equalization (balancing) scheme,
the DC-capacitor voltages are subject to drift in both the steady-state and transient
conditions. The voltage drift phenomenon of the DC-capacitors is due to the non-
zero average values of the DC-side intermediate branch currents that flow through
the capacitors when the DCC transfers non-zero real power. The average values of
the DC intermediate branch currents are functions of the DCC modulation index
and the AC-side power factor. To maintain balanced voltages, the average values
of the DC intermediate branch currents should be forced to zero. The SPWM-
based switching strategies cannot provide DC-capacitor voltage balancing and thus
necessitates auxiliary power circuitry to maintain balanced voltages. This is due
to the inherent non-zero average values of the DC-intermediate branch currents in
a SPWM-switched DCC.

• To counteract the voltage drift phenomenon of a DCC, a computationally efficient

SVM strategy is proposed. The proposed SVM strategy reduces the overhead
Chapter 7. Conclusions 141

calculation time and saves sufficient processor execution time to carry out the DC-
capacitor voltage balancing task. The proposed SVM-based switching strategy
takes advantage of redundant switching states of the DCC to nullify the average
values of the DC intermediate branch currents and counteract the DC-capacitor
voltage drift phenomenon, with no requirement for additional power circuitry. The
salient features of the balancing strategy are (i) online calculations of SVM to select
the best switching states, with the minimum calculation effort, (ii) minimization
of switching frequency by using three adjacent switching states in each switching
sequence, (iii) minimization of the THD content of the AC-side voltage by using
all available voltage levels of the DCC.

• A passive-front-end five-level DCC has practical limitations for real power exchange.
The analysis indicates that a passive-front-end, five-level DCC cannot provide volt-
age balancing capability under real power conversion conditions without de-rating
the AC-side voltage. The proposed balancing strategy is effective to carry out the
balancing task within a subset of theoretical limits.

• In general, as the number of levels of a passive-front-end DCC increases, the number

of redundant switching states increases as well. This provides higher degrees of
freedom to balance the DC-capacitor voltages. Consequently, the region in which
voltage balancing, based on the proposed SVM strategy can be achieved, becomes
larger.

• Without an active balancing scheme, the capacitor voltages of a back-to-back con-

nected DCC system diverge from their nominal values, under both steady-state and
transient conditions. The proposed SVM-based balancing strategy equalizes the ca-
pacitor voltages for all theoretical operating points of the back-to-back connected
five-level DCC system, irrespective of the amount and direction of real power flow
in the DCC system.

• The proposed SVM strategy for a multi-module VSC system, that is based on
a sequential sampling technique, reduces the low-order harmonic magnitudes and
minimizes the net AC-side voltage harmonics of a multi-module VSC system.

Based on the proposed SVM strategy, the switching frequency of each VSC module
is kept at 6 pu (360 Hz) for a 60 Hz system, while the effective modulation frequency
Chapter 7. Conclusions 142

of a four-module VSC system is 6 × 4 = 24. Thus, the first corresponding group of

dominant harmonics are of order 23 and 25.

The technical feasibility of the proposed SVM strategies for the five-level DCC and the
four-module VSC system are investigated and validated based on time-domain simulation
studies in the context of STATCOM and back-to-back HVDC system applications. The
studies conclude that:

• The proposed SVM strategy, based on a classifier NN and the embedded DC-
capacitor voltage balancing scheme, provide a technically viable switching strategy
for a five-level DCC-based STATCOM and also a back-to-back HVDC system.

• The proposed SVM switching strategy, based on the sequential sampling technique,
performs satisfactorily under various transient scenarios of a four-module VSC-
based HVDC system.

7.3 Thesis Contributions

The main contributions of this thesis are as follows:

• A fast SVM switching strategy for a n-level DCC (n ≥ 3) is proposed. The proposed
strategy is fast enough to facilitate the voltage balancing task of a DCC for real-time
implementation.

• A DC-capacitor voltage balancing strategy is proposed that overcomes the capacitor

voltage drift phenomenon of the passive-front-end, five-level DCC. The proposed
voltage balancing strategy guarantees proper operation of a passive-front-end, five-
level DCC within a specific range of operation, with no requirements for additional
power circuitry and without de-rating the AC-side fundamental voltage component.

• A DC-capacitor voltage balancing strategy is developed for a back-to-back con-

nected five-level HVDC system. In comparison with the existing strategies, the de-
veloped strategy enables DC-capacitor voltage balancing of the back-to-back HVDC
system under all operating conditions, without the need for auxiliary power circuits
and/or off-line calculations.
Chapter 7. Conclusions 143

• A sequential sampling SVM strategy for a multi-module HVDC converter system

is proposed. The proposed SVM switching strategy (i) enables low switching fre-
quency, and (ii) minimizes low-order harmonics of the net AC-side voltage of the
VSC system.

7.4 Future Work

The following topics are suggested for the future research:

• Investigation of the proposed SVM balancing strategy for a back-to-back five-level

DCC for large adjustable-speed motor drive systems to eliminate/minimize trans-
formers, (ii) to reduce dv/dt stress, and (iii) to eliminate additional hardware for
DC-voltage balancing task.

• Investigation of the proposed SVM-based multi-module VSC system for HVDC

tie-lines and multi-terminal HVDC systems.

• Investigation of the proposed SVM-based balancing strategy for the next generation
of multi-level converter topologies, e.g. the active neutral point converter topology
[77].
Appendix A

Harmonic Analysis of a SVM-Based

N-Module VSC

This section develops an analytical model to determine harmonic components of a N -

module VSC that employs the proposed sequential sampling SVM technique of Chapter 6.

The most well-known analytical method to determine the harmonic components of a

SPWM-switched VSC was first developed in [78]. While formulation of a SVM algorithm
is conceptually different from that of a SPWM, the harmonic analysis of a SVM-switched
VSC can be carried out based on that of a SPWM switching strategy. The analysis utilizes
the relationship between SPWM and SVM techniques [79]. Adding an offset signal to
the three-phase references of an arbitrary SPWM modulator, it can be transformed into
an equivalent SVM modulator [79]. For a SVM modulator, distribution of zero voltage
vectors within a sampling interval plays the same role as an offset signal added to a
SPWM modulator [51], [79]. The offset signal for the SPWM modulator depends on
the distribution of zero voltage vector within a sampling interval and placement of zero
switching states in a switching pattern.

A.1 Harmonic Analysis of one VSC module

For the SVM pattern used in Chapter 6 and with respect to the distribution of zero
switching states in Fig. 6.7, the equivalent reference waveform of phase-a SPWM modu-

144
Appendix A. Harmonic Analysis of a SVM-Based N-Module VSC 145
y
2S

vdc

S S 0 S S
x

2 2

Figure A.1: Modulation function of SVM-based VSC module

lator of one VSC module, within one period, is [79]



 2m sin(ωt) − 1 0 ≤ ωt ≤ 2π/3,


u(ωt) =  2m sin(ωt − 2π/3) − 1 2π/3 ≤ ωt ≤ 4π/3, (A.1)



−1 4π/3 ≤ ωt ≤ 2π.

The mathematical model of the SVM modulator can be derived based on its corre-
sponding SPWM equivalent of (A.1). According to the phase-a waveform function, the
modulated waveform is constructed based on a double Fourier series [51], [78]. The mod-
ulation function of phase-a is shown in Fig. A.1, where x(t) = ωc t, and y(t) = ωt. ωc
and ω are the carrier and fundamental frequencies, respectively. The modulated phase-a
waveform, i.e. modulation function, is defined by z = f (x, y), where z is equal to vdc
in the shaded region of Fig. A.1, and equal to zero out of the region. The boundary is
expressed by


 ±πm sin y 0 ≤ y ≤ 2π/3,


π
x = ± (1 + u(y)) = ±πm sin(y − π/3) 2π/3 ≤ y ≤ 4π/3, (A.2)
2 



0 4π/3 ≤ y ≤ 2π.

The complex Fourier harmonic component form can be developed for the double variable
controlled waveform f (x, y), as
±∞
X ±∞
X
f (x, y) = Cqn ej(qω+nωc )t , (A.3)
q=0 n=0
Appendix A. Harmonic Analysis of a SVM-Based N-Module VSC 146

where

1 Z 2π Z 2π
Cqn = 2 f (x, y)e−j(qω+nωc ) dxdy. (A.4)
2π 0 0

For the line voltage, we deduce

P±∞ P±∞ P P±∞
fL (x, y) = q=0 n=0 Cqn e
j(qω+nωc )t
− ±∞
q=0 n=0 Cqn ej(q(ωt−2π/3)+nωc t) =
P±∞ P±∞ (A.5)
−j2qπ/3 j(qω+nωc )t
q=0 n=0 Cqn (1 − e )e .

fL (x, y) can be expressed in the real form as

±∞
X ±∞
X
fL (x, y) = mvdc sin(ωt) + vdc Aqn sin(qω + nωc )t, (A.6)
q=±1 n=1

where Aqn , in terms of the Bessel function, is expressed as

Aqn = 2
nπ 2
sin( 2qπ
3
)
hP
±∞ 2k−1 qπ
(A.7)
i
k=1 J2k−1 (mnπ) (2k−1)2 −q 2 (2(−1)
k−1
sin( 2k−1
6
π) − 1) | 2k−16 =±q + 2π
3
sin( 3
) | 2k−16 =±q .

A.2 Harmonic Analysis of a N -Module VSC

In a N -module VSC system that utilizes the sequential sampling technique, the corre-
sponding sampling instants of contiguous VSC modules should be delayed by

2π
4t = . (A.8)
N ωc

This delay corresponds to shifting the carrier phase by 4t in a phase-shifted carrier

SPWM technique. Based on (A.5), phase-a voltage of VSC module p is
P±∞ P±∞ p−1 p−1 P±∞ P±∞
fp (x, y) = q=0 n=0 Cqn ej[qωt+n(ωc t+ N
2π)]
= ej N
2nπ
q=0 n=0 Cqn ej(qω+nωc )t
p−1 (A.9)
= ej N
2nπ
f (x, y).

For a N-module converter, phase-a voltage is

N
X p−1
fN (x, y) = ej N
2nπ
f (x, y), (A.10)
p=1

and the line voltage is


N
X  N f (x, y) n = h.N
j p−1 2nπ L
fN L (x, y) = e N fL (x, y) =  , (A.11)
p=1 0 otherwise
Appendix A. Harmonic Analysis of a SVM-Based N-Module VSC 147

where h is an integer. Substituting for fL (x, y) from (A.6) in (A.11), we have

±∞
X ±∞
X
fN L (x, y) = N mvdc sin(ωt) + N vdc AqnN sin(qω + nN ωc )t, (A.12)
q=±1 n=1

where

AqnN = 2
nN π 2
sin( 2qπ
3
)
hP
±∞ 2k−1 qπ
(A.13)i
k=1 J2k−1 (mN nπ) (2k−1) 2 −q 2 (2(−1)
k−1
sin( 2k−1
6
π) − 1) | 2k−16 = ±q + 2π
3
sin( 3
) | 2k−16 =±q .

Based on (A.12) and (A.13), we conclude that:

• The amplitude of the fundamental component of a N-module VSC is N times of

that of one VSC module.

• The lowest side-band harmonic is around N ωc , i.e. the equivalent switching fre-
quency is N · fsw .
Appendix B

Analysis of DC-Capacitor Voltage

Drift Phenomenon of a
SPWM-Switched, Back-to-Back
Connected Five-Level DCC System

For the SPWM-switched back-to-back connected five-level DCC system of Fig. 5.1, the
average values of the DC intermediate branch currents of DCC-k, i.e. ī3k , ī2k , and ī1k ,
k = 1, 2, are obtained from (3.15) to (3.17) as
 r
 3 −1 1 4m2k −1

 Imk cos(φk )(−mk π + 4mk sin ( 2mk ) + ), 0.5 ≤ mk ≤ 1,

 2π m2k
i3k = (B.1)




 3 m I cos(φ ) 0 ≤ mk ≤ 0.5,
4 k mk k

i2k = 0, (B.2)
 r
 3 −1 1 4m2k −1

 − 2π Imk cos(φk )(−mk π + 4mk sin ( 2mk ) + ) 0.5 ≤ mk ≤ 1,

 m2k
i1k = (B.3)




 − 3 m I cos(φ ) 0 ≤ mk ≤ 0.5,
4 k mk k

The necessary conditions to balance (equalize) the DC-capacitor voltages are

i31 = i32 , (B.4a)

i21 = i22 , (B.4b)
i11 = i12 . (B.4c)

148
Appendix B. Analysis of DC-Capacitor Voltage Drift Phenomenon of a SPWM-Swit

Considering the power balance equation between the two DCC units, we have

Im1 (m1 Vdc ) cos(φ1 ) = Im2 (m2 Vdc ) cos(φ2 ). (B.5)

From (B.5), we deduce

m2 cos(φ2 )
Im1 = Im2 . (B.6)
m1 cos(φ1 )
By substituting for ī3k , ī2k , and ī1k , k = 1, 2, from (B.1) to (B.3), and Im1 from (B.6) in
(B.4) we deduce
v v
u 2
u
1 u 4m1 − 1 1 u 4m22 − 1
−1
m2 (−m1 π + 4m1 sin ( )+ t ) = m (−m π + 4m sin −1
( ) + t ).
2 1 2 2 2
2m1 m1 2m2 m2
(B.7)
Equation (B.7) is satisfied if m1 = m2 . Based on (B.7) and also (B.1) to (B.3), the
operating conditions for which the average values of the DC-intermediate branch currents
become zero and the DC-capacitor voltage balancing without additional control efforts
achieved, are

• Both DCC units operate at zero power factors, i.e. no real power is exchanged.

• Both DCC units, regardless of the values of the AC-side power factors, operate
with equal modulation indices, i.e. m1 = m2 .

Therefore, when the modulation indices of both DCC units are not the same and non-
zero real power is exchanged, a SPWM-based switching strategy is not capable to carry
out the voltage balancing task. This conclusion is consistent with the findings of [32].
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