MOSFET

 Metal Oxide Semiconductor Field Effect Transistor.

n-channel enhancement type MOSFET

 nMOS : p-type substrate and n-type doped S and D.

 pMOS : n-type substrate and p-type doped S and D.
 A conducting channel is formed between D and S through applied gate voltage.
 Enhancement MOSFET : No conducting channel at zero gate bias.
 Depletion MOSFET : A conducting channel already exists at zero gate bias.

Threshold voltage: VTO = The value of VGS needed to create the conducting channel.

MOSFET operation (NMOS) :

Case 1 :

VDS = +ve, VGS = 0,VBody = 0.

No current flows as VGS <VTO.

Cut off region.

Case 2 :

VGS = +ve , VDS=some constant +ve value.

VGS >= VTN (channel will be formed)

ID will flow from S to D in linear region, proportional to VDS.

Hence, the channel region acts as “voltage controlled resistor”.

ID(linear) = µn COx W/2L [2(VGS- VTN) VDS- VDS2]

µn = Mobility of electrons.

W = Width of channel.

L = Length of channel.

COx = Gate capacitance / unit area.

Case 3 :

VGS>= VTN ,VDS is increasing +ve.

As the drain voltage is increasing,the channel depth at the Drain is reducing.

Hence for a certain value of VDS=VDS(sat), the channel at the Drain is reduced to 0.

This is called pinch-off point or pinch-off voltage.

Case 4 :

VDS > VDSAT

 This region of operation is called “Saturation Region”.

 Inversion layer near drain vanishes,channel end voltage remains constant
equal to VDSAT.
 Pinched off section absorbs most of the excess voltage drop (V DS – VDSAT )
and high field region is formed between channel end and drain boundary.
 Thus electrons coming from Source to channel end are drifted to Drain as
IDSAT.

IDSAT= µnCOxW/2L (VGS-VTN)2

MOSFET operating in Saturation Region

 µN>µP
i.e. mobility of electrons is more than mobility of holes. ( Thus, NMOS is
faster dan PMOS).
Hence,while constructing CMOS, W/L ratio of NMOS and PMOS is designed so that this
mismatch is avoided. (W/Lnmos<W/Lpmos)

O/P Characteristics of EMOSFET:

Transfer characteristics of EMOSFET:

PMOS:

For p-type MOSFET- All the above points will be with respect 2 holes instead of electrons.

Thus,the polarity of voltages will be reversed.

VTO will be negative in case of PMOS and VGS<VTO.

Current-voltage equations of the n-channel MOSFET:

ID=0 , for VGS<VT

ID(lin)=µn .COX.W/2L[2(VGS-VT)VDS-VDS2] for VGS≥VT

and VDS<VGS-VT

ID(sat)= µn.COX.W/2L(VGS-VT)2.(1+λ.VDS) for VGS≥VT

and VDS≥VGS-VT

Current-voltage equations of the n-channel MOSFET:

ID=0, for VGS>VT

ID(lin)=µn .COX.W/2L[2(VGS-VT)VDS-VDS2] for VGS≤VT

and VDS>VGS-VT

ID(sat)= µn.COX.W/2L(VGS-VT)2.(1+λ.VDS) for VGS≤VT

and VDS≤VGS-VT
Transfer characteristics of DMOSFET:

In Depletion type MOSFET the channel exists even if V GS=0. If Vds(+ve) is applied ID flows. It
means the channel is not broken like EMOS.

Depletion mode: If negative voltage is applied at the gate, electrons in n-channel will get
repelled. This will generate a depletion region and reduce channel width. So, I D will reduce.
If VGS≤ VGS(OFF) the channel width becomes zero and hence the current ID=0.

Enhancement mode: If positive voltage is applied at the gate, electrons will be attracted
towards the SiO2 layer and the channel will be enhanced. This will increase I D similar to
EMOSFET.
 SCALING AND ITS EFFECTS
Definition: The reduction in the physical size of the MOSFET keeping the geometrical ratios
constant is known as scaling.

 The design of high-density chips in VLSI technology requires that the packing density
of MOSFETs used in the circuits is high, and therefore the sizes of the transistors be
as small as possible. Hence, scaling of MOSFETs is done.
 The advantages of scaling, thus, are:
1. Reduction in size of the chip.
2. Increase in packing density.
3. Fabrication of multi-functional chips.

Types of Scaling:

 There are two types of scaling:-

1. Full scaling (constant Field Scaling)
2. Partial scaling (constant Voltage Scaling)
 These two types of scaling have unique effects on the operating characteristics of the
MOS transistor.
 To describe device scaling, a constant scaling factor S>1, is used. All horizontal and
vertical dimensions of the large-sized MOS transistor are then divided by this scaling
factor to obtain the scaled device.
 The extent of scaling is determined by the fabrication technology and more
specifically, the minimum feature size.

Full-scaling (constant field scaling)

 This scaling option attempts to preserve the magnitude of the internal electric fields
in the MOSFET, while the dimensions are scaled down to a factor of S. To achieve
this, all potentials must be scaled down proportionally, by the same scaling factor.
 Doping density is increased by a factor of S, in order to maintain charge-field
relationship using Poisson’s equation.
 The following table shows the effect of scaling on current-voltage characteristics of
MOSFET--

PARAMETER BEFORE SCALING AFTER SCALING

1. Width of the channel W W/S
2. Length of the channel L L/S
3. Thickness of the oxide tox tox /S
4. Supply voltage VDD VDD /S
Vth
5. Threshold voltage Vth /S
6. Oxide capacitance per unit area Cox S Cox
7. Gate capacitance Cg Cg/S
 8. Drain current(linear) ID(lin) ID(lin)/S
9. Drain current(saturation) ID(sat) ID(sat)/S
10. Ron RON RON
11. Time constant tON tON/ S
12. Static power dissipation Pstatic = VDD.ID Pstatic /S2
13. Power density ψ ψ
3
14. Current density J S J
15. Dynamic power dissipation Pdynamic=CL.VDD2.F.β/2 Pdynamic/S 2
16. Doping Density NA or ND S NA or S ND

 The aspect ratio W/L of the MOSFET remains unchanged after scaling.
 The gate oxide capacitance is given by:
C’ox= ε’OX/t’OX

=S.εOX/tOX

=S.COX
C’g = C’OX.W’.L’= (S.COX).(W/S).(L/S)

=Cg/S

Since the gate oxide capacitance is scaled by a factor of S, the transient characteristics,
i.e. charging and discharging time of the scaled device is improved.

 The linear drain current of the scaled MOSFET is found as:-

I’D(lin) = µn.C’ox.W[2(V’GS-V’Tn)V’DS-V’DS2]/2L

= µn..SCox.W[2(VGS-VTn)VDS-VDS2]/2L.S2

= ID(lin)/S

 Similarly, the saturation drain current of the MOSFET is given as:-

I’D(sat) = µn.C’oxW(VGS’-V’Tn)2/2L

= µn..SCox.W(VGS-VTn)2/2L.S2

= ID(sat)/S

 Since the drain current flows between the source and the drain terminals, the
instantaneous power dissipation by the device is given as:-

Pstatic=ID.VDD

We can see that full scaling reduces both the drain current and drain to source
voltage by a factor of S; hence the power dissipation of the transistor will be reduced
by the factor S2.
 P’static= I’D.V’DD

= ID.VDD/S2

= Pstatic/S2

 The significant reduction in the power dissipation is one of the most

advantageous features of full scaling.
 The device area reduces by S2; hence the power density per unit area remains
unchanged for the scaled device.

Ψ’= P’static/W’.L’

= (Pstatic/S2)/(W.L/ S2)

= Pstatic/W.L = ψ

 The current density is also increased by a factor of S3.

J’ = I’D/W’.L’

= (ID/ S )/(W.L/ S2) = S3. J

 The dynamic power dissipation of the scaled device is given by-

P’dynamic=C’L.V’DD2.F’.β/2

Where C’L=C’g=Cg/S

F’=1/t’ON=1/R’on.C’g=S.F

V’DD=VDD/S

β = switching activity factor

so, P’dynamic=(CL/S).(VDD/S)2.(S.F).β/2=Pdynamic/S2

Though we achieve small size with reduced power dissipation, one of the major
disadvantages of constant field scaling is that each individual scaled device will require its
own power supply; thereby invalidating the use of a global power supply for the chip. In
order to use a global supply voltage for the chip, a number of level-shifter circuits would be
required. Hence, constant voltage scaling is preferred over full-scaling.

Partial Scaling(Constant voltage scaling)

In constant voltage scaling, all dimensions of the MOSFET are reduced by a factor of S, as in
full-scaling. The power supply voltage and the terminal voltages remain unchanged. The
doping densities must be increased by a factor of S2, in order to preserve the charge-field
relations.

PARAMETER BEFORE SCALING AFTER SCALING

1. Width of the channel W W/S
2. Length of the channel L L/S
3. Thickness of the oxide tox tox /S
4. Supply voltage VDD VDD
5. Threshold voltage Vth Vth
6. Oxide capacitance per unit Cox S Cox
area
7. Gate capacitance Cg=COX.W.L Cg/S
8. Drain current(linear) ID(lin) S ID(lin)
9. Drain current(saturation) ID(sat) S ID(sat)
10. Ron RON RON/S
11. Time constant tON= RON. Cg tON/ S 2
12. Static power dissipation Pstatic = VDD.IDD S Pstatic
12. Power density ψ S3ψ
13. Current density J S 3J
14. Dynamic power dissipation Pdynamic=CL.VDD2.F.β/2 S Pdynamic
15. Doping Density NA or ND S2 NA or S2 ND

 The gate-oxide capacitance per unit area is increased by a factor of S, so the

transconductance parameter is also increased by S.
 Since the terminal voltages remain unchanged, the linear drain current of the
scaled MOSFET is given as:-

I’D(lin) = µn.Cox’.W[2(VGS’-V’Tn)V’DS-V’DS2]/2L

= µn..SCox.W[2(VGS-VTn)VDS-VDS2]/2L

=S.ID(lin)

 The saturation drain current is increased by S after constant voltage scaling. This
means that the drain current density (current per unit area) is increased by a factor
of S3.

I’D(sat) = µn.Cox’W(VGS’-V’Tn)2/2L

= µn..SCox.W(VGS-VTn)2/2L

= S. ID(sat)
  Since the drain current is increased by S while the drain to source voltage
remains unchanged, the power dissipation of the MOSFET increases by a factor
of S.

P’static=I’D.V’DD

= S ID.VDD

= S.Pstatic

 The power density (power dissipation per unit area) is found to increase by S3.

Ψ’=P’static/W’.L’

= (S.Pstatic)/(W.L/ S2)

= S3.Pstatic/W.L = S3. ψ

 The current density is also increased by a factor of S3.

J’= I’D/W’.L’

= S3. ID/W.L

= S3. J

 The dynamic power dissipation of the scaled device is given by-

P’dynamic=C’L.V’DD.F’.β/2

Where C’L=C’g=Cg/S

F’=1/t’ON=1/R’on.C’g=S2.F

V’DD=VDD

β = switching activity factor

so, P’dynamic=(CL/S).(VDD)2.(S2.F).β/2=S.Pdynamic

Thus constant voltage scaling may be preferred over constant field scaling in many practical
cases because of the external voltage level constraints, however, constant voltage scaling
increases the drain current density and the power density by a factor of S3.This may cause
serious reliability problems for the scaled transistor.
EFFECTS OF SCALING:

OXIDE BREAKDOWN / DIELECTRIC STRESS:

It is a drawback only for constant voltage scaling.

As thickness of oxide t ox is decreased, Evert=Vgs/tox increases. Therefore there will be large

electric field across silicon-dioxide layer, if this field is larger than a breakdown field; the
silicon-dioxide layer may sustain permanent damage during operation, leading to device
failure. This effect is known as oxide breakdown.

GATE TUNNELING:

As the thickness of oxide is scaled down by a factor s, according to quantum mechanics

there is finite probability that the carriers will tunnel through the oxide, which results in
leakage current in gate. This is known as gate tunneling.

Probability of tunneling drops off exponentially with increase in t ox. To avoid gate tunneling
tox should not be below 15 A.

ELECTRONMIGRATION:

This is the major drawback of constant voltage scaling.It causes wear out of metal through
the formation of voids. High current densities lead to electron wind that causes metal atoms
to migrate over time.

This effect is seen more in case of Al wires than in Cu wires.

SUBTHRESHOLD CURRENT(Drain-induced barrier lowering):

If the gate bias voltage is not sufficient to invert the surface, i.e. V gs<Vto, the carriers in the
channel face potential barrier that blocks the flow. Increasing the gate voltage reduces the
potential barrier and eventually allows the electron flow under the influence of channel
electric field.

If the drain voltage is increased, the potential in the channel decreases, leading to drain-
induced barrier lowering(DIBL). The reduction in the potential barrier eventually allows the
electrons to flow between source and drain, even if gate-to-source voltage is lower than
threshold voltage. The channel current that flows under these conditions is known as
subthreshold current.
The equation for subthreshold current is given as follows:

ID(subthreshold)=qDnWxcn0 . eqΦr/kT. eq/kT (A.Vgs+B.Vds)/LB

Where xc = subthreshold channel depth,

Dn = electron diffusion co-efficient,

LB = length of barrier region in channel,

Φr = reference potential.

PUNCH THROUGH:

For large drain bias voltages, the depletion region surrounding the drain can extend farther toward
the source and the two depletion regions can eventually merge. This condition is termed as punch
through.

The gate voltage loses its control upon the drain current and the current rises sharply once punch
through occurs.
 SHORT -CHANNEL EFFECTS
A MOS transistor is said to be a short channel device if its channel length is the same order
of magnitude as the depletion region thickness of the source and drain junctions.

Alternatively, a MOSFET can be defined as a short channel device if channel length L is

approximately equal to the source and drain junction depth xj.

The short channel effects are:

1)VELOCITY SATURATION:

The electron drift velocity is given by:

Vd= µE

where µ —> mobility of the electrons

E—>electric field intensity

There are two types of electric feilds :

Elat=Vds/L

Evertical=Vgs/tox

Where L is the length of the channel

tox is the thickness of the oxide layer.

The velocity is proportional to the field at lower values of the field.It tends to saturate at
high channel electric fields.
The value of the electric field at which vd saturates is denoted as Ec(critical value of E).

Vd s
As Vds increases,channel length decreases,thus, E(lat)= keeps on increasing.
L

The drift velocity of the electrons keeps on increasing linearly upto Ec and then saturates.

µ E(lat )
Vd=
1+ E(lat )/LEc

Velocity saturation affects the current-voltage characteristics.

Consider the saturation mode drain current

Cox W ( Vgs−Vtn)2
Id(sat)=µn
2 L 1+(Vgs−Vtn)/ LEc

In the absence of short channel,

(Vgs−Vtn)
<< 1
LEc

(Vgs−Vtn)2
∴ Id(sat)= µn Cox W
2 L 1

When the length of the channel decreases,

(Vgs−Vtn)
>>1
LEc

Cox (Vgs−Vtn)
∴ Id(sat)= µn .W . . Ec
2 1

This means,
 • ID,sat is proportional to Vgs–Vth rather than (Vgs – Vth)2

• ID,sat is independent on L

This accounts for the linear portion of the graph in the transfer characteristics.

2)MOBILITY DEGRADATION:

In short channel MOS transistors,the carrier velocity in the channel is also a function of the
normal(vertical) electric field component Evertical.

Vgs
Evertical=
tox

Since this field also influences the collisions suffered by carriers in e surface region,the
surface mobility is reduced with respect to the bulk mobility.

The dependence of surface electron mobility on the vertical electric field can be expressed
as:

1
µn=µno
1+ η(Vgs−Vtn)

where µn → mobility of the electron when Vgs is normal

µno→mobility of the lectrons when Vgs increases

η→empirical parameter

as Vgs increases,the number of electrons attracted towards the source increases.

Thus,current density increases.But due to short channel,the number of collisions increases

and hence mobility decreases.

3)CHANNEL LENGTH MODULATION:

Leff=L-2Loverlap

Consider the inversion layer charge Q1 that represents the total mobile charge on the
surface.

The inversion layer at the source end is given by:

Q1(y=0) = -Cox(Vgs-Vtn)

At the drain end:

Q1(y=L)=-Cox(Vgs-Vds-Vtn)

At saturation,Vds=Vgs-Vtn

thus, Q1(y=L)= -Cox(0)=0

i.e: the channel is pinched off at the drain end.

If Vds increases further,larger portion of the channel is pinched

∴ L' =L−Δ L

The portion of the channel between pinch-ff and drain will be in the depletion mode.

The channel length at pinch remains the same i.e: Vd(sat)

Cox . W
Id(sat) =µn .(Vgs-Vtn)2
2 L'
 Cox . W
=µn .(Vgs-Vtn)2
2 L−ΔL

Cox . W
=µn 2 ΔL .(Vgs-Vtn)2
L(1− )
L

ΔL
Let (1- )=1-λVds
L

where λ is the channel length modulation parameter.

Cox . W
∴ I d(sat)= µn .(Vgs-Vtn)2
2 L(1−λVds)

= Cox . W
µn .(Vgs-Vtn)2 (1+λVds)
2 L

Because resistance is proportional to length, shortening the channel decreases its

resistance, causing an increase in current with increase in drain bias for a MOSFET operating
in saturation.

4)THRESHOLD VOLTAGE:

In short channel MOS transistors, the n+ drain and source diffusion regions in the p-
substrate also induce a significant amount of depletion charge.The channel length reduces
and hence the number of charge carriers reduces and the threshold voltage reduces.
This threshold voltage is given by:

∴VT0(short channel)=VT0 - 𝜟VT0

Where VT0 is the zero bias threshold voltage.It is threshold shift or reduction due to short
channel effect.

Let 𝜟Ls and 𝜟LD represent the lateral extent of the depletion regions associated with the
source junction and the drain junction, respectively. Then, the bulk depletion region charge
contained within the trapezoidal region is:

ΔLs+ ΔLd
QB0= - (1- )√ 2 q ℇ siNa .∨2ϕ∨¿ ¿
2L

Here, xdS and xdD represent the depth of the pn-junction depletion regions associated with
the source and the drain, respectively. The edges of the source and drain diffusion regions
are represented by quarter-circular arcs, each with a radius equal to the junction depth, x j.
The vertical extent of the bulk depletion region into the substrate is represented by x dm. The
junction depletion region depths can be approximated by

2 ℇ si
√
xds= (
qNa
) .ϕ ⃘ ⃘ ⃘ ⃘

xdD=(√ 2qNa
ℇ si
) .(ϕ ⃘ +Vds)
With the junction built in voltage:

ϕ ⃘ =(kT/q) ln(ND.NA/ni2)

∴(xj+xdD)2=x2dm +(xj +𝜟LD)2

∴𝜟LD2 +2xj. 𝜟LD+ xdm2- xdD2-2xj. xdD=0

∴ 𝜟LD=-xj+√ xj 2−( x 2−x 2 ) +2 xjx dD

≅ xj (√ 1+2 xdD /xj -1)

∴ 𝜟Ls≅ xj (√ 1+2 xdS / xj -1)

Now, the amount of the threshold voltage reduction DVT0 due to short-channel effects can
be found as:

1 xj
𝜟VT0= √ 2 q ℇ siNa .∨2 ϕ∨¿ ¿. . [ (√ 1+2 xdD /xj -1)+√ 1+2 xdS / x j -1)]
Cox 2L
PUNCH THROUGH:

Also, since the channel length is comparable to the drain and source depletion region
thickness,for large drain-bias voltage, the drain depletion will go on increasing and will
eventually merge with the source depletion region resulting in punchthrough. The gate
voltage loses control of the current resulting in a sharp rise in current which may damage
the transistor.

CHANNEL HOT ELECTRON EFFECT OR HOT CHANNEL DEGRADATION:

Channel hot electron effect

It is one of the limitations of scaling. In a small geometry device there exists a large electric
field across the channel regions. At high field, electrons gain very high velocity and hence
very high kinetic energy. Later these electrons (hot electrons) impinge the S iO2 layer. Then
SiO2 will undergo impact ionization which will permanently destroy the surface charge
density at Si- SiO2 interface hence:

1. The threshold voltage VTO of device will change

2. Reduces the drain current capability of device

3. Degrades the device characteristics.

This phenomenon by which device characteristic is degraded due to the impact ionization of
SiO2 layer is called hot carrier degradation o channel hot electron effect.
 RESISTIVE LOAD INVERTER

The basic structure of the resistive-load circuit is as shown in the figure 3.3. An
enchancement-type nMOS transistor acts as the driver device and the load consists of
simple linear resistor RL. Since the following analysis concentrates on the static behavior of
the circuit, the output load capacitance is not shown in this figure.

To simplify the calculations, the channel-length modulation effect will be neglected and
note that the source and the substrate terminals of the driver transistor are both connected
to the ground; hence VSB = 0.

Input voltage range Operating mode

Vin < VTO Cut – off

VTO <= Vin < Vout + VTO Saturation

Vin >= Vout + VTO linear

For input voltages smaller than the threshold voltage V TO, the transistor is in cut-off, and
does not conduct any drain current. Since the voltage drop across the load resistor is equal
to zero, the output voltage must be equal to the power supply voltage, V DD. As the input
voltage is increased beyond VTO, the driver transistor starts conducting a nonzero drain
current. Note that the driver MOSFET is initially in saturation, since its drain-to-source
voltage (VDS= Vout) is larger than (Vin - VTO).

Thus ,

IR = kn/2 (Vin - VTO)2

With increasing input voltage, the drain current of the driver also increases, and the output
voltage Vout starts to drop. Eventually, for input voltages larger than Vout + V TO, the driver
transistor enters the linear operation region. At larger input voltages, the tranistor remains
in linear mode, as the output voltage continues to decrease.

IR = kn/2 [2 (Vin – VTO)Vout – Vout 2 ].

The various operating regions of the driver tranistor and the corresponding input-output
conditions are listed in table shown above.

Figure 3.2 shows the voltage transfer characteristic of a typical resistive-load inverter circuit,
indicating the operating modes of the driver transistor and the critical voltage points on the
VTC. Now, we start with the calculation of the five critical voltage points, which determine
the steady-state input-output behavior of the inverter.

Calculation of VOH

First we note that the output voltage Vout is given by

Vout = VDD – RL.IR

When the input voltage Vin is low i.e. smaller than the threshold voltage of the driver
MOSFET, the driver transistor is cut-off. Since the drain current of the driver transistor is
equal to the load current, IR = ID = 0. It follows that the output voltage of the inverter under
these conditions is:

VOH = VDD

Calculation of VOL

To calculate the ouput low voltage VOL , we assume that the input voltage is equal to V OH ,
i.e., Vin = VOH = VDD . Since Vin – VTO > Vout in this case, the driver transistor operates in the
linear region. Also note that the load current IR is

IR = ( VDD - Vout) / RL

Using Kirchhoff Current Law (KCL) for the output node, i.e., I R = ID , we can write the
following equation:

( VDD – VOL )/ RL = (kn/2)[2 ( VDD- VTO ) VOL – VOL 2 ]

This equation yields a simple quadratic in V OL , which is solved to find the value of the output
low voltage.

VOL 2 – 2( VDD – VTO + (kn RL) -1 ) VOL + (2/ kn RL ) VDD =0

Note that the two possible solutions of above equation, we must choose the one that is
physically correct i.e., value of the output low voltage must be between 0 and V DD . The
solution of above equation is given below. It can be seen that the product ( k n RL ) is one of
the important design parameters that determine the value of VOL.

VOL = VDD – VTO + (kn RL) -1 - √ ((VDD – VTO + (kn RL) -1) 2 –(2 VDD / kn RL ))

Calculation of VIL
By definition, VIL is the smaller of the two input voltage values at which the slope of the VTC
becomes equal to (-1); i.e., dVout/dVin = -1. Simple inspection of the VTC figure shows that
when the input is equal to VIL , the output voltage ( Vout ) is only slightly smaller than V OH.
Consequently, Vout > Vin – V TO, and the driver transistor operates in saturation. We start
our analysis by writing the KCL for the output node,

VDD – Vout / RL = ( kn /2) (Vin - VTO) 2

To satisfy the derivative condition, we differentiate both sides of above equation with
respect to Vin, which results in the following equation:

(-1/ RL ) (dVout/dVin) = kn (Vin - VTO)

Since the derivative of the output voltage with respect to the input voltage is equal to (-1) at
VIL, we can substitute dVout/dVin = -1 in above equation.

(-1/ RL ) (-1) = kn ( VIL - VTO)

Solving above for VIL we get,

VIL = VTO + ( kn RL ) -1

The value of the output voltage when the input is equal to V IL can also be found by
substituting above equation in first equation of this section

Vout(Vin = VIL ) = VDD – ( kn RL / 2) (VTO – VTO + (kn RL) -1) 2

= VDD – (2 kn RL ) -1

Calculation of VIH
VIH is the larger of the two voltage points on VTC at which the slope is equal to (-1). It can be
seen from fig 5.8 that when the input voltage is equal to V IH, the output voltage Vout is only
slightly larger than the output low voltage VOL . Hence, Vout < Vin – VTO, and the driver
transistor operates in the linear region. The KCL equation for the output node is given
below.

( VDD – Vout )/ RL = (kn/2)[2 ( VDD- VTO ) Vout – Vout 2 ]

Differentiating both sides of above equation we get

(-1/ RL ) (dVout/dVin) = ( kn /2) [2(Vin – VTO ) (dVout/dVin) + 2Vout – 2Vout(dVout/dVin)]

Next, we can substitute dVout/dVin = -1 into above equation since the slope of the VTC is
equal to (-1) also at Vin = VIH.

(-1/ RL ) (-1) = kn [ (VIH – VTO) (-1) + 2Vout]

Solving above for VIH

VIH = VTO + 2Vout - (kn RL) -1

Thus, we obtain two algebraic equations for two unknowns V IH and Vout. To determine the
unknown variables, we substitute above equation in first equation of this topic to get

( VDD – Vout )/ RL = (kn/2)[2 (VTO + 2Vout - (kn RL) -1 - VTO ) Vout – Vout 2 ]

The positive solution of this second-order equation gives the output voltage Vout when the
input is equal to VIH.
Vout(Vin = VIH ) = √(2 VDD / 3 kn RL )

Finally, VIH can be found by putting above equation in equation of VIH

VIH = VTO + √(8 VDD / 3 kn RL ) - (kn RL) -1

In addition to these voltage points, which characterize the static input-output behavior, the
inverter threshold voltage Vth may also be calculated in a straightforward manner. Note that
the driver transistor operates in saturation mode at this point. Thus, the inverter threshold
voltage can be found simply by substituting Vin = Vout = Vth into

VDD – Vout / RL = ( kn /2) (Vin - VTO) 2

And by solving the resulting quadratic for Vth.

Power Consumption and Chip Area

The average DC power consumption of the resistive-load inverter circuit is found by

considering two cases, Vin = VOL (low) and Vin = VOH (high). When the input voltage is equal
to VOL , the driver transistor is in cut-off. Consequently, if the leakage current is neglected,
there is no steady-state current flow in the circuit (I D = IR = 0), and the DC power dissipation
is equal to zero. When the input voltage is equal to V OH , on the other hand, both the driver
MOSFET and the load resistor conduct a nonzero current. Since the output voltage in this
case is equal to VOL , the current drawn from the power supply can be found as

ID = IR = ( VDD – Vout )/ RL

Assuming that the input voltage is “low” during 50% of the operation time, and “high”
during the remaining 50%, the average DC power consumption of the inverter can be
estimated as follows:

PDC (average) = ( VDD /2) ( VDD – Vout )/ RL

= ( VDD /2) ( VDD – VOL )/ RL

Design problem

Consider the following inverter design problem: V DD = 5V, kn’ = 30µA/ V2 , and VTO = 1V,
design a resistive load-inverter circuit with V OL =0.2V. Specifically, determine the (W/L) ratio
of the driver transistor and the value of the load resistor RL that achieve the required VOL.

Note that the driver transistor is operating in the linear region when the output voltage is
equal to VOL and the input voltage is equal to VOH = VDD

( VDD – VOL )/ RL = (kn’/2)(W/L)[2 ( VOH- VTO ) VOL – VOL 2 ]

Assuming VOL = 0.2V and using given values

( 5 – 0.2 )/ RL = (30*10 -6 /2)(W/L)[2 ( 4 ) 0.2 – 0.2 2 ]

This equation can be written as

(W/L) RL = 2.05 * 105 Ω

At this point, we recognize that the designer has a choice of different (W/L) and R L values, all
of which satisfy the given specification, V OL = 0.2V. The selection of the pair of values to use
for (W/L) and RL in the final design ultimately depends on other considerations, such as the
power consumption of the circuit and the silicon area. The next table lists some of the
design possibilities, along with the average DC power consumption for each design.

(W/L) ratio Load resistor RL (k Ω) DC power consumption

PDC,average [µW]

1 205.0 58.5

2 102.5 117.1

3 68.4 175.4

4 51.3 233.9

5 41.0 292.7

6 34.2 350.8
It is seen that the power consumption increases significantly as the value of the load resistor
RL is decreased, and the (W/L) ratio is increased. If lowering the DC power consumption is
the overriding concern, we may choose a small (W/L) ratio and a large load resistor. On the
other hand, if the fabrication of the large load resistor requires a large silicon area, a clear
trade-off exists between the DC power dissipation and the area occupied by the inverter
circuit.

Application: - SRAM

Advantages :- Simple Fabrication

Disadvantages: -

1) Large size.
2) More DC power consumption.
3) Not full voltage swing.
4) VTC characteristics not ideal.
 CMOS INVERTER

A Complementary MOS (CMOS) configuration consists of an enhancement type NMOS & an

enhancement type PMOS operating in complementary mode. (Fig.A)

Fig. A

The circuit topology is complementary push-pull in the sense that for high input, the NMOS
drives(pulls down) the output node while the PMOS acts as the load & for low input, the
PMOS drives(pulls up) the output node while the NMOS acts as the load. Both the devices
contribute equally to the circuit operation characteristics.

Circuit Operation:-

As shown in fig. A, input voltage is connected to the gate terminals of both the NMOS &
PMOS. The substrate of NMOS is connected to ground while that of PMOS is connected V DD,
in order to reverses bias the source & drain junctions. As V SB=0, there won’t be any substrate
bias effect for either device. Also,

VGS,n = Vin

→ (1)
VDS,n = Vout

&

VGS,p = –(VDD – Vin)

→ (2)

VDS,p = –(VDD – Vout)

When Vin< VT0,n, the NMOS is in cut-off. At the same time, the PMOS is on, operating in the
linear region.

ID,n = ID,p = 0 → (3) (except for small leakage currents).

Also VDS,p = 0

&

Vout = VOH = VDD → (4)

On the other hand, when Vin> (VDD + VT0,p), the PMOS is in cut-off & the NMOS is operating in
the linear region.

But, VDS,n = 0 as eq.(3) is satisfied.

Hence, Vout = VOL = 0 → (5)

i.e.,

VOH = VDD
VOL = 0

NMOS operates in saturation if

Vin > VT0,n & VDS,n ≥ VGS,n – VT0,n

i.e., Vout ≥ Vin – VT0,n → (6)

The PMOS operates in saturation if

Vin < (VDD + VT0,p) & VDS,p ≤ VGS,p – VT0,p

i.e., Vout ≤ Vin – VT0,p → (7)

 Fig. B

In region A, Vin < VT0,n, the NMOS is in cut-off & VOH = VDD. As the input voltage is increased
beyond VT0,n(into region B), the NMOS starts conducting in saturation mode & the output
voltage begins to decrease. VIL is also located in this region. As the output voltage further
decreases, the PMOS enters saturation at the boundary of region C. V th is located in this
region. When Vout falls below Vin – VT0,n, the NMOS starts to operate in linear mode. This is
region D in which VIH is located. In region E, with V in >(VDD + VT0,p), the PMOS is cut-off & V OL =
0.

Calculation of VIL:-

By definition, the slope of the VTC is equal to -1 i.e. dVout/dVin= -1 when Vin=VIL.

The NMOS is operating in the saturation and PMOS in the linear region.
I/P↓, O/P↑

NMOS:

VGS=Vin > VT0,n

NMOS ON

VDS=Vout > VGS – VT0,n

NMOS in Saturation

PMOS:

VGS=Vin – VDD < VT0,p

PMOS ON

VDS=Vout – VDD > VGS – VT0,p

PMOS in Linear
 ID,n(sat) = ID,p(lin)

kn.(VGS,n – VT0,n)2/2 = kp[2.(VGS,p – VT0,p).VDS,p – V2DS,p]/2 → (8)

Substituting equations (1) & (2),

Kn.(Vin – VT0,n)2/2 = kp.[2.(Vin – VDD – VT0,p).(Vout – VDD) – (Vout – VDD)2]/2 → (9)

Differentiating w.r.t. Vin,

kn.(Vin – VT0,n) = kp.[(Vin – VDD – VT0,p).(dVout/ dVin) + (Vout – VDD) – (Vout – VDD).(dVout/ dVin)] → (10)

Substituting Vin= VIL & (dVout/ dVin) = -1,

kn.(VIL – VT0,n) = kp.(2Vout – VIL + VT0,p – VDD) → (11)

Hence,

VIL = (2Vout + VT0,p – VDD + kRVT0,n)/(1 + kR) → (12)

where kR= kn/kp

This equation when solved with eq. (9) gives the numerical value of V IL & the corresponding
output voltage, Vout.

Calculation of VIH:-

When the input voltage is V IH, the NMOS is operating in the linear & PMOS in the saturation
region.

I/P↑, O/P↓ PMOS:

NMOS: VGS↑ = Vin↑ – VDD

VGS=Vin > VT0,n VGS<VT0,p

NMOS ON PMOS ON

VDS=Vout < VGS – VT0,n VDS=Vout – VDD < VGS – VT0,p

NMOS in Linear PMOS in Saturation

ID,n(lin) = ID,p(sat)
kn. [2.(VGS,n – VT0,n). VDS,n – V2DS,n]/2 = kp.(VGS,p – VT0,p)2/2 → (13)

Substituting equations (1) & (2),

kn. [2.(Vin – VT0,n). Vout – V2out]/2 = kp. (Vin – VDD – VT0,p)2/2 → (14)

Differentiating w.r.t. Vin,

kn.[(Vin – VT0,n).(dVout/dVin) + Vout – Vout.(dVout/dVin)] = kp.(Vin – VDD – VT0,p) → (15)

Substituting Vin= VIH & (dVout/dVin) = -1,

kn.( –VIH + VT0,n + 2Vout) = kp.(VIH – VDD – VT0,p) → (16)

Hence,

VIH = [VDD + VT0,p + kR.(2Vout + VT0,n)]/[1 + kR] → (17)

This equation when solved with eq. (14) gives the numerical values of V IH & Vout.

Calculation of Vth:-The inverter threshold voltage is defined as Vth=Vin=Vout. Both the NMOS
& PMOS are operating in the saturation region.

I/P = O/P

NMOS:

VGS=Vin > VT0,n

NMOS ON

VDS=Vout > VGS – VT0,n

NMOS in Saturation

PMOS:

VGS=Vin – VDD < VT0,p

PMOS ON

VDS=Vout – VDD < VGS – VT0,p

PMOS in Saturation

ID,n(sat) = ID,p(sat)

kn.(VGS,n – VT0,n)2/2 = kp.(VGS,p – VT0,p)2/2 → (18)

Substituting equations (1) & (2),

kn.(Vin – VT0,n)2/2 = kp.(Vin – VDD VT0,p)2/2 → (19)

The correct solution for this eq. is

Vin.(1 + √(kp/kn) = VT0,n + √(kp/kn).(VDD + VT0,p) → (20)

Hence, the inverter threshold(switching threshold) voltage Vth is found as

Vth = [VT0,n + √(1/kR). (VDD + VT0,p)]/ [1 + √(1/kR)] → (21)

If kR = 1, Vth = VDD/2.

DESIGN OF CMOS INVERTERS:

The inverter threshold voltage Vth is identified as one of the most important
parameters that characterize the steady-state input-output behaviour of the CMOS inverter
circuit.The CMOS inverter can by virtue of its complementary push-pull operating mode,
provide a full output voltage swing between 0 and V DD, and therefore, the noise margins are
relatively wide.Thus, the problem of designing a CMOS inverter

can be reduced to setting the inverter threshold to a desired voltage value.

Given the power supply voltage VDD, the nMOS and the pMOS transistor threshold
voltages,and the desired inverter threshold voltage V th, the corresponding ratio kR can be
found as follows.

Recognizing eqn (21) yields:

√(1/kR)=(Vth-VT0,n)/(VDD+VT0,n-Vth)…………………………..(22)

Now solve for kR that is required to achieve the given Vth.

kR=kn/kp=[(VDD+VT0,n-Vth)/(Vth-VT0,n)]2………………….(23)

The switching threshold voltage of an ideal inverter is defined as

Vth,ideal=1/2*VDD …………………………………………….(24)
Substituting eqn (24) in eqn(25) gives
2
(kn/kp)ideal=[(0.5VDD+VT0,p)/( 0.5VDD-VT0,n)] ……………(25)

for a near ideal CMOS VTC that satisfies the condition (24).Since the operations of the nMOS
and the pMOS transistors of the CMOS inverter are fully complementary, we can achieve
completely symmetric input output characteristics by setting the threshold

voltages as VT0= VT0,n=| VT0,p|. This reduces eqn(25) to:

(kn/kp)symmetric inverter=1……………………………………….(26)

Note that the ratio kr is defined as

(kn/kp)= µn*Cox*(W/L)n = µn*(W/L)n

µp*Cox*(W/L)p µp*(W/L)p………………………….(27)

assuming that the gate oxide thickness tox, and hence, the gate oxide capacitance

Cox have the same value for both nMOS and pMOS transistors. The unity-ratio condition eqn
(25) for the ideal symmetric inverter requires that

[(W/L)n] / [(W/L)p] = µp / µn ≈ [230cm2/V.s] / [580cm2/V.s]……..(28)

Hence,

(W/L)p ≈ 2.5(W/L)n ………………………………………………..(29)

It should that the numerical values used in eqn(28) for the electron and hole
mobilities are typical values and that exact µn and µp values will vary with surface doping
concentrations of the substrate and the tub.

Note that the inverter threshold voltage V th shifts to lower values with increasing k R
ratio.
 For a symmetric CMOS inverter with V T0,n=| VT0,p| and kR=1, the critical voltage V IL can
be found using equation (12) , as follows:

VIL=1/8*( 3VDD+2 VT0,n)…………………………………………(30)

Also the critical voltage VIH is found as :

VIH=1/8*( 5VDD-2 VT0,n)………………………………………….(31)

Note that the sum of VIL and VIH is always equal to VDD ina symmetric inverter.

VIL+VIH = VDD……………………………………………………(32)

The noise margins NML and NMH for this symmetric CMOS inverter are now calculated
using ;

NML =VIL-VOL = VIL

NMH =VOH-VIH = VDD-VIH………………………………………(33)

Which are equal to each other, and also equal to VIL.

NML=NMH=VIL……………………………………………………..(34)

The noise margin of CMOS inverter is very high as compared to enhancement and depletion
circuits.

PROBLEM:

Consider a CMOS inverter circuit with the following parameters:

Vdd=3.3V

Vto,n=0.6V

Vto,p=-0.7V

kn=200uA/V2

kp= 80µA/V2
Calculate the noise margins of the circuit, Notice that the CMOS inverter being considered
here has kR = 2.5 and the output high voltage V OH are found, using eqn(4) and eqn(5), as V OL
=0 and VOH = 3.3V. To calculate VIL in terms of the output voltage, we use eqn(12).

VIL = (2Vout + VTO,p – VDD + kRVTO,n)/ (1 + k R)

= (2Vout – 0.7 - 3.3 + 1.5)/ (1 + 2.5) = 0.57Vout – 0.71

Now substitute this expression into the KCL equation (9).

2.5(0.57Vout – 0.71 – 0.6)2 = 2(0.57Vout – 0.71 3.3 + 0.7) (Vout – 3.3) – (Vout – 3.3) 2

This expression yields a second-order polynomial in V out, as follows:

0.66Vout2 + 0.05 Vout – 6.65 = 0

Only one root of this quadratic equation corresponds to a physically correct solution for V out
(i.e., Vout > 0).

Vout = 3.14V

From this value, we can calculate the critical voltage VIL as:

VIL = 0.57. 3.14 – 0.71 = 1.08V

To calculate VIH in terms of the output voltage, use eqn(17):

VIH = (VDD + VTO,p + kR . (2Vout + VTO,n )/ (1 + kR )

 = [3.3 – 0.7 + 2.5(2 Vout + 0.6)]/ (1 + 2.5) = 1.43 Vout + 1.17

Next, substitute this expression into the KCL equation (14) to obtain a second-order
polynomial in Vout

2.5[2(1.43 Vout + 1.17 – 0.6) Vout - Vout Vout -1.43)2

2.61 Vout2 + 6.94 Vout – 2.04 = 0

Again, only one root of this quadratic equation corresponds to the physically correct
solution for Vout at this operating point, i.e., when Vin = VIH

Vout = 0.27V

From this value, we can calculate the critical voltage VIH as:

VIH = 1.43. 0.37 + 1.17 = 1.55V

Finally, we find the noise margins for low voltage levels and for high voltage levels.

NML = VIL – VOL = 1.08V

NMH = VOH – VIH = 1.75V

POWER AND AREA CONSIDERATIONS:

Since the CMOS inverter doesn’t draw any significant current from the power source in both
of its steady-state operating points (V out =VOH and Vout=VOL), the DC power dissipation of this
circuit is almost negligible.The drain current that flows through the nMOS and the pMOS
transistors in both cases is essentially limited to the reverse leakage current of the source
and drain pn-junctions, and in short channel MOSFET’s, the relatively small subthreshold
current. This unique property of the CMOS inverter is one of the most important advantages
of this configuration. In many applications requiring a low overall power consumption,
CMOS is preferred over other circuit alternatives for this reason. It must be noted, however,
that the CMOS inverter does not conduct a significant amount of current during a switching
event , ie.,when the output voltage changes from a low to high state, or from a high to low
state, or from a high to low state.

Advantages of CMOS:-

1. The steady-state power dissipation is virtually negligible, except for small power
dissipation due to leakage currents.

2. Voltage Transfer Characteristic (VTC) exhibits a full output swing between 0V & V DD &
the VTC transition is usually very sharp. The VTC of CMOS resembles that of an ideal
inverter.

Disadvantages of CMOS:-

1. NMOS & PMOS have to be fabricated on the same chip side-by-side. Hence, the
CMOS process is more complex. An n-well on p-type wafer or a p-well on n-type
wafer has to be built.

2. The close proximity of NMOS & PMOS may lead to formation of two parasitic bipolar
transistors causing ‘latch-up’ condition. Additional ‘guard-rings’ must be built around
the NMOS & PMOS to prevent this.

APPLICATIONS:

1. It acts a switching device.

2. It is used in complementary push-pull circuits.
 STICK DIAGRAMS
Stick diagram is a schematic representation of circuit at
physical design level.A VLSI circuit may be viewed as a 3-D
set of patterned material layers.Sick diagram provides top
view of circuit.
Stick diagrams are useful for planning the layout and routing
of the integrated circuits.In stick diagrams every line of a
conducting material layer is represented by a line of a distinct
colour.
Polysilicon gate
n+ diffusion
Metal 1
Metal 2
or p+ diffusion
n -well & p-well boundaries

or Metal contact

Enhancement NMOS

Enhancement PMOS

Depletion NMOS

Depletion PMOS
 3 Types Of Contacts

Poly Metal Contact

Metal Active Contact

Poly Active Contact

• The width of the line is not important as stick diagrams give only wiring and
routing information ,
• VLSI Circuits may be viewed as a 3-D set of patterned material layers..The
colours allow us to trace signal flow paths through the conducting layers in a
complex integrated circuit.
• A stick diagram is a schematic representation of a circuit of physical design level.
• In the early days of MOS integrated circiuts ,it was noticed that when chip was
illuminated with a white light source,each conducting layer had a distinct colouring
associated with it.When viewed under a microscope,which gave them a distinct
colouring.
• Used to develop the design layout.
• Stick diagram defines transistor type and active area A=WL.
• Metal layers can cross other layers without forming a contact
• Layers are isolated by Silicon Dioxide, a transparent layer hence not shown in
Stick diagram
• Only parallel & perpendicular lines are involved.
• Order of lines is important. First active later then polysilicon(order of fabrication)
EULER PATH
•Before the cell can be constructed from a transistor schematic it is necessary to
develop a strategy for the cell’s basic layout.Stick Diagrams are a means for the
design engineer to visualize the cell routing and transistor placement.
•METHOD:Stick diagrams are constructed in two steps.
1) The first step is to construct a logic graph of the schematic
a) Identify each transistor by a unigue name of its gate signal(A,B,C,D …….)
b) Identify each connection to the transistor by a unique name(1,2,3,4……)
2) The second step is to construct one Euler path for both the pull up and pull
down network.
a) Euler paths are defined by a path that traverses each node in the path,such
that each edge is visited only once.
b) The path is defined by the order of each transistor name.For eg) if the path
traverses transistor A then B then C,the the path name is {A,B,C}
c) The Euler path of the Pull up network must be the same as the Pull down
network
d) Euler paths are not necessarily unique.
e) It may be necessary to redefine the function to find a Euler path.
CMOS INVERTER ( VOUT=VIN)

TRUTH TABLE •NMOS pull down transistor

VIN VOUT •PMOS pull up transistor
•VIN=0 PMOS ON & NMOS OFF
0 1
•VIN=1 NMOS ON & PMOS OFF
1 0
•If PMOS ON : VOUT=1
•If NMOS ON : VOUT=0
VDD
Thus, VIN
VDD

V OUT

VIN V OUT

GND
GND

NMOS INVERTER
 DEPLETION NMOS INVERTER

CMOS NAND
VOUT = AB 2 NMOS in series (pull down) & 2 PMOS in parallel (pull up)

TRUTH TABLE
A B VOUT
…….(1)
0 0 1
….....(2)
0 1 1
1 0 1 …….(3)

1 1 0 …….(4)

• PMOS pull up transistor

• NMOS pull down transistor
• (1):Both PMOS are ON & NMOS OFF
• (2):One PMOS & one NMOS is ON
• (3):One PMOS & one NMOS is ON
• From (1),(2),(3): When either one or both PMOS are ON,VOUT=1
PMOS in parallel.
• When both the i/ps are 1 PMOS are OFF & NMOS are ON.From (4)
only when both NMOS are ON the o/p is pulled to 0 NMOS in series.
 CMOS NAND (VOUT = AB)
VDD
VDD
A B

B
A

V OUT
V OUT

B
GND

GND

NMOS NAND
 DEPLETION NMOS NAND

CMOS NOR (VOUT = A + B )

(VOUT = A + B ) 2 NMOS in parallel (pull down) & 2 PMOS in series (pull up)
TRUTH TABLE
A B VOUT
…….(1)
0 0 1
….....(2)
0 1 0
1 0 0 …….(3)

1 1 0 …….(4)
• PMOS pull up transistor
• NMOS pull down transistor
• (2): One PMOS & one NMOS is ON
• (3): One PMOS & one NMOS is ON
• (4): Both NMOS are ON & both PMOS are OFF
• From (2),(3),(4): When either one or both PMOS are ON,VOUT=1
NMOS in parallel.
• When both the i/ps are 0 NMOS are OFF & PMOS are ON.From (4)
only when both PMOS are ON the o/p is pulled to 0 PMOS in series.
 CMOS NOR
VDD

VDD
A B

V OUT
B
V OUT

A B

GND

GND

NMOS NOR
 DEPLETION NMOS NOR

(VOUT=A B)

CMOS EXOR/ HALF ADDER

TRUTH TABLE
A B VOUT
…….(1)
0 0 0
….....(2)
0 1 1
1 0 1 …….(3)

1 1 0 …….(4)
• PMOS pull up transistor
• NMOS pull down transistor

(VOUT=A B) = A B + A B
=AB+AB
= (A B) (A B)
= (A + B) (A + B)
CMOS EXOR/ HALF ADDER
VDD
VDD
A A B B
A A

B B
V OUT

V OUT

A B

A B

GND
GND

CMOS EXNOR (VOUT=A B)

TRUTH TABLE
A B VOUT
…….(1)
0 0 0
0 1 0 ….....(2)

1 0 0 …….(3)
1 1 0 …….(4)

VOUT = (A B + A B)
=(A B) (AB)
= (A + B) (A + B)
CMOS EXNOR
VDD
VDD
A A B B
A A

B B
V OUT

V OUT

A B

A B

GND
GND

A(B+C)+DE = A(B+C)+DE
= A(B+C) (DE)
VDD = {A+( B + C)} (D+E)
= {A+(B C)}(D+E)
D A

E
B C

V OUT

D E

B
A C

GND
 VDD

E D A C B

V OUT

GND

A(B+C)+DE VDD

VDD
A D E C B

B
A C

V OUT
D E
V OUT

D A

E
B C

GND
GND
FULL ADDER

TRUTH TABLE
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SUM = A B Cin
= A B Cin+ A B Cin + A B Cin + A B Cin
Cout = AB+BCin+ACin
Thus, SUM = (A+B+Cin) Cout +ABCin
= A B Cin + Cout(A + B + Cin)

FULL ADDER
VDD

A B C

A
Cin
B

C
SUM

A B C
A
B
Cin
C

GND
 VDD

A A VDD

A B
B B
B

C C C A
SUM Cout
C C C
C A

B B B B
A

GND

A A

GND

STICK DIAGRAM OF FULL ADDER VDD

A B Cin Cout A B Cin

SUM

GND
 2:1 MUX

A0
TRUTH TABLE
2:1 Vout S0 Vout
A1 MUX
0 A0
1 A1

S0 Vout = S0(A0) + S0(A1)

S0 S1=S0

S0 S1=S0

A0 A0

Vout
Vout

A1
A1
 INTERLAYER CONTACTS
Layers of metal, polysilicon, and diffused material are normally isolated by silicon dioxide.
Various masks are required to define areas where the oxide is to be etched to produce the
desired effect. Metal is normally connected to either polysilicon or diffusion by a contact
cut. The minimum sized contact cut is 2λ by 2 λ. A metal overlap of λ around all four sides
of the oxide cut will ensure a good low resistance contact. Cuts and vias are used to make
contact between two metal layers and are typically 2 λ by 2 λ.

Butting Contact

The butting contact is a simple contact to make connection between diffusion to polysilicon.
Here metal makes contact to both the diffusion forming the source and to the polySi.

Metallization is required only over the butting contact holes which are 2 λ * 4 λ in size. A
border of width λ around all four sides is added to allow for misregistration, and ensure
proper contacts thus bringing metallization size to 4 λ * 6 λ.

4λ
2λ

4λ

Advantage:

No extra masking step required but requires a metal cap

Buried Contact

It is a preferred method. The buried contact window defines the area where oxide is to be
removed so that polySi connects directly to diffusion.

4λ

4λ

The buried contact window as in the following figure surrounds this contact by λ in all
directions to avoid any part of this area forming a transistor.

Separated from its related transistor gate by λ to prevent gate area from being reduced.

l
Advantages:

No metal cap required, hence no additional making steps.

Metal can cross over buried contact, hence easier routing of conductors.

Disadvantages:

Additional mask is required.

Self-registration may be lost.

1. Buried contact with self-registration

5λ

4λ

2. Buried contact without self-registration

2λ 2λ

4λ

5λ
 LAYOUT DESIGNING AND DESIGNING RULES

Layout design rules are set of geometric constrains that a layout of any circuit to be
manufacture must conform. It specifies minimum line widths for metal and poly connections
or diffusion area and spacing.

Design rules are to be followed to ensure:

1. Better area efficiency

2. Better yield, better reliability and also helps in estimating the exact

values of parasitic capacitance

3. Increase the probability of fabricating a successful product on Si wafer

If the design rules are not followed it may lead to

1. Open or short circuit inside IC

2. Functional or non-functional circuit

3. Degradation of device performance

Two ways of describing design rules are:

1. Micron rule – It includes constraints like minimum feature sizes and

allowable feature seperations.

2. Lambda rule – It specifies constraints in terms of single parameter (λ)

and thus allows linear, proportional scaling of all geometrical

constraints.
Rule Description NMOS PMOS Diagram
Number Technology Technology

Minimum active 2λ 3λ
3λ 3λ
R1 line width

Minimum active 2λ 3λ
3λ
R2 line spacing

Minimum poly line 2λ 2λ 2λ

R3 width

Minimum poly line 2λ 2λ

2λ
R4 spacing

Minimum poly 2λ 2λ
R5 extension outside
active 2λ

2λ
Minimum poly 2λ 2λ
R6 inside active

Minimum poly 1λ 1λ
R7 outside active
1λ
 Rule Description NMOS PMOS Diagram
Number Technology Technology

Metal 1 line 3λ 3λ 3λ
R8 width

Minimum 3λ 3λ 3λ
R9 metal1 line
spacing

Minimum 2λ 2λ
R10 contact size
2λ
inside poly

Minimum 2λ 2λ
R11 contact spacing 2λ
inside poly

Minimum 1λ 1λ
R12 contact spacing
from poly edge
1λ

Minimum 1λ 1λ
R13 contact spacing
from metal edge
1λ

Minimum 2λ 3λ
R14 contact spacing 3λ
from active
edge; inside poly
 Rule Description NMOS PMOS Diagram
Number

Minimum 2λ 2λ
R15 contact size
inside active 2λ

Minimum 2λ 2λ
R16 contact spacing 2λ
inside active

Minimum 1λ 1λ
R17 contact spacing
active edge 1λ

Minimum 1λ 1λ
R18 contact spacing
from metal edge
1λ

Minimum 2λ 3λ
R19 contact spacing 3λ
from poly edge

Minimum
- 6λ 6λ
contact spacing
R20 of two different
actives

Minimum 3λ 3λ 3λ 4λ
R21 metal2 line and and
width and 4λ 4λ
spacing
 LATCHUP AND ITS PREVENTION
Latchup:

The tendency of CMOS chips to develop low resistance paths between V DD and GND causing
catastrophic melting is called latchup. This occurs when parasitic bipolar transistors formed
by the substrate, well and diffusion turn ON.

Fig (a)

Fig (b)

The cause of latch up can be understood by examining the cross section of a CMOS inverter,
shown in fig. over which is overlaid an equivalent circuit. In addition to the expected nMOS
and pMOS transistors, the schematics depicts a circuit composed of an npn-transistor , a
pnp-transistor, and two resistors connected between the power and ground rails. The npn-
transistor is formed between the grounded n-diffusion source of the nMOS transistor, the p-
type substrate and the n-well. The resistors are due to the resistance through the substrate
or well to the nearest substrate and well taps. The cross-coupled transistors form a bistable
silicon controlled rectifier (SCR). Ordinarily, both the parasitic bipolar transistors are OFF.
Latch up can be triggered when transient currents flow through the substrate during normal
chip power-up or when external voltages outside the normal operating range are applied. If
substantial current flows in the substrate, V sub will rise, turning ON the npn-transistor. This
pulls current through the well resistor, bringing down V well and turning ON the pnp-tansistor.
The pnp-transistor current in turn raises V sub, initiating a positive feedback loop with a large
current flowing between VDD and GND that persists until the power supply is turned off or
the power wires melt.

Prevention:

Latchup prevention is easily accomplished by minimising R sub and Rwell which can be done as
follows:

1. Use a thin epitaxial layer of lightly doped silicon on top of heavily doped substrate
that offers a low resistance.
2. Reduce the gains of the BJTs by lowering the minority carrier lifetime through gold
doping of the substrate (but without causing excessive leakage currents) or reducing
the minority carrier injection efficiency of BJT emitters by using Schottky
source/drain contacts.
3. Use p+ guardband rings connected to ground around nMOS transistors and n+ guard
rings connected to VDD around pMOS transistors to reduce Rwell and Rsub and to
capture injected minority carriers before they reach the base of the parasitic BJTs.
4. Use minimum area p-wells(in case of twin-tub technology or n-type substrate) so
that the p-well photocurrent can be minimised during transient pulses.
5. Every well should have atleast one tap.
6. All substrate and wire taps should connect directly to the appropriate supply in
metal.
7. nMOS transistors should be clustered together near GND and pMOS transistors
should be clustered together near V DD, avoiding convoluted structures that
intertwine nMOS and pMOS transistors in checkboard patterns.
 MOS CAPACITANCES

To examine the transient (AC) response of MOSFETs and their digital circuits, we have to
determine the nature and the parasitic capacitances associated with the MOS transistor.
The on-chip capacitances found in MOS circuits are functions of the layout geometries and
the manufacturing processes. Most of these capacitances are not lumped but distributed.
Based on their physical origins, the parasitic device capacitances are classified as oxide
capacitances and junction capacitances.
Oxide-related capacitances:

The gate electrode overlaps both the source and the drain regions at the edges. The two
overlap capacitances that arise as a result of this structural arrangement are called Cgd and
Cgs, respectively. Assuming that both the source and drain regions have the same width W,
the overlap capacitances can be found as

CGS (overlap)=COX.W.LD

CGD (overlap)=COX.W.LD

With

Cox =Є OX/tox

LD>>Gate Drain overlap length

These overlap capacitances are voltage independent.

Now consider the capacitances which result from interaction between the gate voltage and
the channel charge. Since the channel region is connected to the source, the drain, and the
substrate, we can identify three capacitances between the gate and these regions, i.e. C GS,
CGD, and CGB, respectively.

CUT OFF MODE:

In cut-off mode, the surface is not inverted. Consequently, there is no conducting channel
that links the surface to the source and to the drain. Therefore, the gate-to-source and the
gate-to-drain capacitances are both equal to zero: C GS=CGD=0. The gate-to-substrate
capacitance can be approximated by:
CGB=COX.W.L
LINEAR MODE:

In linear mode operation, the inverted channel extends across the MOSFET, between the
source and the drain. This conducting inversion layer on the surface effectively shields the
substrate from the gate electric field; thus, CGB=0. In this case, the distributed gate-to-
channel capacitance may also be viewed as being shared equally between the source and
the drain, yielding

CGS ~ CGD~(1/2).COX.W.L

SATURATION MODE:

When the MOSFET is operating in saturation mode, the inversion layer on the surface does
not extend to the drain, but it is pinched off. The gate-to-source drain capacitance is
therefore equal to zero (Cgd=0). Since the source is still inked to the conducting channel, its
shielding effect also forces the gate-to-substrate capacitance to be zero, C GD=0. Finally, the
distributed gate-to-channel capacitance as seen between the gate and the source can be
approximated by

CGS ~ (2/3).Cox.W.L

The following table summarizes the oxide capacitance values for three operating modes of
the MOS transistor

Capacitance Cut-off Linear Saturation

CGB(total) CoxWLD 0 0
CGD(total) CoxWLD (1/2)CoxWLD+CoxWLD CoxWLD
CGS(total) COXWLD (1/2)CoxWLD+CoxWLD 2/3COXWL+COXWLD
We have to combine the distributed CGS and CGD values found here with the relevant overlap
capacitances, in order to calculate the total capacitance between the external device
terminals. It is also worth noticing hat the sum of all the voltage-dependent (distributed)
gate oxide capacitances (CGS + CGD+CDS) has a minimum value of 0.66Cox.W.L (in saturation
mode) and a maximum value of Cox.W.L (in cut-off and linear modes). For simple hand
calculations where all three capacitances can be considered to be connected in parallel, a
constant worst case value of Cox.W.(L+2L D) can be used for the sum of MOSFET gate oxide
capacitances.
Junction capacitances:

Consider the voltage-dependent source-substrate and drain-substrate junction

capacitances, CSB and CDB, respectively. Both of these capacitances are due to the
depletion charge surrounding the respective source or drain diffusion regions embedded to
the substrate. The calculation of the associated junction capacitances is complicated by the
here-dimensional shape of the regions that form the source-substrate and the drain-
substrate junctions. Note that both of these junctions are reverse biased under normal
operating conditions of the MOSFET and that the amount of junction capacitance is a
function of the applied terminal voltages. Fig shows the simplified partial geometry of a
typical-channel enhancement MOSFET, focusing on the n-type diffusion region within the p-
type substrate. The analysis to be carried out in the following will apply to both n-channel
and p-channel MOS transistors.
 The dimensions of the rectangular box representing the diffusion region are given
as W, Y, and xj.

 As seen in fig, the n+ diffusion region forms a number of planar pn-junctions with
the surrounding p-type substrate, indicated here with 1through 5.

 Also, comparing this three-dimensional view with fig, we recognize that three of the
five planar junctions shown here (2,3 and 4) are actually surrounded by the p+
channel-stop implant.

 The junction labeled (1) is facing the channel, and the bottom junction (5) is facing
the p-type substrate, which has a doping density of N A .Since the p+ channel-stop
implant density is usually about 10N A, the junction capacitances associated with
these sidewalls will be different from the other junction capacitances.

 To calculate the depletion capacitance of a reverse-biased abrupt pn-junction,

consider first the depletion region thickness, x d . Assuming that the n-type and p-
type doping densities are given by ND and NA, respectively, and that the reverse bias
voltage is given by V (negative), the depletion region thickness can be found as
follows:
xd = √[(2.Єsi/q)(NA+ND/(NA.ND)).(Φ0-V)]

where the built-in junction potential is calculated as

Φ0 = (kT/q).ln(NA.ND /ni2)

Note that the junction is forward biased with a positive bias voltage. The depletion-region
charge can be stored in this area can be written I terms of the depletion region thickness, x d.

Qj=A.q.{NA.ND/( NA+ND)}.xd

=A√[2.Єsi.q. {NA.ND/( NA+ND)}. (Φ0-V)] ……………………..(1)

Here, A indicates the junction area. The junction capacitance associated with the depletion
region is defined as

Cj=│dQj/dV│ ……………………………(2)

By differentiating equation for Qj with respect to the bias voltage V, we can obtain the
expression for the junction capacitance as follows:

Cj(V)=A. √[(1/2).Єsi.q. {NA.ND/ ( NA+ND)}] . 1/ √(Φ0-V) ………………………..(3)

This expression can be rewritten in a more general form, to account for the junction grading.

Cj(V)=A.Cj0/(1-V/ Φ0)m …………………………(4)

The parameter m in above eqution is called the grading co-efficient. Its value is equal to ½
for an abrupt junction profile, and 1/3 for a linearly graded junction profile. Obviously, for
an abrupt pn-junction profile, i.e., for m=1/2, (3) and (4) become identical. The zero-bias
junction capacitance per unit area Cj0 is defined as

Cj0 = √[(1/2).Єsi.q. {NA.ND/ ( NA+ND)}.{1/Φ0}] ………………………(5)

Note that the value of the junction capacitance Cj given by (4) ultimately depends on the
external bias voltage that can be applied across the pn-junction. Since the terminal voltages
of a MOSFET will change during the dynamic operation, accurate estimation of the junction
capacitances under transient conditions is quite complicated; the instantaneous values of all
junction capacitances will also change accordingly. The problem of estimating capacitance
value under changing bias conditions can be simplified, if we calculate a large-signal aveage
(linear) junction capacitance instead, which, by definition, is independent of the bias
potential. The equivalent large-signal capacitance can be defined as follows:

Ceq=∆Q/∆V = {Qj(V2)-Qj(V1)}/{V2∫∫-V1} = {1/(V2-V1)}.∫ Cj(V) dV

Here, the reverse bias voltage across the pn-junction is assumed to change from V1 to V2.
Hence, the equivalent capacitance Ceq is always ccalculated for a transition between two
known voltage levels. By substituting (4) in (6), we obtain

Ceq= -{2.A. Cj0. Φ0/(V2-V1)(1-m)} . [√(1-V2/ Φ0 )1-m - (1-V1/ Φ0 )1-m] ………………..(7)

For the special case of abrupt pn-junction, equation (7) becomes

Ceq= -{2.A. Cj0. Φ0/(V2-V1). [√(1-V2/ Φ0 ) - (1-V1/ Φ0 )]} ………………..(8)

This equation can be rewritten in a simpler form by defining a dimensionless co-efficient

Keq, as follows:

Ceq=A.Cj0.Keq ………………………………..(9)

Keq = -2√ Φ0 /(V2-V1).( √ Φ0-V2 - √ Φ0-V1 ……………………(10)

Where Ke is the voltage equivalence factor ( note that 0<Keq<1). Thus the co-efficient Keq
allows us to take into account the voltage-dependent variations of the junction capacitance.
The accuracy of the lare-signal equivalent junction capacitance Ceq found by using (9) and
(10) is usually sufficient for most first-order hand calculations.
 ENERGY-BAND DIAGRAM
INTRODUCTION TO PN-JUNCTION PHYSICS

A conducting material is made up of atoms that have easily shared orbiting electrons. As a
simple example, copper is a better conductor than aluminum because the copper atoms’
electrons aren’t as tightly coupled to its nucleus allowing its electrons to move around the
atom’s nucleus.

A significant electric field id required to break these electrons away from their nucleus (and
thus for current conduction).A semiconductor like silicon has four valence electrons.
Silicon’s conductivity falls between an insulator and conductor (and thus the name
“semiconductor”).as the silicon atoms are brought together, they form a periodic structure
and bands of energy that restrict the allowable energies an electron can occupy. At absolute
zero temperature,(T=0 K),all of the valence electrons in a semiconductor crystal reside in the
valence energy band, Ev. As temperature increases, the electrons gain energy (heat is
absorbed by the silicon crystal),which causes some of the valence electrons to break free
and move to a conducting energy level Ec.

Fig. shows the movement of an electron from the valence to the conduction band. Note that
there aren’t any allowable Between Ec and Ev in the silicon structure.(if the atoms were in a
structure. i.e: not by itself, this limitation isn’t present).

When the electron moves from the valence energy band to the conduction energy band, a
hole is left in the valence band. An electron in the valence band improves the material’s
conductivity (as it can move easily in the semiconductor material as it is not tightly coupled
to the atoms nucleus).At the same time, a hole in the valence band increases the materials
conductivity(electrons in the valence band can move around simply by falling into an open
hole).

Increasing the number of holes and electrons increase the conductivity.

Since the holes are more tightly coupled to the nucleus,its mobility is lower than the
electrons’ mobility in the conduction band(the reason why size of PMOS is greater than
NMOS).
CARRIER CONCENTRATION

Pure silicon is often called as intrinsic silicon.As the temperature of the silicon crystal is
increased,it absorbs heat.

Some electrons in the valence gain enough energy to overcome the bandgap energy of
silicon(Eg).

This movement from valence to conduction band is called generation.

When the electron loses energy and falls back into the valence band,its called
recombination.

The time an electron spends in the conduction band before it recombines is characterized
by the lifetime τT..This is an important parameter for circuit design.

The number of electrons in the conduction band at a given time at room temperature is
given by:

ni=14.5x109 carriers/cm3

these are known as intrinsic carriers.

If n is the number of free (electrons excited upto conduction band) electrons and p is the
number of holes for an intrinsic silicon then,

n=p=ni=14.5x109 carriers/cm3

The number of silicon atoms, Nsi in a given volume of crystalline silicon is:

Nsi=50 x 1021 atoms/cm3

So there is only one excited electron/hole pair for (roughly) every 10 12 silicon atoms.

Next let’s add different materials to intrinsic silicon (called doping the silicon) to change
silicon’s electrical properties. If we add a small amount of a material containing atoms with
five valence electrons like phosphorus (silicon has 4), then the added atom will bond with
the silicon atoms and the donated electron would be free to move around (and easily
excited to the conduction band). IF we call the density of this added donor material N D with
units of atoms/cm3 and we assume the number of atoms added to the silicon is much larger
than the intrinsic carrier concentration, then we can write the number of free electrons (the
electron concentration n) in the material as

n= ND when NSi >> ni ……………..(2)

A material with added donor atoms is said to be an ‘n-type’ material. Similarly, if we were to
add a small material to silicon with atoms having three valence electrons (like boron), the
added material would bond with the silicon resulting in a hole in the valence band. Again,
this increases the conductivity of silicon because, now, the electrons in the valence band can
move into the hole (having the effect of making it look like the hole is moving). The added
material is said to be an acceptor material. The added material accepts an electron from the
silicon crystal. If the density of the added acceptor material is N, then the hole
concentration,p, in the material is

P=NA when NSi>>NA>>ni …………….(3)

A material with added acceptor atoms is said to be a ‘p-type’ material.

If we dope a material with donor atoms, the number of free electrons in the material, n,
goes up, as indicated by above equations. We would expect, then, the number of free holes
in the material to go down (some of these free electrons fall easily into the available holes
reducing the number of holes in the material). The relationship between the number of
holes, electrons, and intrinsic carrier concentration, is governed by the mass-action law,

pn=ni2

EXAMPLE

Suppose silicon is doped with phosphorus having a density N D of 1018 atoms/cm3. Estimate
the doped silicon’s hole and electron concentration.

The electron concentration from eq. (1) is n=1018 electons/cm3 (one electron for each donor
atom). The hole concentration is found using the mass-action law as

Basically, all of the holes are filled. Note that with a doping density of 10 18 there is one
dopant atom for every 50000 silicon atoms. If we continue to increase the doping
concentration, our assumption that NSi>>ND isn’t valid and the material is said to be
degenerate (no longer mainly silicon). A degenerate semiconductor does not follow the
mass-action law (or any of the equations for silicon)

FERMI ENERGY LEVEL

To describe the carrier concentration in a semiconductor, the Fermi energy level is often
used. The Fermi energy level is useful when determining the contact potentials in materials.
For example, the potential that you have to apply across a diode before it turns on is set by
the p-type and n-type material contact potential difference. Also, the Threshold voltage is
determined, in part, by contact potentials.

The Fermi energy level simply indicates the energy level where the probability of occupation
by a free electron is 50%. The fig. shows that for intrinsic silicon the (intrinsic) Fermi level E i
is close to the middle of the bandgap. In p-type silicon, the Fermi level E f moves towards the
valence band, since the number of free electrons, n, is reduced with the abundance of
holes. The Fermi level for an n-type silicon moves towards E c with the abundance of
electrons in the conduction band.

The energy difference between Ei and Ef is given, for a p-type semiconductor, by

And for an n-type semiconductor by

The band diagram of a pn junction is seen in the fig. (d). Note how the Fermi energy level is
constant throughout the diode. A variation in E f would indicate a non-equilibrium situation
(the diode has an external voltage applied across it). To get current flow in a diode, we must
apply an external potential that approaches the diode’s contact potential (its built-in
potential Vbi). By applying a potential to forward bias the diode, the conduction energy
levels in each side of the diode move closed to the same level. The voltage applied to the
diode when the conduction energy levels are exactly at the same level is given by

where kT/q=VT is the thermal voltage

 ACCUMULATION, DEPLETION AND INVERSION

Let us see the electrical behavior of the MOS under externally applied bias voltage. Assume
that the substrate voltage is set to zero and let the gate voltage be the controlling
parameter. Depending on the polarity and the magnitude of gate voltage, there are three
different operating regions namely-

 Accumulation
 Depletion
 Inversion

Accumulation

If a negative voltage Vg is applied to the gate electrode, the holes in the p-type substrate are
attracted to the semiconductor-oxide interface. The majority carrier concentration near the
surface becomes larger than the equilibrium hole concentration in the substrate; hence, this
condition is called carrier accumulation on the surface.

Note the oxide electric field is directed towards the gate electrode. The negative surface
potential also causes the energy bands to bend upwards near the surface. While the hole
density near the surface increases as a result of the applied negative gate bias, the electron
concentration decreases as the negatively charged electrons are pushed deeper into the
substrate.

Here the gate bias is negative so tits Fermi level will increase and the holes near the surface
are attracted so its Fermi level will decrease. Now, in this case energy band will bend
upwards (since we see the bend w.r.t. substrate)
Depletion

Now consider a case in which a small positive gate voltage is applied. Since the substrate is
at zero potential, the oxide electric field will be directed towards the substrate. The positive
surface potential causes the energy bands to bend downwards near the surface. The holes
in the substrate will be repelled back into the substrate due positive gate bias and these
holes will leave negatively charged fixed acceptor ions behind. Thus, a depletion region is
created as shown in fig. the region near the semiconductor-oxide interface is devoid of
mobile carrriers.

Let xd be the depth of depletion region and is given by-

|Ø S−Ø F|
√
X d= 2 ε Si ∙
q∙ N A

Depletion region charge density is given by

Q= −q ∙ N A ∙ X d = - √ 2 q ∙ NA ∙ ε Si ∙|Ø S−Ø F|

Here, gate is at positive bias so its Fermi level will decrease and the electrons will be
attracted at the surface so its Fermi level will increase. Thus, we observe the energy band
bending downward.

Inversion

Now if we increase the positive gate voltage, the downward bending of the energy will
increase and thus Ei becomes smaller than the Fermi level E Fp on the surface, which means
that the substrate semiconductor in this region becomes n-type. This n-type region created
near h surface by positive gate bias is called the inversion layer and this condition is called
surface inversion. Within this thin layer, the density of the electrons is larger than the hole
density since positive gate potential attracts minority carriers from the substrate.
As a practical definition, the surface is said to be inverted when the density of the mobile
electrons on the surface becomes equal to the density of holes in the substrate. This
condition requires that the surface potential has the same magnitude, but the reverse
polarity. Once the surface has inverted, any further increase in the gate voltage leads to an
increase of mobile electron concentration on the surface, but not to an increase of the
depletion depth. Thus, the depletion region depth achieved at the onset of surface inversion
is equal to the maximum depletion depth, x dm , which remains constant for higher gate
voltages. Using the inversion condition Øs = - ØF , the maximum depletion region depth at the
onset of the surface inversion is

|2 Ø F|
√
X dm = 2 ε Si∙
q∙ N A
 THRESHOLD VOLTAGE
Threshold voltage is a function of the total charge in the depletion region because the gate
charge must mirror depletion charge (Qd) before an inversion layer is formed.

Threshold voltage depends on four physical components :

1)the work function difference gate and channel(ØGC)

2)the gate voltage component to change the surface potential

3)the gate voltage component to offset the depletion charge

4)the voltage component to offset the fixed charges in the gate oxide and the silicon oxide
interface.

The work function difference ØGC between the gate and channel reflects the built in potential
of the MOS system. Depending on the gate material, the work function difference is

ØGC = ØF (substrate) –ØM for metal gate

This component accounts for the built in voltage drop across the MOS system.

Now, the externally applied voltage must be applied to achieve the surface inversion i.e., to
change the surface potential by -2ØF.This will be second component of threshold voltage.

Another component of the applied gate voltage is necessary to offset the applied depletion
region charge, which is due to the fixed acceptor ions in the depletion region near the
surface. We can calculate the depletion region charge density at surface inversion ()

We know that,

QB = (2qNAεSi| ØS- ØF|) 1/2

For surface inversion,

ØS = (-ØF)

QB0= (2qNAεSi| -2ØF|) 1/2

The component that offsets the depletion region charge is then equal to (-QB0 /COX).

COX=gate oxide capacitance per unit area.

Now we consider the influence of non-ideal physical phenomenon .There always exists a
fixed positive density QOX at the interface between the gate oxide and the silicon substrate,
due to impurities and lattice imperfections at the interface.
The gate voltage component that is necessary to offset this positive charge at the interface
is (-QOX/COX).

Combining all these voltage components, we get the threshold voltage(V T0) as follows:

VT0 = ØGC –2ØF – (QB0 /COX) – (QOX /COX).

Above equation gives the threshold voltage for zero substrate bias i.e., without body effect.

For finding threshold voltage with body effect, we need to consider the influence of V SB upon
the depletion region charge density.

Hence the generalized form of threshold voltage can be written as

VT = ØGC – 2ØF – (QB /COX) – (QOX /COX).

i.e., VT0 = ØGC – 2ØF – (QB0 /COX) – (QOX /COX) – [(QB– QB0)/COX]

i.e., VT = VT0 – [(QB– QB0)/COX]

[(QB– QB0)/COX]= (2qNAεSi) 1/2/COX {(|– 2ØF |+VSB) ½– (|– 2ØF |)1/2 }

VT =VT0+ γ {( |– 2ØF | + VSB ) 1/2 – ( |– 2ØF | ) 1/2 }

Where-

γ = (2qNAεSi) 1/2/COX

γ=substrate bias coefficient (positive for n-MOS , negative for p-MOS)

The threshold voltage can be used both for n-channel and p-channel MOS transistors. Some
of the terms in this equation have different polarities for n-MOS and p-MOS. The reason for
this polarity difference is that substrate semiconductor is p-type in an n-MOS and n-type in a
p-MOS.

Parameter ØGC ØF QB /COX QOX /COX

n-MOS -ve -ve -ve +ve

p-MOS +ve +ve +ve +ve

Typically ,threshold voltage of an enhancement type n-channel MOSFET is positive quantity

whereas threshold voltage of an enhancement type p-channel MOSFET is negative.
 BODY EFFECT
For our analysis substrate and source are connected to ground. What happens if the
substrate voltage is less than source voltage? To understand the effect, suppose source and
drain are at zero potential and gate voltage is less than V th so that a depletion region is
formed under the gate but no inversion layer exists. As V b becomes more negative more
holes are attracted to the substrate connection, leaving a larger negative charge behind as
shown in the figure thus the depletion region becomes wider. We know that the threshold
voltage depends on the charge present in the depletion region to form an inversion layer.
Thus, as Vb decreases and Qd increases and therefore Vth increases. This is known as body
effect.

Where, =body effect co-efficient.

Consider the circuit shown

First neglect the body effect, as Vin varies Vout closely follows the input because the drain
Current remains constant equal to I1. We can write,

Vin-Vout=VGS

We can conclude that Vin - Vout remains constant if I1remains constant refer fig. b)

Now, consider the body effect and here the substrate is tied to ground. Then, as V in
increases and thus Vout becomes more positive, the potential difference between the source
and body increases, thus increasing the V TH. Equation of I1 thus implies Vin - Vout must increase
so as to maintain ID constant.

Body effect is usually undesirable. The change in the threshold voltage e.g. as in fig. a, often
complicate the design of analog(or even digital) circuits. Device technologist balance Nsub
and Cox to obtain the reasonable value of .
 IC FABRICATION

 Based on fabrication process ICs are classified into:

1. Monolithic ICs:- entire device on one plate; all circuit components (active or
passive) and interconnections are manufactured into a single chip of silicon
Application:-where identical circuits are required in very large quantities

2. Hybrid ICs:-separate component parts are attached to a substrate and

interconnected by means of realization.
Application:-small scale custom circuits

 Based on application :-

1. Digital ICs :- less complex

2. Analog ICs :- parameters are variable and hence design is more complex

 Based on level of integration :-

1. SSI(Small Scale Integration):- 10 to 100 transistors per chip (Logic gates ,

Flipflops)
2. MSI(Medium Scale Integration):-100 to 1000 transistors per chip(counters ,
multiplexers, adders)
3. LSI (Large Scale Integration) = 1000/20000 transistors per chip
(8 bit microprocessor)

4. VLSI (very large scale integration) = 10000 or more

(32 bit microprocessor, huge memories)

 Based on substrate
1. Passive substrate (R,C,L)
2. Active substrate(Si tech, Si-Ge tech, ..... Ge-As)

Si technology
 MOS BIPOLAR CMOS

NMOS PMOS a. P-well process

b. N-well process

High speed low speed c. Twin tub process

Low area large area d. SOI process

Large P.D. large P.D.

--> integration of both nmos and pmos

--> high speed

--> no static P.D.

--> dynamic P.D. increases with freq

Obtaining silicon:

The process of obtaining silicon is called zone refining.

Electronic Grade Silicon(EGS) , a polycrystalline material of high purity (99.99% pure) is raw
material for preparation of single crystal silicon.

RAW MATERIALS:- sand/silica/quartzite SiO2

 Major impurities present in this – Boron,Carbon

 Pure EGS requires that doping elements be in parts per billion range (ppb)
and carbon less than 2 ppm.

EGS requires multiple steps:-

1. SiO2 mixed with coal and heated at temperature greater than 1200 degree C.

SiO2 + SiC ---> Si + SiO + CO

(solid) (solid) (liq) (gas) (gas)

The above process is power intensive , requires 13 Wh/Kg and then Si is solidified which is
98% pure.

This Si is used for metal alloys but not for ICs due to impurities.

2. Si is mixed with HCl gas to get trichloroselane.

300C

Si + 3 HCl ----> SiHCl3 + H2(gas) + heat

(solid) (gas) (liquid at room temperature

subject to fractional distillation

to get pure SiHCl3)

900 degree Centigrade

 SiHCl3 + H2 -------------------------------------> Si + 3HCl

(gas) (99.99% pure)

Si obtained in this state is 99.99% pure and is further used.

FABRICATION PROCESS (PLANAR PROCESS)

1) Crystal Growth
2) EPITAXIAL Growth
3) Oxidation
4) Photolithography
5) Diffusion
6) Ion Implantation
7) Metallization

1.CRYSTAL GROWTH:

There are two methods of crystal growth: CZ process and Float Zone process.

 Starting material for crystal growth is highly purified (99.99) polycrystalline silicion
 CZ is most often used for producing Si crystal Silicon ingots
 Policrystalline silicon along with an appropriate amount of dopant is put in Quartz crucible
and is then placed in a furnace.
-->The material is then heated to a temperature in excess of silicon melting point 1420C.

--> A small single crystal rod of silicon called a seed crystal is then dipped into Si melt and
slowly pulled out.

-->As the seed crystal is pulled out of the melt, it brings with it a solidified mass of silicon with
same crystalline structure as that of seed crystal.
-->During crystal pulling process, the seed crystal and the crucible are rotated in opposite
directions in order to produce ingots of circular cross section.

-->Diameter is controlled by pulling rate.

--> Next top and bottom portions of ingot are cut off and ingot surface is ground to produce an
exact diameter.

-->Ingot is also ground flat slightly along length to get reference plane.

The silicon wafers so obtained have very rough surface due to slicing so polishing is done to get
a smooth surface.

WAFER SHAPING:-

After the crystal is grown,

 Remove the seed

 Grind the surface to define the diameter of the crystal
 One or more regions are ground along the length of wafer and these regions are
called flats , which will define
1. orientation of the crystal(<111> or <100>)
2. conductivity type (P or N)
 There are two flats,
1. Primary flat:- the longest one, allows the mechanical locator in an automatic
processing equipment to position the wafer and orient the devices relative to the
crystal.
2. Secondary flat:-which is the smaller flat identify the orientation and conductivity
type.
 3. The wafers are sliced using a diamond cutter and slicing determines crystal
orientation. <100> or <111>.
4. After slicing, the wafer is tapped using the mixture of Al2O3 and glycerin to produce
typical flatness uniformity within 2micro meter.
5. During lapping with Al2O3, there will be surface defects and they can be chemically
etched by using a developer solution (HF acid with acetic acid).

FLOAT ZONE PROCESS

It is used to grow Si crystal having less contamination (carbon and oxygen contamination)
compared to the CZ process. They are mainly used for high power, high voltage devices
having very high resistivity material, whereas the resistance is less in the case of CZ process.
Also those crystals obtained through float zone process, the purification is simple.

The schematic structure of float zone is as shown.

Atr high purity, poly-crystalline silicon with a seed crystal at the bottom is held in the vertical
position and roated. The rod is enclosed in a quartz envelope within which an inert
atmosphere (Argon) is maintained. During the process a small zone of approximately a few
cm length of the crystal is kept molten by a radio frequency heater, which is moved from
the sed upward so that the molten zone / floating traverses the length of the rod.

The surface tension between the solid and the molten Si will keep the Si atom together, so
that the crystal grows as single crystal, During this process, impurities are added to the Si so
that Si gets converted to P or N type.

2.EPITAXIAL GROWTH PROCESS:

To fabricate discrete devices and integrated circuits we make use of different kinds thin
films. These films are classified into five groups.

 Thermal Oxide
  Dielectric layers
 Epitaxial layers
 Poly crystalline layer
 Metal films

EPITAXIAL PROCESS

EPI + TAXI

Layered Ordered Process

 Layer-wise growth of Si under controlled temperature and controlled diffusion of

impurities.
 Process takes place inside a reactor at 800 – 900 degree centigrade
 Process is called CVD (Chemical vapour Deposition)
 Source of Silicon
o SiCl4 gas (silicon tetrachloride)
o Silane (SiH4)
 Reaction : H2 reduction at high temperature
SiCl4 + 2H2 ----- 1100 C ---- > Si + 4 HCl

SiH4 --- H2 Gas, T > 900 C --- > Si + 2H2

 Impurities added
o B2H6 (diborane)
o PH3 (Phosphine)
to get P / N silicon
Note:- All bipolar devices are fabricated in the N – epi layer.

Advantages of SiH4:

 Less temperature required

 Faster growth rate
 Less process time

The CVD mechanism involves a number of steps:

1. Reactants are transported into the substrate region

2. They are transferred to the substrate surface where they are absorbed
3. Chemical reaction takes place at the surface followed by EPITAXIAL growth.
4. The gaseous products are taken back by the gas stream
5. The reaction products are transported out of the reaction chamber

3.OXIDATION :

Why silicon is a natural choice for IC fabrication?

1. Silicon can be oxidized easily at a high temperature. SiO2 provides the required
isolation / surface passivation.
2. We can chemically etch SiO2 using HF acid (with acetic acid to control Ph)
3. Si has a very high band gap energy of 1.1 eV, hence it can be used for high
temperature and also leakage is less.
4. Si technology is an advanced technology
 Need for SiO2 isolation
 To make Si beneath SiO2 layer impervious to impurity diffusion
 Process of oxidation – LOCOS process (Local Oxidation of Si at high temperature)

LOCOS PROCESS

Wet Oxidation Dry Odixation

 Allow H2O vapour to pass through Allow Si + O2 to react at

Si at atemperature T >= 1100 C T > 900 C, we get SiO2

Si + 2H2O --- > SiO2 + 2H2 (gas) Si + O2 --- > SiO2

 used to grow thick oxide layer Used to grow thin oxide

called as Fox layer layer (thinox)

If thickness is > 1 Micro meter ----- > Fox layer

if thickness is < 1 micto meter ------ > Thinox layer

Thickness of SiO2 layer depends on;

 process temp
 process time
 impurity type and concentration
 crystal orientation

For additional surface passivation,we can use Si3N4 layer

Advantages of Si3N4

 better surface passivation

 good adhesive property
 prevents surface scratches
 it can be chemically etched using HF acid

4.PHOTOLITHOGRAPHY:

It is a process of transferring patterns of geometic shape on a mask onto a photo-sensitive

material called photoresist, covering the entire silicon wafer surface. These patterns define
the various regions in IC such as implantation region, diffusion region, contact window,
bonding contact pad areas.

Optical Lithography:

The wafer is placed in a clean room which is illuminated by yellow light. (photomasks are
insensitive to lights having wavelength >= 0.5 um). To enhance adhesiveness at the surface,
the surface must be changed from hydrophobic to hydrophilic and later a promoter is added
to the silicon surface. The wafer is accelerated at constant rotation speed (1000/10,000
rpm) for about 30 seconds to get uniform film of 0.5-1 um thickness. The thickness of the
photoresist is related to its viscosity. After the spinning, the wafer is soft baked at 90-120
degree Celsius to remove the solvent from photoresist film. The photomask is placed over
the wafer and resist is exposed to UV light. When light is incident, it will undergo
polymerisation to get PPR (polymerised photoresist). The wafer is then rinsed and dried and
post baked at about 100-180 degree Celsius to improve the adhesiveness of resist to the
substrate.
Using the developer’s solution, we can chemically etch the unexposed photoresist and then
SiO2 layer beneath it. The PPR will provide the necessary passivation. After etching SiO2
layer, we can chemically etch the rest of the PPR using developer solution again. This will
leave behind a window opening in SiO2.

The performance of an exposure tool is evaluated by 3 parameters:

1. Resolution: It is the minimum feature dimension that can be transferred with high
fidelity to a resist film on Si wafer.
2. Registration: It is the measure of how accurately the patterns on successive mask can
be aligned with respect to the previously defined patterns on the wafer.
3. Throughput: It is the number of masks that can be exposed per hour in a repetitive
operation.

There are two types of optical exposure methods:

1. Proximity printing: Here the mask is placed at a small distance above the wafer
surface. The resolution is degraded to 2-5 um range. This is because of the diffraction
occurring at the corners when the light is incident.
2. Contact printing: Here the wafer is brought into physical contact with the mask.
Better resolution of 1 um is provided in this case. But the major drawback is caused
by the dust particles, which are embedded in the mask during exposure causing
defect. And in repetitive exposure , the mask will get damaged. This drawback is
rectified using proximity printing.
X-ray lithography:
In X-ray lithography, an X-ray source illuminates a mask , which casts shadows into a resist
covered wafer. X- rays have lower wavelength than Ultraviolet rays. As the
wavelength is reduced , diffraction effects are reduced and resolution is improved.
 5.DIFFUSION:

 Due to lateral diffusion, we can’t construct shallow region using diffusion method.
 Diffusion is not used if doping concentration is critical.

Like → Emitter region of BJT

→ Gate of JFET

→ Channel region of MOSFET

 Diffusion takes place in a diffusion furnace at 800-900° C.

 Water is placed inside the diffusion chamber. N 2 or D2 gas will transport implies into
the diffusion furnace.
 Impurities are
Solid sources → Bn for Boron

→ As2 O 3 for Arsenic

→ P2 O5 for Phosphorous

Liquid sources

Are → B Br3

→ As Cl3

→ P O Cl3

Gas sources

Are → B H6

→ As H3
 → P H3

 The diffusion depth (xj) depends on:-

→ Process temperature

→ Process time

→ Impurity concentration

6.ION IMPLANTATION:-

Latest method of Doping:-

Transmutation (to know exact doping conc.) by mass change.

Si + A° → P31 (each Si atom is bombarded)

Ion implantation is the introduction of high energy charged particles into Si substrate, the
implantation energy in the range 1 KeV to 1 MeV. This results in an average depth from 10
nm to 10 µm, with an average doping density of 10 12 ions / cm2 , for threshold volt
adjustment, 1012 to 1018 ions / cm2 in the case of buried insulation layers.
The advantages of implantation are,

1. Precise control
2. Reproducibility of impurity doping
3. Lower process temperature
4. Less process time

The Gas sources are B F3 or AsH3 , heated to high temperature, where they breakup to gas
ions B+ , As+ and extraction voltage of 40 kV is used to move the charged ions out of the
chamber, the ions will enter to mass analiser where it is subject to an external magnetic
field. The magnetic field is selected such that only those ions having the desired mass to
charge ratio can travel through it without being filtered.

The selected ions can enter the acceleration tube where they are accelerated to the
implantation energy. The apertures ensures that beam is well collimated. The pressure in
the implantation region/chamber is kept below 10 4 Pa to minimize the scattering of gas
molecules. The ion beam is then scanned over the water surface using electrostatic
deflection plates. Thus the high energy ions are implanted into the Si wafer.

The energetic ions lose energy through collisions with e and nuclei and then comes
to rest inside the substrate. The average depth where the ions comes to rest can be
controlled by adjusting the accelerating energy. The side effect of implantation is the
damage to the semiconductor due to collision. Hence we make use of Rapid Thermal
Annealing process (RTA) to minimise the crystal defects. By controlling the temperature and
time we can remove the implant damage.

The implant depth (xj) depends upon two parameters,

1. The accelerating potential / energy,

2. Beam current

7.METALLISATION :-

It is a process of defining metal contacts and metal interconnects on the Si wafer

surface. Using photo-lithography we define contact openings on Si O 2 layer. Al is heated to a
high temperature approximately 600° C. Al vapourises, the Al vapour is allowed to pass
through the Si surface , Al will get deposited aver Si. This process is called vaccum
evaporation of Al inside a bell jar / CVD process.

Al deposit has a thickness of approximately 2 µM.

Using an interconnection mask, we can chemically etch the excess Al using H 3PO4
(phosphoric acid).

During metallization two problem are associatedwith the process,

1. Ion spiking
(The melting point of Si & Al becomes than that of Al and is 577° C)

Therefore substrate temperature can’t exceed 577° C.

2. Elecromigration:-
At high field and at high current density, there is a transport mass and nuclei from one
point to another due to interaction of e - and nuclei cousing voids in the metal which leads to
an open circuit during or after fabrication.

DIFFUSION ION IMPLANTATION

It is requires temperature(T>9000C ) It is temperature independent

It requires long time It requires less time (few seconds to

minutes).

It is uncontrolled process It is controlled process

Concentration gradient of impurities drives High energy impurity ions are implanted in
the carrier in the Si wafer. the wafer.

It can’t be used to fabricate region where It is used to fabricate region where the
the doping is critical. doping is critical.

Diffusion depth depends on time, process, It depends on beam current, accelerating

temperature, impurity concentration. potential.

It is crystal friendly(no crystalline defects). There are crystalline defects.

CMOS FABRICATION

Various ways of CMOS FABRICATION are:

 1) N-well process
2) P-well process
3) Twin-Tub process
4) Silicon on insulator process (SOI)

The basic masks for fabrication are as follows (For P-well process)
MASK 1: Defines the areas in which the deep p-well diffusions are to take place
MASK 2: Defines the thin oxide regions , those areas where the thick oxide is to be
stripped and thin oxide grown to accommodate p and n transistors and wires.
MASK 3: Used to pattern polysilicon layer which is deposited after thin oxide.
MASK 4: A p-plus mask is now used to define all areas where p-diffusion take place.
MASK 5 : Defines areas where n-type diffusion is to take place.
MASK 6: Contact cuts & metal layer pattern defined.

P-well process:
Fabrication of CMOS inverter:-
As it is p-well process; p-well will act as p type substrate and will be used for fabrication of
NMOS while N type substrate for PMOS.

BASIC STEPS : CRYSTAL GROWTH

1) N-type silicon crystal is created using Czochralski process.
Sliced to get N type Si wafer for substrate (Crystal is sliced).Such wafers have 75 to
150mm of diameter and 0.4mm thick and are doped with impurity concentration of
1015/cm3 to 1016/cm3.

2) OXIDATION
Deposition os silicon-dioxide layer ≈30-35nm which acts as pasivation layer(prevents
entry of impurities).
Deposition of Silicon nitride layer over silicon dioxide which acts as better passivation
layer and provide mechanical strength
 MASK 1: P-well implant

3) MASK 2: Defines areas where thick oxide is stripped and thin oxide is grown

4) Polysilicon Gate Deposit

 Apply PPR (positive photo resist ) over silicon.
 Develop p-well mask on any mask layout pattern is transferred from mask on
silicon surface.
 (REFER PHOTOLITHOGRAPHY NOTES ON EXACTLY WHAT HAPPENS)
 Etch PPR, remove Silicon-dioxide/silicon nitride layer
 Implant B+ ions to get a p-well
 Redeposit silicon dioxide and silicon nitride layer
 Develop Fox layer & grow thin oxide layer.

MASK 3: Polysilicon mask

Deposit polysilicon over entire Si using chemical vapour deposition process than
photoresist is coated over polysilicon. The areas where poly gate is to be defined
using polymask are unexposed to UV light while other area is exposed so PPR is
removed from exposed area and polysilicon is also etched alongwith silicon dioxide
and slicon nitride etched using developing solution.
Finally the PPR which was unexposed is also etched so we get the gate os our
transistor.

MASK 4: N+ mask Drain or Source of NMOS and body for PMOS

 MASK 5: P+ mask for drain or source of PMOS and P+ for body of NMOS

Next step is just to have smooth surface deposit phosphorous in Si and deposit it.

MASK 6: Metallization: It is same like polysilicon deposition. Aluminium is heated

upto 6000C and when it melts is passed over entire Si surface than using PPR and
metal mask . Areas where metal contacts are not required are exposed to UV light
and PPR is etched from these areas also aluminium beneath such PPR (as it is the
area where metal contacts are not required) is etched using H 3PO4 and other areas
where metal contacts are required (later only PPR is etched and hence we get our
contacts).

Final Design/fabrication looks like:-

In N-well process replace all n with p and vice versa.

Twin Tub Process:

 Start with N+ Si substrate to reduce parasites to prevent Latch Up.

 Grow N- epitaxial layer (Epitaxial layer is thin layer with controlled thickness and
uniform doping density)
a. Crystal Growth(same as before)
b. Epitaxial growth

c. Oxidation(same as before)
d. P well and N well implant using two different masks.

Then Polysilicon deposit, diffusion, metallization all steps same as before.

 High doping of N+ or P+ substrate is used to prevent Latch Up.

SOI/SOS CMOS PROCESS

SOI- Si on insulator

SOS- Si on sapphire

 Start with insulator/sapphire instead of p/n Si substrate

 Grow an epitaxial n-layer over4 insulator & surface is oxidized

 Using a photo mask etch Si layer to get to n-islands & deposit Sio 2

 Mask one n-layer & convert the other n layer to p island and deposit thin oxide layer
over surface

 Fabricate NMOS transistor in p-island & PMOS transistor in n-island

Fabrication of the nMOS Transistor

1. Crystal growth: Using the Czochralski process, P-type silicon substrate is developed
from silicon crystal.

2. Oxidation: A layer of SiO2 having thickness of around 30 to 35 nanometer is

deposited on the surface. This layer acts as passivation layer which prevents the
entry of impurities into the substrate.
A layer of silicon nitrite Si 3N4 is deposited over the SiO2 layer which acts as a better
passivation layer and provides mechanical strength .

3. MASK 1 : Development of p+channel stopper:

Channel stopper/isolation islands are used to electrically isolate different transistors
on the chip. A p+ mask is used in the lithography process to obtain channel stopper.
 As shown in the figure, the mask covers the required portion of the photoresist.
Then it is exposed to UV light. Part of the photoresist which is exposed becomes
soluble and can be removed with developing
solution.

After the formation of the channel stopper, unexposed photoresist is also etched.
And then in the oxidation chamber, thick oxide layer called field oxide layer is
deposited. This creates oxide isolation around active areas.

4. MASK 2: Oxide layer thickness is approximately 30-35 nm. For gate we need oxide
layer thickness of about 10-15 nm. So Si 3N4 layer is etched along with oxide layer (but
not field oxide) and through dry oxidation thin oxide layer is deposited in those
regions( where oxide apprx. 35 nm was etched)

5. MASK 3 : N channel/ P channel implant (Only for depletion mosfet and not
enhancement mosfet because in Depletion type the channel already exists)
For N channel, As+ ions are implanted into the channel region. For P channel B+,
ions are implanted.
6. MASK 4 : Polysilicon deposit
First a layer of polysilicon (1.5 um thick) is deposited on the surface using chemical
vapour deposition process. A photoresist is deposited over the entire polysilicon.
Area where polygate is to be defined is kept unexposed to UV light with the help of
the mask. Other areas are exposed and the photoresist is removed from these areas.
Polysilicon along with SiO2 and Si3N4 are also etched using H2SO4/HCl.

Then even the unexposed photoresist is etched later and we get the gate of the
transistor. N+ ions are ion-implanted into Si substrate at approximately 30 KeV
energy and they align themselves with the gate. Transistor drain and source are thus
defined.

7. MASK 5: Redeposition of Field oxide

If field oxide is etched while etching thin oxide, it has to be redeposited. First thick
oxide is deposited over the surface and then all the regions where thick oxide is not
required is etched using mask.

8. MASK 6: Metallization
Aluminium is heated up to 600 degree Celsius and when it melts, it is passed over
entire surface. Photoresist is deposited on the surface as well. Areas where metal
contacts are not required are exposed to UV light and photoresist is etched from
these areas. The metal beneath the exposed area is removed with the help of H 3PO4.
The unexposed photoresist is also etched later on leaving behind required metal
contacts
9. Phosphorous is deposited over silicon to obtain smoothness
The final fabrication:

Enhancement Load MOS inverter

If depletion load NMOS inverter asked, modify the above diagram.

For PMOS replace P with N and N with P.