1. no.

of (#) flops in the design

245037 Flip-Flops
1. #scan_clk 5
2. #funcional_clk 7

3. #reset and value

4. #scan channels
140 scan channels

5. #scan chains (full scan)

140 scan chain

6. max chain length (full scan)

The length of the longest scan chain is 1755 bit positions, which is 101% of the average scan
chain length 1748 (based on 244713 total scan chain bits and 140 valid scan chains)

7. #internal scan chains (compression mode)

The length of the longest scan chain is 117 bit positions, which is 101% of the average scan chain
length 117 (based on 244713 total scan chain bits and 2100 valid scan chains)
8. max chain length in compression mode ?
Longest Scan Chain: 117 bits
9. what are the violations (TSV) reported in the log
WARNING (TSV-093):

[Severe] During the scan operation three state net

dut_core_dftw_inst.dut_core_inst.winnet0_top_wn_interftransition_faultes_pe
tbi_a_peanx_top_1_peanx_sync_1_pulse_sync_annpd_unconnected is sourced by
block
dut_core_dftw_inst.dut_core_inst.winnet0_top_wn_interftransition_faultes_pe
tbi_a_peanx_top_1_peanx_sync_1_pulse_sync_annpd_p1268A.U2 and block
dut_core_dftw_inst.dut_core_inst.winnet0_top_wn_interftransition_faultes_pe
tbi_a_peanx_top_1_peanx_sync_1_pulse_sync_cpgrx_p1268A.U2 which may
simultaneously drive opposite values resulting in 3-state contention. [end
TSV_093]

WARNING (TSV-390):
There are 10719 intransition_faulttive (non-scan) latches. [end
TSV_390]
INFO (TSV-383):
There are 8362 floating latches. [end TSV_383]
INFO (TSV-068): The length of the longest scan chain is 117 bit
positions, which is 101% of the average scan chain length 117 (based on
244713 total scan chain bits and 2100 valid scan chains). [end TSV_068]
INFO (TSV-378): Scan chain beginning at 'pin scan_in[137]' and ending
at 'pin
dut_core_dftw_inst.cfu_tx_ser_transition_faultk_0_xx0x_x1x_x2x_x3xx_reg
_net_reg_4bit.U11.DFF.Q' is controllable and observable. The length of
the scan chain is 110 bit positions. [end TSV_378]
INFO (TSV-378):
Scan chain beginning at 'pin scan_in[135]' and ending at 'pin
dut_core_dftw_inst.cfu_tx_ser_data_0_xx156x_x157x_x158x_x159xx_reg_net_
reg_4bit.U14.DFF.Q' is controllable and observable. The length of the
scan chain is 110 bit positions. [end TSV_378]
WARNING (TSV-024):
[Severe] The select input of MUX block
dut_core_dftw_inst.dut_core_inst.qsgmii1_qsgmii_reset_sync_qsgmii_pcs_t
x_reset_reset_sync__sync_rstb___clk_mux_inst___clk_mux_basic_virage_lc9
_lvt_inst.U1 is fed by a clock pin por_int_rstb. [end TSV_024]
WARNING (TSV-101):
[Severe] Unpredictable signal value (X) from Floating Memory Element
block
dut_core_dftw_inst.dut_core_inst.upi0_top_upi_rx_top_upi_rx_data_top_up
i_rx_data_stm_upi_data_stm_rf_env_upi_sprf_256_32_trfhdpg256x33_bistw_i
nst_two_inst_check_inst_gen_bist_din_fll_bypass_ff_on_bist_din_fll_0_in
st_bist_din_fll_inst_q_reg.U0 may be observed at block
dut_core_dftw_inst.dut_core_inst.upi0_top_upi_rif_slave_upi_rif_control
ler_pre_rif_datr_reg_x0_1_2_3x_inst_4bit.U13.DFF.

10. any scan chain broken issue reported ?

WARNING (TSV-093):

[Severe] During the scan operation three state net

dut_core_dftw_inst.dut_core_inst.winnet0_top_wn_interftransition_faultes_pe
tbi_a_peanx_top_1_peanx_sync_1_pulse_sync_annpd_unconnected is sourced by
block
dut_core_dftw_inst.dut_core_inst.winnet0_top_wn_interftransition_faultes_pe
tbi_a_peanx_top_1_peanx_sync_1_pulse_sync_annpd_p1268A.U2 and block
dut_core_dftw_inst.dut_core_inst.winnet0_top_wn_interftransition_faultes_pe
tbi_a_peanx_top_1_peanx_sync_1_pulse_sync_cpgrx_p1268A.U2 which may
simultaneously drive opposite values resulting in 3-state contention. [end
TSV_093]

11. Total howmany tests (testmode) ? listout order and try to understand this order ?
can change this order ?
Ans: transition_fault_NO_CLK_GATE
stuck-at_fault
stuck-at_fault_NO_CLK_GATE
stuck-at_fault_NO_CLK_GATE_RESET_CONTROL
 stuck-at_fault_NOCOMPRESSION_NO_CLK_GATE
stuck-at_fault_RAM
stuck-at_fault_RAM_NOCOMPRESSION

12. howmany # scan patterns ? and coverage ?

***********************************************************************
***************
Testmode Statistics: transition_fault_NO_CLK_GATE
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6600362 1566105 1460 0 5032797 23.73 23.73
Total Dynamic 5828554 1206537 0 0 4622017 20.70 20.70
Global Statistics
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6664254 1566105 1460 0 5096689 23.50 23.50
Total Dynamic 6662248 1206537 0 0 5455711 18.11 18.11
***********************************************************************
***************
----Final Pattern Statistics----
Test Section Type # Test Sequences
----------------------------------------------------------
Scan 1
----------------------------------------------------------
Total 1

13. howmay # logic patterns ? and coverage ?

: transition_fault_NO_CLK_GATE
stuck-at_fault
stuck-at_fault_NO_CLK_GATE
stuck-at_fault_NO_CLK_GATE_RESET_CONTROL
stuck-at_fault_NOCOMPRESSION_NO_CLK_GATE
stuck-at_fault_RAM
stuck-at_fault_RAM_NOCOMPRESSION
39793
1978
338
63
5151
373

14. what are the files writing out after every test ?
15. Is there commit test done in the log ?
16. # faults ?

: transition_fault_NO_CLK_GATE
stuck-at_fault
stuck-at_fault_NO_CLK_GATE
stuck-at_fault_NO_CLK_GATE_RESET_CONTROL
stuck-at_fault_NOCOMPRESSION_NO_CLK_GATE
 stuck-at_fault_RAM
stuck-at_fault_RAM_NOCOMPRESSION

***********************************************************************
***************
Testmode Statistics: transition_fault_NO_CLK_GATE
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6600362 4468386 5099 0 2126877 67.70 67.70
Total Dynamic 5828554 2961084 20 0 2867450 50.80 50.80
Global Statistics
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6664254 4468386 5099 0 2190769 67.05 67.05
Total Dynamic 6662248 2961084 20 0 3701144 44.45 44.45
***********************************************************************
***************
----Final Pattern Statistics----
Test Section Type # Test Sequences
----------------------------------------------------------
Logic 3928
----------------------------------------------------------
Total 3928
INFO (TBD-809): Master test vector file statistics: [end TBD_809]
experiments = 1
test sections = 1
tester loops = 1
test procedures = 63
test sequence = 3928
init sequencess = 1
patterns = 19658
events = 27530
INFO (TBD-805): File(s) generated (bytes and name): [end TBD_805]
138829945 ./tbdata/TBDbin.transition_fault_NO_CLK_GATE
178823168 ./tbdata/faultStatus
***********************************************************************
***************
Testmode Statistics: stuck-at_fault
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6283241 6238100 5160 23198 16783 99.28 99.65
Global Statistics
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6664254 6494763 5160 23198 141133 97.46 97.80
***********************************************************************
***************
----Final Pattern Statistics----
Test Section Type # Test Sequences
----------------------------------------------------------
Logic 6849
----------------------------------------------------------
Total 6849
INFO (TBD-809): Master test vector file statistics: [end TBD_809]
experiments = 1
test sections = 1
tester loops = 1
test procedures = 114
test sequence = 6849
init sequencess = 1
patterns = 39793
events = 46698
INFO (TBD-805): File(s) generated (bytes and name): [end TBD_805]
318530339 ./tbdata/TBDbin.stuck-at_fault
182177792 ./tbdata/faultStatus
***********************************************************************
***************
Testmode Statistics: stuck-at_fault_NO_CLK_GATE
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6600362 6549767 5155 24071 21369 99.23 99.60
Global Statistics
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6664254 6549770 5155 24076 85253 98.28 98.64
***********************************************************************
***************
----Final Pattern Statistics----
Test Section Type # Test Sequences
----------------------------------------------------------
Logic 392
----------------------------------------------------------
Total 392
INFO (TBD-809): Master test vector file statistics: [end TBD_809]
experiments = 1
test sections = 1
tester loops = 1
test procedures = 9
test sequence = 392
init sequencess = 1
patterns = 1978
events = 2410
INFO (TBD-805): File(s) generated (bytes and name): [end TBD_805]
20760605 ./tbdata/TBDbin.stuck-at_fault_NO_CLK_GATE
182177792 ./tbdata/faultStatus
***********************************************************************
***************
Testmode Statistics: stuck-at_fault_NO_CLK_GATE_RESET_CONTROL
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6472509 6422225 5165 24360 20759 99.22 99.60
Global Statistics
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6664254 6550072 5165 24365 84652 98.29 98.65
***********************************************************************
***************
----Final Pattern Statistics----
Test Section Type # Test Sequences
----------------------------------------------------------
Logic 64
----------------------------------------------------------
Total 64
INFO (TBD-809): Master test vector file statistics: [end TBD_809]
experiments = 1
test sections = 1
tester loops = 1
test procedures = 2
test sequence = 64
init sequencess = 1
patterns = 338
events = 418
***********************************************************************
***************
Testmode Statistics: stuck-at_fault_NOCOMPRESSION_NO_CLK_GATE
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6590637 6542403 5261 24382 18591 99.27 99.64
Global Statistics
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6664254 6559117 5261 24387 75489 98.42 98.78
***********************************************************************
***************
----Final Pattern Statistics----
Test Section Type # Test Sequences
----------------------------------------------------------
Logic 725
----------------------------------------------------------
Total 725
***********************************************************************
***************
Testmode Statistics: stuck-at_fault_NOCOMPRESSION_NO_CLK_GATE
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6590637 6540584 5162 24384 20507 99.24 99.61
Global Statistics
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6664254 6557298 5162 24389 77405 98.40 98.76
***********************************************************************
***************
----Final Pattern Statistics----
Test Section Type # Test Sequences
----------------------------------------------------------
Logic 9
----------------------------------------------------------
Total 9

***********************************************************************
***************
Testmode Statistics: stuck-at_fault_RAM
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6590174 6544549 2776 23310 19539 99.31 99.66
Global Statistics
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6664254 6567151 5728 24385 66990 98.54 98.90
***********************************************************************
***************
----Final Pattern Statistics----
Test Section Type # Test Sequences
----------------------------------------------------------
Logic 1308
----------------------------------------------------------
Total 1308
***********************************************************************
***************
Testmode Statistics: stuck-at_fault_RAM_NOCOMPRESSION
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6580449 6534025 2783 23323 20318 99.29 99.65
Global Statistics
#Faults #Tested #Possibly #Redund #Untested %TCov %ATCov
Total Static 6664254 6566682 5735 24398 67439 98.54 98.90
***********************************************************************
***************
----Final Pattern Statistics----
Test Section Type # Test Sequences
----------------------------------------------------------
Logic 71
----------------------------------------------------------
Total 71
INFO (TBD-809): Master test vector file statistics: [end TBD_809]
experiments = 1
test sections = 1
tester loops = 1
test procedures = 3
test sequence = 71
init sequencess = 1
patterns = 373
events = 508
INFO (TBD-805): File(s) generated (bytes and name): [end TBD_805]
8759786 ./tbdata/TBDbin.stuck-at_fault_RAM_NOCOMPRESSION
182177792 ./tbdata/faultStatus
Analyze three-state drivers for contention