Computer Architecture

ECE 361
Lecture 5: The Design Process & ALU Design

361 design.1
 Quick Review of Last Lecture

361 design.2
 MIPS ISA Design Objectives and Implications

°Support general OS and C-

style language needs

°Support general and

Traditional data
embedded applications types, common
operations, typical
°Use dynamic workload
characteristics from general
addressing modes
purpose program traces
and SPECint to guide
design decisions

°Implement processor core

with a relatively small RISC-style:
number of gates
Register-Register /
°Emphasize performance Load-Store
via fast clock

361 design.3
 MIPS jump, branch, compare instructions
° Instruction Example Meaning

° branch on equal beq $1,$2,100 if ($1 == $2) go to PC+4+100

Equal test; PC relative branch

° branch on not eq. bne $1,$2,100 if ($1!= $2) go to PC+4+100

Not equal test; PC relative

° set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0
Compare less than; 2’s comp.

° set less than imm.slti $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; 2’s comp.

° set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0
Compare less than; natural numbers

° set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; natural numbers

° jump j 10000 go to 10000

Jump to target address

° jump register jr $31 go to $31

For switch, procedure return

° jump and link jal 10000 $31 = PC + 4; go to 10000

For procedure call
361 design.4
 Example: MIPS Instruction Formats and Addressing Modes

• All instructions 32 bits wide

6 5 5 5 11
Register (direct) op rs rt rd

register
Immediate op rs rt immed

Base+index
op rs rt immed
Memory
register +
PC-relative
op rs rt immed
Memory

PC +

361 design.5
 MIPS Instruction Formats

361 design.6
 MIPS Operation Overview

° Arithmetic logical

° Add, AddU, AddI, ADDIU, Sub, SubU

° And, AndI, Or, OrI

° SLT, SLTI, SLTU, SLTIU

° SLL, SRL

° Memory Access

° LW, LB, LBU

° SW, SB

361 design.7
 Branch & Pipelines

Time

li r3, #7 execute

sub r4, r4, 1 ifetch execute

bz r4, LL ifetch execute Branch

addi r5, r3, 1 ifetch execute Delay Slot
LL: slt r1, r3, r5
Branch Target ifetch execute

By the end of Branch instruction, the CPU knows whether or not

the branch will take place.

However, it will have fetched the next instruction by then,

regardless of whether or not a branch will be taken.

Why not execute it?

361 design.8
 The next Destination
Input Input
Multiplicand Multiplier

32

Multiplicand
Register LoadMp

Arithmetic
32=>34
signEx
32
<<1
34 1000 µProc
34
32=>34 1 0
CPU 60%/yr
signEx 34x2 MUX
34
Multi x2/x1 “Moore’s Law” .
34
(2X/1.

Performance
100 5yr)
Processor-Memory
34-bit ALU Sub/Add
Control Performance Gap:
Logic
34
(grows 50% / year)
10

[0]"
32 2 32 ShiftAll

"L O
ENC[2] DRAM

LO[1]

Encoder
2 HI register 2 LO register

2 bits

Booth
9%/yr.

Extra
ENC[1]

Prev
(16x2 bits) (16x2 bits) DRAM(2X/10
ENC[0]
2
1

LoadLO
ClearHI
LoadHI
LO[1:0] yrs)

1
1
9
1
9
8
1
9
8
0
1
9
8
1
1
9
8
2
1
9
8
3
1
9
8
4
1
9
8
5
1
9
8
6
1
9
8
7
1
9
8
1
9
9
1
9
10
9
9
1
91
9
2
1
9
13
49
9
1
95
91
9
6
2
79
0
9
8
0
9
0
32 32

Result[HI] Result[LO] Time

Single/multicycle
Datapaths

Begin ALU design using MIPS ISA.

IFetchDcd Exec Mem WB

IFetchDcd Exec Mem WB

IFetchDcd Exec Mem WB

IFetchDcd Exec Mem WB

Pipelining

I/O
361 design.9
Memory Systems
 Outline of Today’s Lecture

° An Overview of the Design Process

° Illustration using ALU design

° Refinements

361 design.10
 The Design Process

"To Design Is To Represent"

Design activity yields description/representation of an object

-- Traditional craftsman does not distinguish between the

conceptualization and the artifact

-- Separation comes about because of complexity

-- The concept is captured in one or more representation languages

-- This process IS design

Design Begins With Requirements

-- Functional Capabilities: what it will do

-- Performance Characteristics: Speed, Power, Area, Cost, . . .

361 design.11
 Design Process

Design Finishes As Assembly CPU

-- Design understood in terms of Datapath Control
components and how they have
been assembled ALU Regs Shifter
-- Top Down decomposition of
complex functions (behaviors)
into more primitive functions Nand
Gate
-- bottom-up composition of primitive
building blocks into more complex assemblies

Design is a "creative process," not a simple method

361 design.12
 Design Refinement
Informal System Requirement

Initial Specification

Intermediate Specification

refinement
increasing level of detail
Final Architectural Description

Intermediate Specification of Implementation

Final Internal Specification

Physical Implementation
361 design.13
 Design as Search

Problem A

Strategy 1 Strategy 2

SubProb 1 SubProb2 SubProb3

BB1 BB2 BB3 BBn

Design involves educated guesses and verification

-- Given the goals, how should these be prioritized?

-- Given alternative design pieces, which should be selected?

-- Given design space of components & assemblies, which part will yield
the best solution?

Feasible (good) choices vs. Optimal choices

361 design.14
 Problem: Design a “fast” ALU for the MIPS ISA

° Requirements?

° Must support the Arithmetic / Logic operations

° Tradeoffs of cost and speed based on frequency of occurrence,

hardware budget

361 design.15
 MIPS ALU requirements

° Add, AddU, Sub, SubU, AddI, AddIU

• => 2’s complement adder/sub with overflow detection
° And, Or, AndI, OrI, Xor, Xori, Nor
• => Logical AND, logical OR, XOR, nor
° SLTI, SLTIU (set less than)
• => 2’s complement adder with inverter, check sign bit of result

361 design.16
 MIPS arithmetic instruction format
31 25 20 15 5 0
R-type:
op Rs Rt Rd funct

I-Type: op Rs Rt Immed 16

Type op funct Type op funct Type op funct

ADDI 10 xx ADD 00 40 00 50
ADDIU 11 xx ADDU 00 41 00 51
SLTI 12 xx SUB 00 42 SLT 00 52
SLTIU 13 xx SUBU 00 43 SLTU 00 53
ANDI 14 xx AND 00 44
ORI 15 xx OR 00 45
XORI 16 xx XOR 00 46
LUI 17 xx NOR 00 47

° Signed arith generate overflow, no carry

361 design.17
 Design Trick: divide & conquer

° Break the problem into simpler problems, solve them and glue together
the solution

° Example: assume the immediates have been taken care of before the
ALU
• 10 operations (4 bits) 00 add
01 addU
02 sub
03 subU
04 and
05 or
06 xor
07 nor
12 slt
13 sltU

361 design.18
 Refined Requirements
(1) Functional Specification
inputs: 2 x 32-bit operands A, B, 4-bit mode (sort of control)
outputs: 32-bit result S, 1-bit carry, 1 bit overflow
operations: add, addu, sub, subu, and, or, xor, nor, slt, sltU

(2) Block Diagram (CAD-TOOL symbol, VHDL entity)

32 32

A B 4
c ALU m
ovf
S
32

361 design.19
 Behavioral Representation: VHDL

Entity ALU is
generic (c_delay: integer := 20 ns;
S_delay: integer := 20 ns);

port ( signal A, B: in vlbit_vector (0 to 31);

signal m: in vlbit_vector (0 to 3);
signal S: out vlbit_vector (0 to 31);
signal c: out vlbit;
signal ovf: out vlbit)
end ALU;

...

S <= A + B;

361 design.20
 Design Decisions

ALU

bit slice

7-to-2 C/L 7 3-to-2 C/L

PLD Gates CL0 CL6 mux

° Simple bit-slice
• big combinational problem
• many little combinational problems
• partition into 2-step problem

° Bit slice with carry look-ahead

° ...

361 design.21
 Refined Diagram: bit-slice ALU

A 32 B 32

a31 b31 a0 b0 4
ALU0 m ALU0 m
M
co cin co cin
s31 s0

Ovflw
32
S

361 design.22
 7-to-2 Combinational Logic

° start turning the crank . . .

Function Inputs Outputs K-Map

M0 M1 M2 M3 A B Cin S Cout
0 add 0 0 0 0 0 0 0 0 0

127
361 design.23
 A One Bit ALU

° This 1-bit ALU will perform AND, OR, and ADD

CarryIn

Mux
Result

1-bit
Full
B Adder

CarryOut

361 design.24
 A One-bit Full Adder CarryIn

A 1-bit
° This is also called a (3, 2) adder C
Full
B Adder
° Half Adder: No CarryIn nor CarryOut

° Truth Table: CarryOut

Inputs Outputs

A B CarryIn CarryOut Sum Comments

0 0 0 0 0 0 + 0 + 0 = 00
0 0 1 0 1 0 + 0 + 1 = 01
0 1 0 0 1 0 + 1 + 0 = 01
0 1 1 1 0 0 + 1 + 1 = 10
1 0 0 0 1 1 + 0 + 0 = 01
1 0 1 1 0 1 + 0 + 1 = 10
1 1 0 1 0 1 + 1 + 0 = 10
1 1 1 1 1 1 + 1 + 1 = 11
361 design.25
 Logic Equation for CarryOut

Inputs Outputs

A B CarryIn CarryOut Sum Comments

0 0 0 0 0 0 + 0 + 0 = 00
0 0 1 0 1 0 + 0 + 1 = 01
0 1 0 0 1 0 + 1 + 0 = 01
0 1 1 1 0 0 + 1 + 1 = 10
1 0 0 0 1 1 + 0 + 0 = 01
1 0 1 1 0 1 + 0 + 1 = 10
1 1 0 1 0 1 + 1 + 0 = 10
1 1 1 1 1 1 + 1 + 1 = 11

° CarryOut = (!A & B & CarryIn) | (A & !B & CarryIn) | (A & B & !CarryIn)
| (A & B & CarryIn)

° CarryOut = B & CarryIn | A & CarryIn | A & B

361 design.26
 Logic Equation for Sum

Inputs Outputs

A B CarryIn CarryOut Sum Comments

0 0 0 0 0 0 + 0 + 0 = 00
0 0 1 0 1 0 + 0 + 1 = 01
0 1 0 0 1 0 + 1 + 0 = 01
0 1 1 1 0 0 + 1 + 1 = 10
1 0 0 0 1 1 + 0 + 0 = 01
1 0 1 1 0 1 + 0 + 1 = 10
1 1 0 1 0 1 + 1 + 0 = 10
1 1 1 1 1 1 + 1 + 1 = 11

° Sum = (!A & !B & CarryIn) | (!A & B & !CarryIn) | (A & !B & !CarryIn)
| (A & B & CarryIn)

361 design.27
 Logic Equation for Sum (continue)

° Sum = (!A & !B & CarryIn) | (!A & B & !CarryIn) | (A & !B & !CarryIn)
| (A & B & CarryIn)

° Sum = A XOR B XOR CarryIn

° Truth Table for XOR:

X Y X XOR Y
0 0 0
0 1 1
1 0 1
1 1 0

361 design.28
 Logic Diagrams for CarryOut and Sum

° CarryOut = B & CarryIn | A & CarryIn | A & B

CarryIn

B CarryOut

° Sum = A XOR B XOR CarryIn

CarryIn
A
B Sum

361 design.29
 Seven plus a MUX ?
° Design trick 2: take pieces you know (or can imagine) and try to put
them together

° Design trick 3: solve part of the problem and extend

S-select
CarryIn
and
A

or Result

Mux
1-bit add
Full
B Adder

CarryOut
361 design.30
 A 4-bit ALU

° 1-bit ALU 4-bit ALU

CarryIn0
CarryIn
A0 1-bit
A Result0
B0 ALU
CarryIn1 CarryOut0
A1 1-bit Result1
Result B1 ALU
Mux
CarryIn2 CarryOut1
A2 1-bit Result2
B2 ALU
1-bit CarryIn3 CarryOut2
Full A3
B 1-bit Result3
Adder
B3 ALU

CarryOut CarryOut3

361 design.31
 How About Subtraction?

° Keep in mind the followings:

• (A - B) is the that as: A + (-B)
• 2’s Complement: Take the inverse of every bit and add 1

° Bit-wise inverse of B is !B:

• A + !B + 1 = A + (!B + 1) = A + (-B) = A - B

Subtract

A CarryIn
4
Zero

“ALU”
Result
Sel 4
2x1 Mux

B 0
4
1 4
4 !B CarryOut

361 design.32
 Additional operations

° A - B = A + (– B)
• form two complement by invert and add one
S-select
invert CarryIn
and
A

or Result

Mux
1-bit add
Full
Adder
B

CarryOut
Set-less-than? – left as an exercise
361 design.33
 Revised Diagram

° LSB and MSB need to do a little extra

A 32 B 32

a31 b31 a0 b0 4
ALU0 ALU0
M
? co cin co cin
s31 s0
C/L to
produce
select,
comp,
Ovflw 32 c-in
S

361 design.34
 Overflow
Decimal Binary Decimal 2’s Complement
0 0000 0 0000
1 0001 -1 1111
2 0010 -2 1110
3 0011 -3 1101
4 0100 -4 1100
5 0101 -5 1011
6 0110 -6 1010
7 0111 -7 1001
-8 1000
° Examples: 7 + 3 = 10 but ...

° -4 - 5 = -9 but ...

0 1 1 1 1 0
0 1 1 1 7 1 1 0 0 –4
+ 0 0 1 1 3 + 1 0 1 1 –5

1 0 1 0 –6 0 1 1 1 7

361 design.35
 Overflow Detection

° Overflow: the result is too large (or too small) to represent properly
• Example: - 8 < = 4-bit binary number <= 7

° When adding operands with different signs, overflow cannot occur!

° Overflow occurs when adding:

• 2 positive numbers and the sum is negative
• 2 negative numbers and the sum is positive

° On your own: Prove you can detect overflow by:

• Carry into MSB ° Carry out of MSB

0 1 1 1 1 0
0 1 1 1 7 1 1 0 0 –4
+ 0 0 1 1 3 + 1 0 1 1 –5

1 0 1 0 –6 0 1 1 1 7

361 design.36
 Overflow Detection Logic

° Carry into MSB ° Carry out of MSB

• For a N-bit ALU: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
CarryIn0

A0 1-bit Result0 X Y X XOR Y

B0 ALU
0 0 0
CarryIn1 CarryOut0
A1 0 1 1
1-bit Result1
ALU 1 0 1
B1
1 1 0
CarryIn2 CarryOut1
A2 1-bit Result2
B2 ALU
CarryIn3
A3 Overflow
1-bit Result3
B3 ALU

CarryOut3

361 design.37
 Zero Detection Logic

° Zero Detection Logic is just a one BIG NOR gate

• Any non-zero input to the NOR gate will cause its output to be zero
CarryIn0
A0 1-bit Result0
B0 ALU
CarryIn1 CarryOut0
A1 1-bit Result1
B1 ALU
Zero
CarryIn2 CarryOut1
A2 1-bit Result2
B2 ALU
CarryIn3 CarryOut2
A3 1-bit Result3
B3 ALU

CarryOut3

361 design.38
 More Revised Diagram

° LSB and MSB need to do a little extra

A 32 B 32

signed-arith
and cin xor co

a31 b31 a0 b0 4
ALU0 ALU0
M
co cin co cin
s31 s0
C/L to
produce
select,
comp,
Ovflw 32 c-in
S

361 design.39
 But What about Performance?

° Critical Path of n-bit Rippled-carry adder is n*CP

CarryIn0
A0 1-bit Result0
B0 ALU
CarryIn1 CarryOut0
A1 1-bit Result1
B1 ALU
CarryIn2 CarryOut1
A2 1-bit Result2
B2 ALU
CarryIn3 CarryOut2
A3 1-bit Result3
B3 ALU

CarryOut3

Design Trick: throw hardware at it

361 design.40
 The Disadvantage of Ripple Carry

° The adder we just built is called a “Ripple Carry Adder”

• The carry bit may have to propagate from LSB to MSB
• Worst case delay for a N-bit adder: 2N-gate delay

CarryIn0
A0 1-bit Result0
B0 ALU
CarryIn1 CarryOut0 CarryIn
A1 1-bit Result1 A
B1 ALU
CarryIn2 CarryOut1
A2 1-bit Result2
B2 ALU
CarryIn3 CarryOut2
A3 B CarryOut
1-bit Result3
B3 ALU

CarryOut3
361 design.41
 Carry Look Ahead (Design trick: peek)
Cin A B C-out
0 0 0 “kill”
A0 S 0 1 C-in “propagate”
B1 G 1 0 C-in “propagate”
P 1 1 1 “generate”
C1 =G0 + C0 • P0
A S P = A or B
B G G = A and B
P
C2 = G1 + G0 • P1 + C0 • P0 • P1
A S
B G
P
C3 = G2 + G1 • P2 + G0 • P1 • P2 + C0 • P0 • P1 • P2
A S
G G
B
P P

C4 = . . .
361 design.42
 Plumbing as Carry Lookahead Analogy

c0
g0
p0

c1 c0
g0
p0

c0
g1 g0
p1 p0

c2
g1
p1

g2
p2

g3
p3

361 design.43 c4
 The Idea Behind Carry Lookahead (Continue)

° Using the two new terms we just defined:

• Generate Carry at Bit i gi = Ai & Bi
• Propagate Carry via Bit i pi = Ai or Bi

° We can rewrite:
• Cin1 = g0 | (p0 & Cin0)
• Cin2 = g1 | (p1 & g0) | (p1 & p0 & Cin0)
• Cin3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & Cin0)

° Carry going into bit 3 is 1 if

• We generate a carry at bit 2 (g2)
• Or we generate a carry at bit 1 (g1) and
bit 2 allows it to propagate (p2 & g1)
• Or we generate a carry at bit 0 (g0) and
bit 1 as well as bit 2 allows it to propagate (p2 & p1 & g0)
• Or we have a carry input at bit 0 (Cin0) and
bit 0, 1, and 2 all allow it to propagate (p2 & p1 & p0 & Cin0)
361 design.44
 The Idea Behind Carry Lookahead
B1 A1 B0 A0

Cin1
Cin2 1-bit 1-bit Cin0
ALU ALU

Cout1

Cout0
° Recall: CarryOut = (B & CarryIn) | (A & CarryIn) | (A & B)
• Cin2 = Cout1 = (B1 & Cin1) | (A1 & Cin1) | (A1 & B1)
• Cin1 = Cout0 = (B0 & Cin0) | (A0 & Cin0) | (A0 & B0)

° Substituting Cin1 into Cin2:

• Cin2 = (A1 & A0 & B0) | (A1 & A0 & Cin0) | (A1 & B0 & Cin0) |
(B1 & A0 & B0) | (B1 & A0 & Cin0) | (B1 & A0 & Cin0) | (A1 & B1)

° Now define two new terms:

• Generate Carry at Bit i gi = Ai & Bi
• Propagate Carry via Bit i pi = Ai or Bi

361 design.45
 Cascaded Carry Look-ahead (16-bit): Abstraction

C C0
L
A G0
P0
C1 =G0 + C0 • P0

4-bit
Adder

C2 = G1 + G0 • P1 + C0 • P0 • P1

4-bit
Adder

C3 = G2 + G1 • P2 + G0 • P1 • P2 + C0 • P0 • P1 • P2
G
4-bit P
Adder

361 design.46 C4 = . . .
 2nd level Carry, Propagate as Plumbing

g0
p0

p1 g1
p1
p2
p3 g2
p2
P0
g3
p3
G0
361 design.47
 A Partial Carry Lookahead Adder

° It is very expensive to build a “full” carry lookahead adder

• Just imagine the length of the equation for Cin31

° Common practices:
• Connects several N-bit Lookahead Adders to form a big adder
• Example: connects four 8-bit carry lookahead adders to form
a 32-bit partial carry lookahead adder

A[31:24] B[31:24] A[23:16] B[23:16] A[15:8] B[15:8] A[7:0] B[7:0]

8 8 8 8 8 8 8 8

8-bit Carry C24 8-bit Carry C16 8-bit Carry C8 8-bit Carry C0
Lookahead Lookahead Lookahead Lookahead
Adder Adder Adder Adder

8 8 8 8

Result[31:24] Result[23:16] Result[15:8] Result[7:0]

361 design.48
 Design Trick: Guess

CP(2n) = 2*CP(n)
n-bit adder n-bit adder

CP(2n) = CP(n) + CP(mux)

n-bit adder 1 n-bit adder 0 n-bit adder

Cout Carry-select adder

361 design.49
 Carry Select

° Consider building a 8-bit ALU

• Simple: connects two 4-bit ALUs in series

A[3:0] CarryIn
4
Result[3:0]

ALU
4
B[3:0]
4
A[7:4]
4
Result[7:4]
ALU

4
B[7:4]
4
CarryOut

361 design.50
 Carry Select (Continue)

° Consider building a 8-bit ALU

• Expensive but faster: uses three 4-bit ALUs A[3:0] CarryIn
4
Result[3:0]

ALU
0 4
A[7:4] B[3:0]
4 C4
4
X[7:4] Sel
ALU 0
4 1

2 to 1 MUX
B[7:4] A[7:4] Result[7:4]
4 C0 4
Y[7:4] 4

ALU
4 1
B[7:4]
4 C1
0 1 Sel C4
2 to 1 MUX

CarryOut

361 design.51
 Carry Skip Adder: reduce worst case delay

B A4 B A0

4-bit Ripple Adder 4-bit Ripple Adder

P3 P2 S P3 P2 S
P1 P0 P1 P0

Just speed up the slowest case for each block

Exercise: optimal design uses variable block sizes

361 design.52
 Additional MIPS ALU requirements

° Mult, MultU, Div, DivU (next lecture)

=> Need 32-bit multiply and divide, signed and unsigned

° Sll, Srl, Sra (next lecture)

=> Need left shift, right shift, right shift arithmetic by 0 to 31 bits

° Nor (leave as exercise to reader)

=> logical NOR or use 2 steps: (A OR B) XOR 1111....1111

361 design.53
 Elements of the Design Process

° Divide and Conquer (e.g., ALU)

• Formulate a solution in terms of simpler components.
• Design each of the components (subproblems)

° Generate and Test (e.g., ALU)

• Given a collection of building blocks, look for ways of putting
them together that meets requirement

° Successive Refinement (e.g., carry lookahead)

• Solve "most" of the problem (i.e., ignore some constraints or
special cases), examine and correct shortcomings.

° Formulate High-Level Alternatives (e.g., carry select)

• Articulate many strategies to "keep in mind" while pursuing any
one approach.

° Work on the Things you Know How to Do

• The unknown will become “obvious” as you make progress.

361 design.54
 Summary of the Design Process
Hierarchical Design to manage complexity

Top Down vs. Bottom Up vs. Successive Refinement

Importance of Design Representations:

Block Diagrams

Decomposition into Bit Slices top bottom

down up
Truth Tables, K-Maps
mux design
Circuit Diagrams meets at TT
Other Descriptions: state diagrams, timing diagrams, reg xfer, . . .

Optimization Criteria:

Gate Count Area Logic Levels

Delay Power
[Package Count] Fan-in/Fan-out

Pin Out Cost Design time

361 design.55