Laboratory 2

Logic Gates
Design Manual
 Logic Gates Design
To design logic gates, you need to create just the ff:
• INVERTER
• NAND
• NOR

**AND Gate is just NAND Gate and an Inverter

- Instance the NAND Gate and the Inverter from the Account’s Library.
**OR Gate is just NOR Gate and an Inverter
- Instance the NOR Gate and the Inverter from the Account’s Library.

INVERTER
- Same with the Inverter made from previous Laboratory. (Refer
to Laboratory 1 Manual)

Note: Create a cell for each logic gate. Always verify the DRC in every cell layout.
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Logic Gates Design Outline
Part 1: Inverter
Part 2: NAND Gate
Part 3: AND Gate
Part 4: NOR Gate
Part 5: OR Gate
Part 6: Example Combined
Part 7: Test Bench
Part 8: Verification
Part 9: Post Simulation
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Part 1: INVERTER

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 Inverter

Schematic Symbol Layout

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Part 2: NAND GATE

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 NAND Gate

Symbol

Schematic

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NAND Gate

Layout
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Part 3: AND Gate

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AND Gate

Click I to add instance then

select the NAND cell.

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AND Gate

Click I to add instance then

select the Inverter cell.

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 AND Gate
Add pins and wire to finish the schematic design. Click Y to create the symbol.

Schematic

Symbol
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AND Gate
Create the Layout view.

Click I to add instance then

select the NAND cell.

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AND Gate

Click I to add instance then

select the Inverter cell.

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AND Gate

Edit the hierarchy number to

see the various layers. Then
Zoom in or out, you can then
see the inner hierarchy.

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AND Gate

Move the INVERTER cell to overlap

with the NAND cell. Route the
necessary connections. Add the
input and output pins.

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AND Gate

Layout
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Part 4: NOR Gate

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 NOR Gate

Symbol

Schematic

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NOR Gate

Layout
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Part 5: OR Gate

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OR Gate

Click I to add instance

then select the NOR cell.

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OR Gate

Click I to add instance then

select the Inverter cell.

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 OR Gate
Add pins and wire to finish the schematic design. Click Y to create the symbol.

Schematic

Symbol
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OR Gate

Click I to add instance

then select the NOR cell.

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OR Gate

Click I to add instance then

select the Inverter cell.

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OR Gate

Edit the hierarchy number to see

the various layers. Then Zoom in
or out, you can then see the
inner hierarchy.

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OR Gate

Move the INVERTER cell to overlap

with the NOR cell. Route the
necessary connections. Add the
input and output pins.

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OR Gate

Layout
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Part 6: COMBINATION

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 Ex. AND-NOR
Instance the AND Gate and then the NOR Gate.

Schematic

Symbol
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Ex. AND-NOR

Click I to add instance

then select the AND cell.

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Ex. AND-NOR

Click I to add instance

then select the NOR cell.

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Ex. AND-NOR

Move the NOR cell to overlap

with the AND cell. Route the
necessary connections. Add the
input and output pins.

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Ex. AND-NOR

Layout
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Part 7: TEST BENCH

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 Test Bench

Instance the AND-NOR Cell and the rest of the necessary cells for the test
bench. Connect through wires. Check and edit parameter on property window.
Click Q to view property window.
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Simulation

To open model file.

Select Tools Menu the SAE. Click M to add Model

files. Select TT.
Path: account/TSMC0180UM/models/hspice
Select rf018.l

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 Simulation

Click A to add analyses then edit the

parameters. Then select the wires for
the corresponding expressions.

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Pre-Simulation Waveform

Click Ctrl+O to open the file to

view in the waveview. Select
the .tr0 file. Click Ctrl+H to
view the Output view window.

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 Pre-Simulation Waveform

Input on pin A

Input on pin B

Input on pin C

Double click the parameters

needed for analysis and view
the waveform. AND-NOR OUTPUT

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Pre-Simulation Waveform

Use the measurement

tool for the Rise/Fall
Time.

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Pre-Simulation Waveform

Fall Time

Rise Time

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Part 8: VERIFICATION

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DRC Verification

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DRC Setup

Add Runset file.

Path: /home/documents/TSMC_018um/hercules/drc
Then Click OK.

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DRC Result

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LVS Verification

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LVS Setup P.1

Add Runset file.

Path: /home/documents/TSMC_018um/hercules/lvs

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LVS Setup P.2

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 LVS Result
This is verifies that the layout design matches the schematic design.
If not, debug the errors.

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LPE Verification

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LPE Setup P.1

Select Runset file.

Path: /home/documents/TSMC_018um/hercules/starrc

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LPE Setup P.2

Go to the lvs folder from the LVS verification.

Path: /home/account/TSMC018UM/Inverter/hercules_lvs

Select Mapping file.

Path: /home/documents/TSMC_018um/hercules/starrc

Select GRD file.

Path: /home/documents/TSMC_018um/hercules/starrc

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LPE Setup P.3

Select Output Runset Path.

Path: /home/account/TSMC018UM/EE270/AND_NOR/
Create output.sp file.

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 LPE Result
Refer to the Custom Designer Console of This is verifies that the layout design has no errors
in terms of the parasitic extraction.

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Part 9: POST SIMULATION

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Post Simulation P.1
Open on gedit the pre-simulation hspice code on
the simulation folder.
Path:
/home/account/simulation/EE270/AND_NOR_TB/
Schematic/HSPICE/nominal/netlist
Open on gedit the post-simulation hspice code on
the simulation folder.
Path:
/home/account/TSMC018UM/EE270/AND_NOR

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 Post Simulation P.2

From the input.sp, copy the highlighted code to the output.sp file just below
the comments line or the line before the Subckt.
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 Post Simulation P.3

From the input.sp, copy the highlighted code to the output.sp file at the bottom part
or after the Subckt code.
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 Post Simulation P.4

In the output.sp file, rename the Inverter pins in sequenced with the pinning of the
Subckt.

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 Post Simulation P.4

Click Replace on the menu bar. Rename the <space>P<space> with

<space>PCH<space> and <space>N<space> with
<space>NCH<space>
Select Replace All.
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 Post Simulation P.5
Go back to terminal, go to the folder
where the post.sp file is located.
Run Hspice.
Type hspice filename.sp then Enter.

If there are no more errors, job

is concluded.
Type wv & then a waveview
window pops up.

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Post Simulation: Waveform

Open the File

filename.tr0. Click Ctrl+O
to open waveform files
window.

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 Post Simulation: Waveform

Click the
waveforms for
viewing.

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 Post Simulation: Waveform

Use the measurement tool to select

the needed option for measurement.
For this, the Rise/Fall Time is
measured.

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 Pre-Simulation: Waveform

Open the pre-sim file. Path:

/home/account/simulation/EE270/
AND_NOR_TB/schematic/HSPICE/nominal/results
Select the hspice.tr0 file.
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 POST vs PRE-Simulation

PRE-SIM

POST SIM

It is good if your post-simulation is equal to or better than the pre-simulation result. If not,
you can check your layout to improve your output.
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