NSP4201MR6

ESD and Surge Protection

Device
Low Clamping Voltage Surge Protection
Diode Array
The NSP4201MR6 surge protector is designed to protect high speed www.onsemi.com
data lines from ESD, EFT, and lightning surges. 6
Features
• Protection for the Following IEC Standards: 1
IEC 61000−4−2 (ESD) ±30 kV (Contact) TSOP−6
CASE 318G
IEC 61000−4−5 (Lightning) 25 A (8/20 ms)
• Low Clamping Voltage MARKING DIAGRAM
• Low Leakage
• UL Flammability Rating of 94 V−0
• SZ Prefix for Automotive and Other Applications Requiring Unique
42 MG
G
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS 42 = Specific Device Code
M = Date Code
Compliant G = Pb−Free Package
(Note: Microdot may be in either location)
Typical Applications
*Date Code orientation may vary
• High Speed Communication Line Protection depending upon manufacturing location.
• USB 1.1 and 2.0 Power and Data Line Protection
• Digital Video Interface (DVI)
• Monitors and Flat Panel Displays PIN CONFIGURATION AND SCHEMATIC

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) I/O 1 6 I/O

Rating Symbol Value Unit

VN 2 5 VP
Peak Power Dissipation Ppk 500 W
8/20 ms @ TA = 25°C (Note 1)
I/O 3 4 I/O
Operating Junction Temperature Range TJ −40 to +125 °C
Storage Temperature Range Tstg −55 to +150 °C
Lead Solder Temperature − TL
Maximum (10 Seconds) 260 °C ORDERING INFORMATION
IEC 61000−4−2 Air (ESD) ESD ±30 kV Device Package Shipping
IEC 61000−4−2 Contact (ESD) ±30
NSP4201MR6T1G TSOP−6 3000 / Tape &
IEC 61000−4−4 (5/50 ns) EFT 40 A (Pb−Free) Reel
Stresses exceeding those listed in the Maximum Ratings table may damage the
SZNSP4201MR6T1G TSOP−6 3000 / Tape &
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected. (Pb−Free) Reel
1. Non−repetitive current pulse per Figure 1 (Pin 5 to Pin 2) †For information on tape and reel specifications,
including part orientation and tape sizes, please
See Application Note AND8308/D for further description of refer to our Tape and Reel Packaging Specification
survivability specs. Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:

June, 2017 − Rev. 1 NSP4201MR6/D
 NSP4201MR6

ELECTRICAL CHARACTERISTICS I
(TA = 25°C unless otherwise noted)
IF
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VC Clamping Voltage @ IPP
VRWM Working Peak Reverse Voltage VC VBR VRWM
V
IR Maximum Reverse Leakage Current @ VRWM IR VF
IT
VBR Breakdown Voltage @ IT
IT Test Current
IF Forward Current
IPP
VF Forward Voltage @ IF
Ppk Peak Power Dissipation
C Capacitance @ VR = 0 and f = 1.0 MHz
Uni−Directional Surge Protection

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM (Note 2) 5.0 V
Breakdown Voltage VBR IT=1 mA, (Note 3) 6.0 V
Reverse Leakage Current IR VRWM = 5 V 1.0 mA
Clamping Voltage VC IPP = 1 A, Any I/O to GND 8.5 V
(tp = 8/20 ms per Figure 1)
IPP = 5 A, Any I/O to GND 9.0
IPP = 8 A, Any I/O to GND 10
IPP = 25 A, Any I/O to GND 12
Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins and GND 3.0 5.0 pF
Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins 1.5 3.0 pF
2. Surge protection devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater
than the DC or continuous peak operating voltage level.
3. VBR is measured at pulse test current IT.

100 20
tr PEAK VALUE IRSM @ 8 ms
90 18
% OF PEAK PULSE CURRENT

PULSE WIDTH (tP) IS DEFINED

CLAMPING VOLTAGE (V)

80 16
AS THAT POINT WHERE THE
70 PEAK CURRENT DECAY = 8 ms 14
60 12
HALF VALUE IRSM/2 @ 20 ms I/O−GND
50 10
40 8
30 6
tP
20 4
10 2
0 0
0 20 40 60 80 0 5 10 15 20 25 30
t, TIME (ms) PEAK PULSE CURRENT (A)
Figure 1. IEC61000−4−5 8/20 ms Pulse Waveform Figure 2. Clamping Voltage vs. Peak Pulse Current
(tp = 8/20 ms per Figure 1)

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2
 NSP4201MR6

100 20

80 0

60 −20
VOLTAGE (V)

VOLTAGE (V)
40 −40

20 −60

0 −80

−20 −100
−20 0 20 40 60 80 100 120 140 −20 0 20 40 60 80 100 120 140
TIME (ns) TIME (ns)

Figure 3. IEC61000−4−2 +8 kV Contact Clamping Figure 4. IEC61000−4−2 −8 kV Contact Clamping

Voltage Voltage
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
First Peak
Test Volt- Current Current at Current at 100%
Level age (kV) (A) 30 ns (A) 60 ns (A) 90%
1 2 7.5 4 2
2 4 15 8 4 I @ 30 ns
3 6 22.5 12 6
4 8 30 16 8 I @ 60 ns

10%

tP = 0.7 ns to 1 ns

Figure 5. IEC61000−4−2 Spec

ESD Gun Surge Protection Oscilloscope

50 W
Cable 50 W

Figure 6. Diagram of ESD Test Setup

The following is taken from Application Note systems such as cell phones or laptop computers it is not
AND8308/D − Interpretation of Datasheet Parameters clearly defined in the spec how to specify a clamping voltage
for ESD Devices. at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the protection diode over the time domain of an ESD pulse in the
voltage that an IC will be exposed to during an ESD event form of an oscilloscope screenshot, which can be found on
to as low a voltage as possible. The ESD clamping voltage the datasheets for all ESD protection diodes. For more
is the voltage drop across the ESD protection diode during information on how ON Semiconductor creates these
an ESD event per the IEC61000−4−2 waveform. Since the screenshots and how to interpret them please refer to
IEC61000−4−2 was written as a pass/fail spec for larger AND8307/D.

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3
 NSP4201MR6

TYPICAL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

100 5.0
PEAK POWER DISSIPATION (%)

90 4.5

JUNCTION CAPACITANCE (pF)

80 4.0
70 3.5
60 3.0 I/O−GND
50 2.5
40 2.0
30 1.5 I/O−I/O

20 1.0
10 0.5
0 0.0
0 25 50 75 100 125 150 175 200 0 1 2 3 4 5
TA, AMBIENT TEMPERATURE (°C) VBR, REVERSE VOLTAGE (V)
Figure 7. Pulse Derating Curve Figure 8. Junction Capacitance vs Reverse Voltage

Figure 9. RF Insertion Loss

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 NSP4201MR6

TYPICAL APPLICATIONS

RJ45
Connector

TX+ TX+

TX−
TX−
Coupling
PHY Transformers
Ethernet RX+
RX+
(10/100)

RX−

RX−

NSP4201MR6
VCC

GND
N/C N/C

Figure 10. Protection for Ethernet 10/100 (Differential mode)

R1
RTIP

R3
R2
RRING
T1
VCC

T1/E1
TRANCEIVER
NSP4201MR6

R4
TTIP

R5
TRING
T2

Figure 11. TI/E1 Interface Protection

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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

TSOP−6
CASE 318G−02
1 ISSUE V
SCALE 2:1 DATE 12 JUN 2012
NOTES:
D 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
H 2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM

ÉÉ
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
6 5 4 L2 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

ÉÉ
GAUGE
E1 E PLANE GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
1 2 3 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
L
MILLIMETERS
NOTE 5
M C SEATING
b PLANE DIM MIN NOM MAX

e DETAIL Z A 0.90 1.00 1.10

A1 0.01 0.06 0.10
b 0.25 0.38 0.50
c 0.10 0.18 0.26
D 2.90 3.00 3.10
c E 2.50 2.75 3.00
0.05 A E1 1.30 1.50 1.70
e 0.85 0.95 1.05
L 0.20 0.40 0.60
A1 L2 0.25 BSC
DETAIL Z
M 0° − 10°

STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: STYLE 6:

PIN 1. DRAIN PIN 1. EMITTER 2 PIN 1. ENABLE PIN 1. N/C PIN 1. EMITTER 2 PIN 1. COLLECTOR
2. DRAIN 2. BASE 1 2. N/C 2. V in 2. BASE 2 2. COLLECTOR
3. GATE 3. COLLECTOR 1 3. R BOOST 3. NOT USED 3. COLLECTOR 1 3. BASE
4. SOURCE 4. EMITTER 1 4. Vz 4. GROUND 4. EMITTER 1 4. EMITTER
5. DRAIN 5. BASE 2 5. V in 5. ENABLE 5. BASE 1 5. COLLECTOR
6. DRAIN 6. COLLECTOR 2 6. V out 6. LOAD 6. COLLECTOR 2 6. COLLECTOR

STYLE 7: STYLE 8: STYLE 9: STYLE 10: STYLE 11: STYLE 12:

PIN 1. COLLECTOR PIN 1. Vbus PIN 1. LOW VOLTAGE GATE PIN 1. D(OUT)+ PIN 1. SOURCE 1 PIN 1. I/O
2. COLLECTOR 2. D(in) 2. DRAIN 2. GND 2. DRAIN 2 2. GROUND
3. BASE 3. D(in)+ 3. SOURCE 3. D(OUT)− 3. DRAIN 2 3. I/O
4. N/C 4. D(out)+ 4. DRAIN 4. D(IN)− 4. SOURCE 2 4. I/O
5. COLLECTOR 5. D(out) 5. DRAIN 5. VBUS 5. GATE 1 5. VCC
6. EMITTER 6. GND 6. HIGH VOLTAGE GATE 6. D(IN)+ 6. DRAIN 1/GATE 2 6. I/O

STYLE 13: STYLE 14: STYLE 15: STYLE 16: STYLE 17:
PIN 1. GATE 1 PIN 1. ANODE PIN 1. ANODE PIN 1. ANODE/CATHODE PIN 1. EMITTER
2. SOURCE 2 2. SOURCE 2. SOURCE 2. BASE 2. BASE
3. GATE 2 3. GATE 3. GATE 3. EMITTER 3. ANODE/CATHODE
4. DRAIN 2 4. CATHODE/DRAIN 4. DRAIN 4. COLLECTOR 4. ANODE
5. SOURCE 1 5. CATHODE/DRAIN 5. N/C 5. ANODE 5. CATHODE
6. DRAIN 1 6. CATHODE/DRAIN 6. CATHODE 6. CATHODE 6. COLLECTOR

RECOMMENDED GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6X
0.60
XXXAYWG XXX MG
G G
1 1
3.20 6X
0.95 IC STANDARD

XXX = Specific Device Code XXX = Specific Device Code

A =Assembly Location M = Date Code
Y = Year G = Pb−Free Package
0.95 W = Work Week
PITCH G = Pb−Free Package
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

*This information is generic. Please refer to device data sheet
details, please download the ON Semiconductor Soldering and
for actual part marking. Pb−Free indicator, “G” or microdot “
Mounting Techniques Reference Manual, SOLDERRM/D.
G”, may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB14888C Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: TSOP−6 PAGE 1 OF 1

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