Comparative Study for Some Memristor models in

Different Circuit Applications

Mahmoud Ali1, Seif Mohamed1, Mohamed Elshafey1, and Hassan Mostafa1,2
1
University of Science and Technology, Nanotechnology and Nanoelectronics Department, Zewail City of
Science and Technology, October Gardens, 6th of October, Giza 12578, Egypt
2
Depatment of Electronics and Communication Engineering Department, Cairo University, Giza 12613, Egypt
[email protected], [email protected], [email protected], [email protected]

Abstract—Memristors modeling and applications while spintronic models are CHEN [4] and domain-wall (DW)
are a hot topic in research nowadays, mostly because of based model (SHERIF) [5].
their unique hysteresis behavior, nanoscale properties and
non-volatility. However, there is a scarcity in comparisons A. Resistive Memristors
between different models on circuit based work. In this TEAM model is a simplification of the Simmons Tunnel Barrier
paper, four models are examined: two of resistive model [6], as Simmons model is quite complex, however, it is
memristors (TEAM/VTEAM model and ZC modification) the most accurate model based on the physics of the memristor.
and the other two of spintronic memristors (CHEN model Simmons model defines the state variable as the width of an
and Domain-Wall (DW) based model). Functions and electron tunnel barrier which is modeled in series with a resistor
operations of these four models are compared in three to represent the memristor’s active layer. TEAM model uses the
applications ranging from memory, analog and logic same physics in Simmons model, yet with polynomial
circuits. Lastly it is concluded that the choice of the model dependence rather than exponential dependence of the rate of
may rely on the type of circuit used. change of the state variable. It has a current threshold for the
Keywords—Resistive memristor, Spintronic switching mechanism to take place as well as the flexibility to
memristor, Domain-wall, window function, Read time, Write use either linear or nonlinear I-V relation. It can be modeled to
time, Saturation time, Relaxation based oscillator, Delay. any resistive memristor unlike Simmons model.

I. INTRODUCTION VTEAM is another version of TEAM model with the same

physics, however, it has a voltage threshold rather than
Memristor was firstly introduced in 1971 by Leon Chua as the TEAM’s current threshold and its importance lies in its
fourth fundamental circuit element [1]. The uniqueness of the applicability in memory circuits [7].
memristor stems from its I-V characteristics as it has a
hysteresis behavior that gives it the ability to remember its ZC model [8] is a modification with a new window function
resistance, hence its name: memory-resistance [1]. According (Butterworth) on Stanford model which models the switching
to Chua the equations govern the memristor are (1, 2) mechanisms of bipolar memristive devices especially in RRAM
applications [9]. The state variable is represented by the gap
( ) = ( , ) ∗ ( ) (1) size and its physics is described as the growth of conductive
filament. The advantage of ZC is that the new window function
= ( , ) (2)
diminishes the ability of the state variable to overcome the
assigned lower and upper boundaries while limiting the state
Where is defined as the state variable which is different from
variable by the oxide thickness. This results in introducing
model to model, ( , ) is the resistance of the memristor or
resistive bands instead of the use of ROFF and RON as single
memristance. It was until 2008 that a team at HP fabricated the
values which is more accurate to the experimental results.
first memristor [2]. Since then, different models were
introduced to explain the behavior of memristors. The models B. Spintronic Memristors
differ according to the type of memristor, as there are resistive
(thin films memristors) such as TiOx [2] and IMEC HfOx-based The idea of spintronic memristor is that the current flux entering
memristor [3], and spintronic memristors that depend on the the memristor with certain electron spin that changes the spin
magnetization vector such as CHEN model [4] and domain- and magnetization state of the device. This change moves what
wall model [5]. In this paper, the resistive models used are is called domain wall which separates the free layer FL which
TEAM model [6], VTEAM [7] and ZC modification model [8], has a changing magnetization direction, and pinned layer PL
which has fixed magnetization direction. In addition, the
domain wall is the state variable. This movement changes the

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resistance of the device. Two spintronic models are chosen,
CHEN and Domain Wall-based models which are explained
briefly below. = ∗ (3)
( )

CHEN model uses a current in plane (CIP) structure where two , where
series resistors are connected that represent the resistances in
both the parallel and antiparallel regions. It ignores the = (4)
resistance of domain wall and uses simplified LLG (Landau
Lifshitz Gilbert) equation [4]. Whereas domain wall model is a
generalized model that can model both CIP and CPP (current
perpendicular to plane) structures. It takes into account the
domain wall resistance, thermal effect on magnetization vectors
and resistances and also models the full LLGS (Landau Lifshitz
Gilbert Slonczewski) equation, which adds a torque term- spin
transfer torque (STT) which results from the change of angular
momentum of spin-polarized electrons. In addition of having
voltage dependence on giant magnetoresistance to tunneling Fig. 1 Memory circuit based on 1M adopted from [10]
magnetoresistance ratio (GMR/TMR), respectively [5]
Second is the sense amplifier stage where the logic value is read
This work is divided into three sections covering the circuit from the output of a comparator that compares Vx with a
applications: section II. Memory circuit, section III. Memristor reference voltage Vref, which is half Vin.
based relaxation oscillator, section IV. Logic circuit and the last
The applied read pulse (Vin) consists of two pulses of the same
section is the conclusion. The parameters for memristors used
magnitude and width but opposite polarities to ensure the net
in the circuit applications differ from model to model and they injected flux is zero, which in turn won’t affect the memristor’s
are extracted as follows: VTEAM and ZC models are obtained state. For the integrity of the read/write data, a safety margin
from [8] where the parameters are fitted to the experimental should be introduced while defining logic values. Therefore, a
data of the IMEC HfOx-based memristor. While the parameters logic one is defined to be when the memristor’s normalized
of TEAM model are extracted from [6]. The parameters of the state variable w/D is between 0 and 0.4, and a logic zero is
Chen model is obtained from [4], while DW-based model is defined to be when w/D is between 0.6 and 1, or vice versa
obtained from [5] using CPP structure TMR based memristor. depending on the model. The region from 0.4 to 0.6 in all the
The circuits used for comparison and simulation are explained models is treated as undefined logic and should be avoided to
in their distinct sections. They were simulated on Cadence account for noise and for data integrity.
Virtuoso using Verilog-A models For the write operations, the models are subjected to an applied
II. MEMORY CIRCUIT pulse with an amplitude of |2.3| volts with the polarity changing
depending on the required logic value. The reason for choosing
In this section, the performance of the four memristor models, this specific magnitude is that ZC model won’t write for smaller
previously introduced, is compared in a single memory cell magnitudes which is mentioned in the simulation results. Due
based on 1-memristor (1M) memory. The memory cell circuitry to differences between the Verilog-A models, the significance
is obtained from [10,11] and shown in Fig. 1. The circuit’s R/W of w/D differs from one model to the other as well as the
enable switch moves between three states: write-where a logic significance of the polarity of the pulse on the logic value being
value “1” or “0” is being written to the memristor, read-where written. For DW-based model, w/D = 1 means that R(w) = Ron
the state of the memristor is sensed to read the logic stored in it, (logic “1”) while in chen model w/D = 1 means R(w) =
and floating-where no operation is being done to the memristor Roff (logic “0”), both of the spintronic models need a negative
and, hence, no change in its state occurs. applied voltage to write “1” and a positive voltage to write “0”.
For the ZC and VTEAM models, when w/D = 1, R(w) = Roff .
For the write mechanism, a voltage pulse is applied to the Both models require a positive pulse to write “1” and a negative
memristor. The pulse width must be long enough to ensure the pulse to write “0”. The write time is calculated when w/D
injected flux is sufficient for full switching of the state function reaches 1 from 0 or 0 from 1. For ZC model the state variable
to the desired logic value. The read mechanism is more was normalized to the gapmax parameter. Since the gap is not
complicated as it requires performing the operation without limited to the assigned upper and lower limits, during write 0,
affecting the memristor’s state. The read operation is divided w/D exceeds the value of 1, however, the write time is measured
into two stages. First is the convert stage where a read pulse at the time the upper boundary is reached.
(Vin) is applied to sense the memristor’s state then a signal is
produced (Vx ), which is the output of a voltage divider between For the read operation, circuit parameters used are shown in
the memristance R(w) and Rx. Vx is calculated through: Table. 1. An ideal comparator from Cadence’s ahdLib library
was used in the sense amplifier stage. The only parameter that

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differs from one model to the other is Rx. Calculating Rx for
models with defined Ron and Roff (VTEAM, Chen, DW) is
straightforward. Nonetheless, for ZC model the determination
of Rx took an experimental approach since Ron and Roff exist as
narrow bands. During simulation, the true logic value is read
through the second half of the pulse Vo to get the right result.
The read time is calculated when the 90 % of the maximum
value of Vo is reached in case of reading “1”, and at 10% of the
maximum value of Vo is reached in case of reading “0”. 2.a
Table.1
Read Circuit Parameters

Rise and
Read circuit Vin Period
Fall Rx (Ω)
parameters amplitude of Vin
time
VTEAM 625K
ZC- +-500
1.5 ns 100 ps 199K 2.b
Modification mV
Chen 5.5K
DW-based 1.795K

Fig. 2 shows the transient analysis simulation. It is noted in the

read simulations that the read pulse does not inject enough flux
to perturb the memristors’ states in either halves of the pulse.
However, Chen model is the only exception due to its high
2.c
sensitivity which makes it prone to read disturbance more than
the other models. Table. II concludes the simulation results. For Fig. 2 Transient analysis simulation. (a) Read 1 scheme and
the two spintronic models; Chen exhibited lower power the state variable behavior, (b) Read 0 scheme and the state
consumption and faster read time while the DW-based model variable behavior, (c) State variable behavior for write 1 and
write 0 operations.
performed better in the read operations and proved less prone
to read disturbance. During write “1” and “0” ZC model’s gap III. MEMRISTOR BASED RELAXATION OSCILLATOR
was very slightly affected by pulse amplitudes less than |2.3|
The memristor was introduced in many oscillator circuits as a
volts yet at |2.3| volts the model shows an abrupt transition after
substitute for resistors and capacitors [12-15]. The use of
a certain amount of flux is injected. The VTEAM model
memristor in oscillator circuits differs according to the nature
exhibited a highly asymmetric behavior in the write time as well
and the design of the circuit, so memristors work as substitute
as the power which exhibited the greediest operation of all
to resistances in wein oscillators family as in [13]. In [12] the
during writing “1”. Although the VTEAM simulation is fast, it
memristor was used as a substitute to the capacitor in low
dissipates huge power when compared by the relatively slow
frequency applications in relaxation oscillator circuits. The
and less power greedy ZC. During read ZC consumes more
behavior of increasing and decreasing memristor resistance due
power but in the order of 10^-6 watt which is almost
to the direction of current passing the memristor, works as the
insignificant.
energy storing property of capacitor so the capacitor can be
TABLE. II replaced with memristor. In this paper we used a memristor
Simulation Results based relaxation circuit [16]. This circuit is shown in Fig. 3. It
DW- consists of a memristor, two comparators, AND gate, inverter
Results Table Chen VTEAM ZC and a resistor. The comparators and AND gate act as a Schmitt
based
Write 1 time (ns) 29.55 8.876 4.136 11.53 trigger circuit to fixate the memristor resistance between
, and ensure an oscillation with the mechanism of
Write 1 Power (W) 3.044E-03 6.320E-04 1.466E-02 3.451E-3
positive feedback using the resistance that acts as a voltage
Write 0 time (ns) 29.41 8.85 0.9127 10.57 divider. The inverter works as a substitute to the ground and
Write 0 Power (W) 3.001E-03 5.781E-04 1.247E-04 2.366E-4 ensures an extreme voltages between 0,1 applying at the end of
Read 1 time (ns) 0.8025 0.8047 0.8008 0.8008 the memristor. The comparators and logic gates were ideal
Read 1 Power (W) 2.86E-04 2.58E-04 2.34E-04 2.37E-04 components from the ahdlLib library in Cadence with AND
Read 0 time (ns) 0.80024 0.80584 0.8001 0.8002 gate Vlow = -1, Vhigh = 1, inverter Vlow = 0, Vhigh = 1 and
Read 0 Power (W) 2.636E-04 2.539E-04 2.351E-04 2.344E-4 comparator sigout_high = 1, sigout_low = 0 and sigout_offset
=0

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 As the power = where = , in the circuit is
constant for all models, so power is inversely proportional to
- memristor’s resistance. The change in is related to the
model and how the state function behaves for every model,
Table IV clarifies that ZC modification and Domain wall model
consume more power than TEAM model and CHEN model
respectively as their , is smaller as shown in Fig .5.
Fig. 3 Memristor-based relaxation circuit adopted from [16]
TABLE IV.
In [15] the oscillation frequency is given by = RESULTS OF FOUR MODELS OF THE SIMULATION OF THE CIRCUIT
DOMAIN
Where is the output high voltage = 1, is a coefficient TEAM ZC CHEN
WALL
depending on the voltage ratios of , , is a memristor Frequency
4.975E+08 4.973E+08 4.975E+08 4.974E+08
(HZ)
model coefficient depends on the dopant mobility, , saturation
5.185E-09 7.528E-09 5.550E-09 9.726E-09
and the memristor length. So it depends on the model used. Time (sec)
(Ω) 8.333E+05 3.296E+04 2.448E+04 1.514E+04
The parameters of the circuit were the same except only (Ω) 3.378E+05 9.513E+03 5.704E+03 2.265E+03
which changed in resistive modeling to spintronic modeling as Power
1.823E-06 3.166E-05 3.817E-05 4.841E-05
presented in Table. III. This change was accustomed after (Watt)
iterations on the simulation environment to get the best
oscillation.
TABLE III
PARAMETERS OF MEMRISTOR-BASED RELAXATION CIRCUIT
5.5 KΩ
for Spintronic 500m V
Memristors
for Resistive Memristors 600 mV
-600 mV
(a) (b)
Fig .5 Current Behavior with Time (a) ZC and TEAM
The transient analysis as shown in Fig. 4 of the four models give models current behaviors (b) Chen and Domain Wall Current behaviors.
comparable frequency with changes in 0.02 % in spintronic
models and 0.04 % in resistive models due to the fact that IV. MEMRISTOR RATIOED LOGIC
frequency is dependent on the circuit parameters which are The logic operations are at the heart of any computational
constant among the four models and the memristor coefficient
device. For long, the CMOS logic operation was the most logic
which is comparable to the four models due to fitting the four
models to each other. Fig. 4 shows that the four models not on family used due to its great properties. The advent of
the same phase, that due to the fact that time required to reach memristors allows integrating memristors with CMOS which
oscillation is different from model to another, as it is depending saves physical layers and increase logic density [17]. The MRL
on the way that the model works. In addition, same frequency or memristor ratioed logic is a proposed logic to integrate
is observed in the models as anticipated. CMOS with memristor. The integration is performed as the
memristors do the logic operation with a CMOS inverter to
provide the negation of the logic operation. NOR gate is
simulated using the four models. The power, delay and the
behavior of such circuit are studied.

The NOR gate is shown in Fig. 6 below. The principle of

operation depends on the property of memristor changing
resistance according to the direction of current passing it, as
shown in Fig. 7, the opposite operation happens at Vin2 = 1, Vin1
=0. The two memristors work as voltage divider, and give an
output voltage depending on the memristances values:
, . This output voltage is then inverted using CMOS
inverter. We simulate the four models in a Cadence virtuoso
Fig. 4 Transient analysis of the models
with TSMC 130 nm CMOS technology file. The CMOS has

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130 nm length and 2 um width. The avg. power and delay are in the extremes in ZC and GMR voltage dependences that is
summarized in Table V. The results show substantial covered by Domain Wall model.
improvements in delay in ZC over TEAM; this can be attributed
to more current being drawn in ZC as observed in oscillator VI. ACKNOWLEDGEMENT
circuit. It is worthy to mention that power in ZC did not increase This work was partially funded by ONE Lab at Zewail City of
as it did in oscillator circuit, this may be attributed to the way Science and Technology and at Cairo University, NTRA,
ZC model deals with transitions from high to low in digital ITIDA, and ASRT.
logic. For CHEN and DW models, they are comparable with
slightly improvement for DW model as it incorporates GMR VII. REFERENCES
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