CAD for VLSI Design

(CS61068, 3-1-0)

http://144.16.192.60/~isg/CAD/

Course Outline
• Introduction: VLSI design flow, challenges. Verilog/VHDL:
introduction and use in synthesis, modeling combinational and
sequential logic, writing test benches.
• Logic synthesis: Two-level and multilevel gate-level optimization .
Binary decision diagrams. Basic concepts of high-level synthesis:
partitioning, scheduling, allocation and binding. Technology
mapping.
• Synthesis of reversible logic circuits: Basic concepts of reversible
circuits and synthesis. Exact, transformation based, and ESOP based
synthesis methods.
• Physical design automation: Review of MOS/CMOS fabrication
technology. VLSI design styles: full-custom, standard-cell, gate-array
and FPGA. Physical design automation algorithms: floor-planning,
placement, routing, compaction, design rule check, power and delay
estimation, clock and power routing, etc. Special considerations for
analog and mixed-signal designs.

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 References
1. R.H. Katz, “Contemporary logic design”, Addison-Wesley Pub. Co., 1993.
2. M.J.S. Smith, “Application-specific integrated circuits”, Addison-Wesley Pub. Co.,
1997.
3. S. Ramachandran, “Digital VLSI systems design”, Springer, 2007.
4. M.L. Bushnell and V.D. Agrawal, “Essentials of Electronic Testing”, Kluwer Academic
Publishers, 2000.
5. J. Bhasker, “Verilog VHDL synthesis: a practical primer”, B S Publications, 1998.
6. D.D. Gajski, N.D. Dutt, A.C. Wu and A.Y. Yin, “High-level synthesis: introduction to
chip and system design”, Kluwer Academic Publishers, 1992.
7. M. Sarrafzadeh and C.K. Wong, “An introduction to physical design”, McGraw Hill,
1996.
8. N.A. Sherwani, “Algorithms for VLSI physical design automation”, Kluwer Academic
Publishers, 1999.
9. S.M. Sait and H. Youssef, “VLSI physical design automation: theory and practice”,
World Scientific Pub. Co., 1999.

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Some Points to Note

• Breakup of marks:
– Mid-sem : 30%
– End-sem: 40%
– Assignments: 20%
– Class test: 510

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 Digital Circuit Design Flow

Digital Design Process

• Design complexity increasing rapidly
– Increased size and complexity.
– CAD tools are essential.
– Too many CAD tools to choose from.
• The present trend
– Standardize the design flow.

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 What is design flow?
• Standardized design procedure
– Starting from the design idea down to the actual
implementation.
• Encompasses many steps
– Specification
– Synthesis
– Simulation
– Layout
– Testability analysis
– Many more ……

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• New CAD tools

– Based on Hardware Description Language (HDL).
– HDLs provide formats for representing the outputs of
various design steps.
– An HDL based CAD tool transforms from its HDL input into
a HDL output which contains more hardware information.
• Behavioral level to register transfer level
• Register transfer level to gate level
• Gate level to transistor level

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 Two Competing HDLs
1. Verilog
2. VHDL

In this course we would be concentrating on

Verilog only

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Simplistic View of Design Flow

Design Idea

Behavioral Design
Flow Graph, Pseudo Code
Data Path Design
Bus/Register Structure

Logic Design
Gate/F-F Netlist

Physical Design
Transistor Layout
Manufacturing

Chip / Board

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 Design Representation
• A design can be represented at various levels from
three different angles:
1. Behavioral
2. Structural
3. Physical

• Can be represented by Y-diagram.

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BEHAVIORAL STRUCTURAL
DOMAIN DOMAIN

Programs Gates
Specifications Adders
Truth table Registers

Transistors / Layouts
Cells
Chips / Boards

PHYSICAL
DOMAIN
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 Behavioral Representation
• Specifies how a particular design should respond to
a given set of inputs.
• May be specified by
– Boolean equations
– Tables of input and output values
– Algorithms written in standard HLL like C
– Algorithms written in special HDL like Verilog

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Behavioral Representation :: Example

A n-bit adder is constructed by cascading n 1-bit adders.

A 1-bit adder has
- two operand inputs A and B
- a carry input C
- a carry output Cy
- a sum output S

S = A.B′′.C′′ + A′′.B′′.C + A′′.B.C′′ + A.B.C

Cy = A.B + A.C + B.C

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 An algorithmic level description of Cy

module carry (cy, a, b, c);

input a, b, c;
output cy;
assign
cy = (a&b) | (b&c) | (c&a);
endmodule

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Boolean behavioral specification for Cy

primitive carry (cy, a, b, c);
input a, b, c;
output cy;
table
// a b c co
1 1 ? : 1;
1 ? 1 : 1;
? 1 1 : 1;
0 0 ? : 0;
0 ? 0 : 0;
? 0 0 : 0;
endtable
endprimitive

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 Structural Representation
• Specifies how components are interconnected.
• In general, the description is a list of modules and
their interconnects:
– called netlist.
– can be specified at various levels.

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• At the structural level, the levels of abstraction are

– the module level
– the gate level
– the switch level
– the circuit level
• In each level more detail is revealed about the
implementation.

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 add4

add add add add

carry sum carry sum carry sum carry sum

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Structural representation :: example

4-bit adder

module add4 (s, cy4, cy_in, x, y);

input [3:0] x, y;
input cy_in;
output [3:0] s;
output cy4;
wire [2:0] cy_out;
add B0 (cy_out[0], s[0], x[0], y[0], ci);
add B1 (cy_out[1], s[1], x[1], y[1], cy_out[0]);
add B2 (cy_out[2], s[2], x[2], y[2], cy_out[1]);
add B3 (cy4, s[3], x[3], y[3], cy_out[2]);
endmodule

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module add (cy_out, sum, a, b, cy_in);
input a, b, cy_in;
output sum, cy_out;
sum s1 (sum, a, b, cy_in);
carry c1 (cy_out, a, b, cy_in);
endmodule

module carry (cy_out, a, b, cy_in);

input a, b, cy_in;
output cy_out;
wire t1, t2, t3;
and g1 (t1, a, b);
and g2 (t2, a, c);
and g3 (t3, b, c);
or g4 (cy_out, t1, t2, t3);
endmodule

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Physical Representation
• The lowest level of physical specification.
– Photo-mask information required by the various processing
steps in the fabrication process.
• At the module level, the physical layout for the 4-bit
adder may be defined by a rectangle or polygon,
and a collection of ports.

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 Physical representation -- example
Imaginary physical description for 4-bit adder
module add4;
input x[3:0], y[3:0];
input cy_in;
output s[3:0];
output cy4;
boundary [0, 0, 130, 500];
port x[0] aluminum width = 1 origin = [0, 35];
port y[0] aluminum width = 1 origin = [0, 85];
port cy_in polysilicon width = 2 origin = [70, 0];
port s[0] aluminum width = 1 origin = [120, 65];

add a0 origin = [0, 0];

add a1 origin = [0, 120];

endmodule

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Digital IC Design Flow: A quick look

Design Entry
Pre-layout
Simulation
Logical
Logic Synthesis design
(front-end
CAD)
Partitioning

Post-layout Floorplanning Physical

Simulation
design
(back-end
Placement
CAD)
Circuit
Extraction Routing

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