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Tutorial - 3 - Aug, 2020: Q. No. Question Description Mark S

This document provides a tutorial for a Computer Architecture and Organization course. It includes 5 multiple choice questions about memory systems concepts like memory access time, memory chips needed based on required memory size, speedup from cache memory, memory addressability and word length based on address bits and memory size. The questions cover topics like calculating latency and bandwidth for a memory access, determining number of RAM and ROM chips needed, calculating speedup from cache memory, determining memory addressability and word length, and calculating average access time for a memory hierarchy system.

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Shrey Srivastava
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32 views1 page

Tutorial - 3 - Aug, 2020: Q. No. Question Description Mark S

This document provides a tutorial for a Computer Architecture and Organization course. It includes 5 multiple choice questions about memory systems concepts like memory access time, memory chips needed based on required memory size, speedup from cache memory, memory addressability and word length based on address bits and memory size. The questions cover topics like calculating latency and bandwidth for a memory access, determining number of RAM and ROM chips needed, calculating speedup from cache memory, determining memory addressability and word length, and calculating average access time for a memory hierarchy system.

Uploaded by

Shrey Srivastava
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Tutorial – 3 –

Aug, 2020
Programme : B.Tech – Semester : Interim 2021-2022
Course : Computer Architecture and Organization Code : CSE2003
Faculty : Dr. Trapti Sharma Slot/Class No. : A11
Time : 30min Max. Marks : 10

Answer all the


Questions

Q. No. Question Description Mark


s

1 Consider a memory system that takes 20 ns to service the access of a 2


single 32-bit word. Calculate latency and bandwidth.

2
A computer employs RAM chips of 512*8 and ROM chips of 2048*8.
2
The computer system needs 8K bytes of RAM, 32K bytes of ROM.
How many RAM and ROM chips are needed.
3 Consider a 2-level memory hierarchy consisting of a cache memory M1 and
the main memory M2. Suppose that the cache is 6 times faster than the main
memory, and the cache can be used 90% of the time. How much speedup do 2
we gain by using the cache?
4
A CPU has a 16 bit address for memory addressing: (a) What is the memory
addressability of the CPU ? (b) If the memory has a total capacity of 2 MB, what is
2
the word length of the memory?

5 2
Consider a system having three levels of memory, a cache memory, a semiconductor
main memory, and a magnetic disk secondary memory, if the access times of the
memories are 10 ns, 50 ns, and 1 us, respectively. The cache hit ratio is 80% and the
main memory hit ratio is 85%. Compute the average access time for this system.



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