Scribd
Upload
16 views

Assignment 2

The document describes designing a parity generator and checker circuit based on the student's ID number. The key steps are: 1) Convert the sum of the ID digits to binary. This gives the number of input bits for the circuits. 2) Design and verify the truth table of a parity generator circuit that outputs the parity (odd or even number of 1s) of the inputs. 3) Design and verify the truth table of a corresponding parity checker circuit that checks the parity output by the generator.

Uploaded by

MD. Akif Rahman
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
16 views

Assignment 2

The document describes designing a parity generator and checker circuit based on the student's ID number. The key steps are: 1) Convert the sum of the ID digits to binary. This gives the number of input bits for the circuits. 2) Design and verify the truth table of a parity generator circuit that outputs the parity (odd or even number of 1s) of the inputs. 3) Design and verify the truth table of a corresponding parity checker circuit that checks the parity output by the generator.

Uploaded by

MD. Akif Rahman
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 38

Name: __Siam Ibne Masud_______________________

ID:___1911261__________________ Sec:_02_____

Independent University, Bangladesh (IUB)


Dept. of Electrical and Electronic Engineering
Digital Logic Design Lab
EEE 232L

Assignment 02 Total Marks: 05

1. Design a parity generator & corresponding parity checker circuit with the following conditions &
hints. Add all the digits of your student ID then find out the minimum number of binary bits (n)
required to represent the sum. Convert your sum into binary number (B).
a. Now design & draw the parity generator circuit with “n” inputs system. [1.0]

My Student ID= 1911261


Sum = 1+9+1+1+2+6+1 = 21
Decimal = B(21)10
∴Converting to Binary = B(10101)2
So minimum binary bits, n = 5
b. Develop & verify the truth table through simulation of your designed circuit.
Mark “B” on the Truth Table & describe B(inputs-outputs) with proper logic. [1.5]

[B is the Parity]

(B3⊕B2) B=
B4 B3 B2 B1 B0 B3⊕B2 B1⊕B0 ⊕ [(B3⊕B2)⊕(B1⊕B0)]
(B1⊕B0) ⊕
[B4]

0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 1 1 1
0 0 0 1 0 0 1 1 1
0 0 0 1 1 0 0 0 0
0 0 1 0 0 1 0 1 1
0 0 1 0 1 1 1 0 0
0 0 1 1 0 1 1 0 0
0 0 1 1 1 1 0 1 1
0 1 0 0 0 1 0 1 1
0 1 0 0 1 1 1 0 0
0 1 0 1 0 1 1 0 0
0 1 0 1 1 1 0 1 1
0 1 1 0 0 0 0 0 0
0 1 1 0 1 0 1 1 1
0 1 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0 1
1 0 0 0 1 0 1 1 0
1 0 0 1 0 0 1 1 0
1 0 0 1 1 0 0 0 1
1 0 1 0 0 1 0 1 0
1 0 1 0 1 1 1 0 1
1 0 1 1 0 1 1 0 1
1 0 1 1 1 1 0 1 0
1 1 0 0 0 1 0 1 0
1 1 0 0 1 1 1 0 1
1 1 0 1 0 1 1 0 1
1 1 0 1 1 1 0 1 0
1 1 1 0 0 0 0 0 1
1 1 1 0 1 0 1 1 0
1 1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 0 1
Verifying the parity Generator truth table using simulation:
B4 B3 B2 B1 B0 B
0 0 0 0 0 0

B4 B3 B2 B1 B0 B
0 0 0 0 1 1

B4 B3 B2 B1 B0 B
0 0 0 1 0 1
B4 B3 B2 B1 B0 B
0 0 0 1 1 0

B4 B3 B2 B1 B0 B
0 0 1 0 0 1

B4 B3 B2 B1 B0 B
0 0 1 0 1 0
B4 B3 B2 B1 B0 B
0 0 1 1 0 0

B4 B3 B2 B1 B0 B
0 0 1 1 1 1

B4 B3 B2 B1 B0 B
0 1 0 0 0 1
B4 B3 B2 B1 B0 B
0 1 0 0 1 0

B4 B3 B2 B1 B0 B
0 1 0 1 0 0

B4 B3 B2 B1 B0 B
0 1 0 1 1 1
B4 B3 B2 B1 B0 B
0 1 1 0 0 0

B4 B3 B2 B1 B0 B
0 1 1 0 1 1

B4 B3 B2 B1 B0 B
0 1 1 1 0 1
B4 B3 B2 B1 B0 B
0 1 1 1 1 0

B4 B3 B2 B1 B0 B
1 0 0 0 0 1

B4 B3 B2 B1 B0 B
1 0 0 0 1 0
B4 B3 B2 B1 B0 B
1 0 0 1 0 0

B4 B3 B2 B1 B0 B
1 0 0 1 1 1

B4 B3 B2 B1 B0 B
1 0 1 0 0 0
B4 B3 B2 B1 B0 B
1 0 1 0 1 1

B4 B3 B2 B1 B0 B
1 0 1 1 0 1

B4 B3 B2 B1 B0 B
1 0 1 1 1 0
B4 B3 B2 B1 B0 B
1 1 0 0 0 0

B4 B3 B2 B1 B0 B
1 1 0 0 1 1

B4 B3 B2 B1 B0 B
1 1 0 1 0 1
B4 B3 B2 B1 B0 B
1 1 0 1 1 0

B4 B3 B2 B1 B0 B
1 1 1 0 0 1

B4 B3 B2 B1 B0 B
1 1 1 0 1 0
B4 B3 B2 B1 B0 B
1 1 1 1 0 0

B4 B3 B2 B1 B0 B
1 1 1 1 1 1

∴ The Parity Generator Outputs in Simulations are verified

There are 5 inputs,


At first, we solved the output for the first 2 inputs (B0 & B1).
Then, we solved the output for the next 2 inputs (B2 & B3).
These 2 outputs are used in another XOR gate as 2 two inputs.
Lastly, we connected the last input (B4) and connected it with the output (B3⊕B2)⊕(B1⊕B0)
To generate the parity (B).
This circuit is verified by showing its truth table and simulations.
It is also verified as number of ODD HIGH inputs resulted parity = 1.

(This circuit can also be called a 4 bit parity checker circuit)


c. Now repeat (a.) & (b.) for corresponding parity checker circuit. [2.5]

Separating the truth table and the simulations of parity checker into 2 Equal parts as the
table has 64 combinations:

- When parity = 0
- When parity = 1
-
Truth table of parity checker
when parity, B = 0

B’ is the checker output


B3⊕B2 X
B(parity) B4 B3 B2 B1 B0 B4⊕B B3⊕B2 B1⊕B0 ⊕ ⊕ B’ = Y⊕B
B1⊕B0 (B4⊕B)
=X =Y
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 1 1 1 1
0 0 0 0 1 0 0 0 1 1 1 1
0 0 0 0 1 1 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 1 1 1
0 0 0 1 0 1 0 1 1 0 0 0
0 0 0 1 1 0 0 1 1 0 0 0
0 0 0 1 1 1 0 1 0 1 1 1
0 0 1 0 0 0 0 1 0 1 1 1
0 0 1 0 0 1 0 1 1 0 0 0
0 0 1 0 1 0 0 1 1 0 0 0
0 0 1 0 1 1 0 1 0 1 1 1
0 0 1 1 0 0 0 0 0 0 0 0
0 0 1 1 0 1 0 0 1 1 1 1
0 0 1 1 1 0 0 0 1 1 1 1
0 0 1 1 1 1 0 0 0 0 0 0
0 1 0 0 0 0 1 0 0 0 1 1
0 1 0 0 0 1 1 0 1 1 0 0
0 1 0 0 1 0 1 0 1 1 0 0
0 1 0 0 1 1 1 0 0 0 1 1
0 1 0 1 0 0 1 1 0 1 0 0
0 1 0 1 0 1 1 1 1 0 1 1
0 1 0 1 1 0 1 1 1 0 1 1
0 1 0 1 1 1 1 1 0 1 0 0
0 1 1 0 0 0 1 1 0 1 0 0
0 1 1 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 1 1 1 0 1 1
0 1 1 0 1 1 1 1 0 1 0 0
0 1 1 1 0 0 1 0 0 0 1 1
0 1 1 1 0 1 1 0 1 1 0 0
0 1 1 1 1 0 1 0 1 1 0 0
0 1 1 1 1 1 1 0 0 0 1 1
Truth table of parity checker
when parity, B = 1

B’ is the checker output


B3⊕B2 X
B(parity) B4 B3 B2 B1 B0 B4⊕B B3⊕B2 B1⊕B0 ⊕ ⊕ B’ = Y⊕B
B1⊕B0 (B4⊕B)
=X =Y
1 0 0 0 0 0 1 0 0 0 0 1
1 0 0 0 0 1 1 0 1 1 1 0
1 0 0 0 1 0 1 0 1 1 1 0
1 0 0 0 1 1 1 0 0 0 0 1
1 0 0 1 0 0 1 1 0 1 1 0
1 0 0 1 0 1 1 1 1 0 0 1
1 0 0 1 1 0 1 1 1 0 0 1
1 0 0 1 1 1 1 1 0 1 1 0
1 0 1 0 0 0 1 1 0 1 1 0
1 0 1 0 0 1 1 1 1 0 0 1
1 0 1 0 1 0 1 1 1 0 0 1
1 0 1 0 1 1 1 1 0 1 1 0
1 0 1 1 0 0 1 0 0 0 0 1
1 0 1 1 0 1 1 0 1 1 1 0
1 0 1 1 1 0 1 0 1 1 1 0
1 0 1 1 1 1 1 0 0 0 0 1
1 1 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 1 0 0 1 1 1 1
1 1 0 0 1 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 0 0 0 0
1 1 0 1 0 0 0 1 0 1 1 1
1 1 0 1 0 1 0 1 1 0 0 0
1 1 0 1 1 0 0 1 1 0 0 0
1 1 0 1 1 1 0 1 0 1 1 1
1 1 1 0 0 0 0 1 0 1 1 1
1 1 1 0 0 1 0 1 1 0 0 0
1 1 1 0 1 0 0 1 1 0 0 0
1 1 1 0 1 1 0 1 0 1 1 1
1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 1 0 0 1 1 1 1
1 1 1 1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0 0 0 0
Verifying the Parity Checker truth table using simulation: When parity = 0
B(Parity) B4 B3 B2 B1 B0 B’
0 0 0 0 0 0 0

B(Parity) B4 B3 B2 B1 B0 B’
0 0 0 0 0 1 1

B(Parity) B4 B3 B2 B1 B0 B’
0 0 0 0 1 0 1
B(Parity) B4 B3 B2 B1 B0 B’
0 0 0 0 1 1 0

B(Parity) B4 B3 B2 B1 B0 B’
0 0 0 1 0 0 1

B(Parity) B4 B3 B2 B1 B0 B’
0 0 0 1 0 1 0
B(Parity) B4 B3 B2 B1 B0 B’
0 0 0 1 1 0 0

B(Parity) B4 B3 B2 B1 B0 B’
0 0 0 1 1 1 1

B(Parity) B4 B3 B2 B1 B0 B’
0 0 1 0 0 0 1
B(Parity) B4 B3 B2 B1 B0 B’
0 0 1 0 0 1 0

B(Parity) B4 B3 B2 B1 B0 B’
0 0 1 0 1 0 0

B(Parity) B4 B3 B2 B1 B0 B’
0 0 1 0 1 1 1
B(Parity) B4 B3 B2 B1 B0 B’
0 0 1 1 0 0 0

B(Parity) B4 B3 B2 B1 B0 B’
0 0 1 1 0 1 1

B(Parity) B4 B3 B2 B1 B0 B’
0 0 1 1 1 0 1
B(Parity) B4 B3 B2 B1 B0 B’
0 0 1 1 1 1 0

B(Parity) B4 B3 B2 B1 B0 B’
0 1 0 0 0 0 1

B(Parity) B4 B3 B2 B1 B0 B’
0 1 0 0 0 1 0
B(Parity) B4 B3 B2 B1 B0 B’
0 1 0 0 1 0 0

B(Parity) B4 B3 B2 B1 B0 B’
0 1 0 0 1 1 1

B(Parity) B4 B3 B2 B1 B0 B’
0 1 0 1 0 0 0
B(Parity) B4 B3 B2 B1 B0 B’
0 1 0 1 0 1 1

B(Parity) B4 B3 B2 B1 B0 B’
0 1 0 1 1 0 1

B(Parity) B4 B3 B2 B1 B0 B’
0 1 0 1 1 1 0
B(Parity) B4 B3 B2 B1 B0 B’
0 1 1 0 0 0 0

B(Parity) B4 B3 B2 B1 B0 B’
0 1 1 0 0 1 1

B(Parity) B4 B3 B2 B1 B0 B’
0 1 1 0 1 0 1
B(Parity) B4 B3 B2 B1 B0 B’
0 1 1 0 1 1 0

B(Parity) B4 B3 B2 B1 B0 B’
0 1 1 1 0 0 1

B(Parity) B4 B3 B2 B1 B0 B’
0 1 1 1 0 1 0
B(Parity) B4 B3 B2 B1 B0 B’
0 1 1 1 1 0 0

B(Parity) B4 B3 B2 B1 B0 B’
0 1 1 1 1 1 1
Verifying the Parity Checker truth table using simulation: When parity = 1
B(Parity) B4 B3 B2 B1 B0 B’
1 0 0 0 0 0 1

B(Parity) B4 B3 B2 B1 B0 B’
1 0 0 0 0 1 0

B(Parity) B4 B3 B2 B1 B0 B’
1 0 0 0 1 0 0
B(Parity) B4 B3 B2 B1 B0 B’
1 0 0 0 1 1 1

B(Parity) B4 B3 B2 B1 B0 B’
1 0 0 1 0 0 0

B(Parity) B4 B3 B2 B1 B0 B’
1 0 0 1 0 1 1
B(Parity) B4 B3 B2 B1 B0 B’
1 0 0 1 1 0 1

B(Parity) B4 B3 B2 B1 B0 B’
1 0 0 1 1 1 0

B(Parity) B4 B3 B2 B1 B0 B’
1 0 1 0 0 0 0
B(Parity) B4 B3 B2 B1 B0 B’
1 0 1 0 0 1 1

B(Parity) B4 B3 B2 B1 B0 B’
1 0 1 0 1 0 1

B(Parity) B4 B3 B2 B1 B0 B’
1 0 1 0 1 1 0
B(Parity) B4 B3 B2 B1 B0 B’
1 0 1 1 0 0 1

B(Parity) B4 B3 B2 B1 B0 B’
1 0 1 1 0 1 0

B(Parity) B4 B3 B2 B1 B0 B’
1 0 1 1 1 0 0
B(Parity) B4 B3 B2 B1 B0 B’
1 0 1 1 1 1 1

B(Parity) B4 B3 B2 B1 B0 B’
1 1 0 0 0 0 0

B(Parity) B4 B3 B2 B1 B0 B’
1 1 0 0 0 1 1
B(Parity) B4 B3 B2 B1 B0 B’
1 1 0 0 1 0 1

B(Parity) B4 B3 B2 B1 B0 B’
1 1 0 0 1 1 0

B(Parity) B4 B3 B2 B1 B0 B’
1 1 0 1 0 0 1
B(Parity) B4 B3 B2 B1 B0 B’
1 1 0 1 0 1 0

B(Parity) B4 B3 B2 B1 B0 B’
1 1 0 1 1 0 0

B(Parity) B4 B3 B2 B1 B0 B’
1 1 0 1 1 1 1
B(Parity) B4 B3 B2 B1 B0 B’
1 1 1 0 0 0 1

B(Parity) B4 B3 B2 B1 B0 B’
1 1 1 0 0 1 0

B(Parity) B4 B3 B2 B1 B0 B’
1 1 1 0 1 0 0
B(Parity) B4 B3 B2 B1 B0 B’
1 1 1 0 1 1 1

B(Parity) B4 B3 B2 B1 B0 B’
1 1 1 1 0 0 0

B(Parity) B4 B3 B2 B1 B0 B’
1 1 1 1 0 1 1
B(Parity) B4 B3 B2 B1 B0 B’
1 1 1 1 1 0 1

B(Parity) B4 B3 B2 B1 B0 B’
1 1 1 1 1 1 0

∴ The Parity Checker Outputs in Simulations are verified

There are 6 inputs,


Since number of inputs are even, therefore we connected each pair of inputs with 1 XOR gate.
Then, we solved the output for the first pair of inputs (B0 & B1)
Then, we solved the output for the second pair of inputs (B2 & B3)
Then, we solved the output for the third pair of inputs (B4 & B parity)

The 2 outputs of (B0 & B1) and (B2 & B3) are used in another XOR gate as 2 two inputs.
Then, we connected the output of (B4 ⊕ B parity) as input with the solved output (B3⊕B2)⊕(B1⊕B0)
to achieve the final output for checking the parity (B).
This circuit is verified by showing its truth table and simulations.
It is also verified as number of ODD HIGH inputs resulted checker output = 0

You might also like