Institute of

Applied Microelectronics & Computer Engineering

Selected Topics of VLSI Design

Part 3: Multiplication

Prof. Dr.-Ing. Dirk Timmermann

[email protected]
Outline
● 3.1 Fundamentals
o Unsigned Multiplication, 2’s Complement Multiplication

● 3.2 Unsigned Braun-Array Multiplier

● 3.3 Signed Pezaris-Array Multiplier

● 3.4 Booth Multiplier

● 3.5 Booth-Wallace Multiplier

● 3.6 Evaluation

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3.1 Fundamentals
● Like paper-and-pencil multiplication
● Multiplication of 2 n-bit operands A and B yields 2𝑛-bit product

3.1.1 Unsigned Multiplication

𝑃 𝐴·𝐵 𝑎2 · 𝑏2 𝑎 𝑏 ·2
(see 1.6.2.2 Recursive,
associative function)
𝑃 𝑎 ·𝐵 , 𝑃 𝑃2

● Multiply algorithm:
Note:
1) Generate n partial products 𝑃
𝑃 Product
2) Sum up all partial products 𝑃 𝑃 Partial product
 Shift-and-Add 𝑝 Bit 𝑖 of product
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3.1.1 Unsigned Multiplication (cont’d)
a) Recursive (shift-and-add) using one accumulator
B
n

ai
1 Metric:
*
i = 0, ..., n ‐1 Shift left by i bits
𝐴 𝑂 𝑛 ⋅ log 𝑛
𝑇 𝑂 log 𝑛
CPA
CLK
Reg 𝐿 𝑛
2n
P
b) Serial (shift-and-add) using linear array of CSAs
o All pi are generated in parallel
B
a0
*
a1 CSA Metric:
A
a2
*
CSA
Carry and 
sum
𝐴 𝑂 𝑛
* 𝑇 𝑂 𝑛 log 𝑛
a3 CSA

*
CSA
4n input
of CPA
CPA
CPA
2n

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3.1.1 Unsigned Multiplication (cont’d)
c) Parallel using multi-operand adder (tree-structure)
B

a0
a1 *
A
a2 * Metric:
a3 * 𝐴 𝑂 𝑛
* 𝑇 𝑂 log 𝑛

CSA ‐ Tree

2n 2n

CPA
2n

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3.1.2 Two’s Complement Multiplication
● Option 1
o Complement operands before and result after multiplication
 Unsigned multiplication algorithm applicable

● Option 2
o Use dedicated two’s complement multipliers
 e.g., Braun, Pezaris, Baugh-Wooley

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3.2 Unsigned Braun-Array Multiplier
● E.g., for 4-bit operands
a0b3 a0b2 a0b1 a0b0
a1b3 a1b2 a1b1 a1b0
a2b3 a2b2 a2b1 a2b0
a3b3 a3b2 a3b1 a3b0
p7 p6 p5 p4 p3 p2 p1 p0

bi bi Metric:
ai Braun ai 𝐴 8𝑛 11𝑛 𝑂 𝑛
pi (LSBs) 𝑇 6𝑛 9 𝑂 𝑛
pi pi (MSBs)

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3.2 Unsigned Braun-Array Multiplier (cont’d)
● 4-bit Braun-Array multiplier
b3 b2 b1 b0
a0

p0
a1
1 HA HA HA
p1

a2

FA FA FA
p2

a3
2
FA FA FA
CSA p3
CPA
FA FA FA
3

p7 p6 p5 p4
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3.3 Signed Pezaris-Array Multiplier
● Modified Braun-Array multiplier, here shown for 4-bit operands
● MSB = sign bit  value = -1

-a0b3 a0b2 a0b1 a0b0

-a1b3 a1b2 a1b1 a1b0
-a2b3 a2b2 a2b1 a2b0
a3b3 -a3b2 -a3b1 -a3b0
p7 p6 p5 p4 p3 p2 p1 p0

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3.3 Signed Pezaris-Array Multiplier (cont’d)
● Four cases for partial product Pi
a) 3 pos. operands  regular FA
𝑎 𝑏 𝑐
b) 2 pos., 1 neg. operands
o 1 𝑠𝑢𝑚 2
o Weight of sum-bit: -1
o Weight of cout: +2
𝑎 𝑏 𝑐 2𝑐 𝑠

c) 1 pos., 2 neg. operands

o 2 𝑠𝑢𝑚 1
o Weight of sum-bit: +1
o Weight of cout: -2
𝑎 𝑏 𝑐 2𝑐 𝑠
d) 3 neg. operands  logically identical to a)
 identical implementation: regular FA
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3.3 Signed Pezaris-Array Multiplier (cont’d)

● b) and c) have same implementation

𝑠 𝑎⊗𝑏⊗𝑐 (regular FA)

𝑐 𝑎∧𝑏 ∨ 𝑎∧𝑐 ∨ 𝑏∧𝑐 (modified FA)

● Approach: replace FA in regions , , and  with modified

FA (input a = •)
● Same structure like Braun multiplier (except modified FA)
b3 b2 b1 b0
a0

p0
a1
1 HA HA HA
p1
a2

FA FA FA
p2

a3
2
FA FA FA
CSA p3
CPA
FA FA FA
3

p7 p6 p5 p4
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3.4 Booth Multiplier
● Observation: multiplication delay 𝑓 ⋕ partial products 𝑃 𝑓 𝑛
o For every 0 in ai one row can be omitted in array!
o  Recoding of ai to maximize number of 0’s
(𝑎 ∈ 0,1 → 𝑎 ′ ∈ 1,0,1 )
● Two possibilities:
a) ai always constant: CSD-Recoding (1/3 of area on average)
b) ai variable: modified Booth-Encoding (1/2 of area)
 Booth Multiplier bi
n
ai‘
Mod.Booth-

* Metric:
Recoding

ai n/2 partial
* products Pi 𝐴 𝑂 𝑛
* 𝑇 𝑂 𝑛 log 𝑛
*
Parallel CSA - array
calculation
CPA

● Note: “horizontal” data compression can be achieved with Dadda-

multiplier (Booth = “vertical” compression)
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3.5 Booth-Wallace Multiplier
● take Booth multiplier and replace CSA-array with Wallace-tree (see
2.4.3)

Metric:
𝐴 5 … 6𝑛
𝑇 𝑂 𝑙𝑜𝑔 𝑛 ; → 𝑇 2 · 𝑙𝑜𝑔 𝑛

CSA tree CPA

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3.6 Evaluation of multiplier architectures

Trough-
Latency Area Regularity Pipelining
put
Recursive -- o ++ - (control needed) --
Braun + o o ++ ++
Booth + + o + +
Booth-
+ ++ -- - +
Wallace

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